// SPDX-License-Identifier: ISC /* * Copyright (c) 2010 Broadcom Corporation */ #include <linux/types.h> #include <linux/atomic.h> #include <linux/kernel.h> #include <linux/kthread.h> #include <linux/printk.h> #include <linux/pci_ids.h> #include <linux/netdevice.h> #include <linux/interrupt.h> #include <linux/sched/signal.h> #include <linux/mmc/sdio.h> #include <linux/mmc/sdio_ids.h> #include <linux/mmc/sdio_func.h> #include <linux/mmc/card.h> #include <linux/mmc/core.h> #include <linux/semaphore.h> #include <linux/firmware.h> #include <linux/module.h> #include <linux/bcma/bcma.h> #include <linux/debugfs.h> #include <linux/vmalloc.h> #include <linux/unaligned.h> #include <defs.h> #include <brcmu_wifi.h> #include <brcmu_utils.h> #include <brcm_hw_ids.h> #include <soc.h> #include "sdio.h" #include "chip.h" #include "firmware.h" #include "core.h" #include "common.h" #include "bcdc.h" #define DCMD_RESP_TIMEOUT … #define CTL_DONE_TIMEOUT … /* watermark expressed in number of words */ #define DEFAULT_F2_WATERMARK … #define CY_4373_F2_WATERMARK … #define CY_4373_F1_MESBUSYCTRL … #define CY_43012_F2_WATERMARK … #define CY_43012_MES_WATERMARK … #define CY_43012_MESBUSYCTRL … #define CY_4339_F2_WATERMARK … #define CY_4339_MES_WATERMARK … #define CY_4339_MESBUSYCTRL … #define CY_43455_F2_WATERMARK … #define CY_43455_MES_WATERMARK … #define CY_43455_MESBUSYCTRL … #define CY_435X_F2_WATERMARK … #define CY_435X_F1_MESBUSYCTRL … #ifdef DEBUG #define BRCMF_TRAP_INFO_SIZE … #define CBUF_LEN … /* Device console log buffer state */ #define CONSOLE_BUFFER_MAX … struct rte_log_le { … }; struct rte_console { … }; #endif /* DEBUG */ #include <chipcommon.h> #include "bus.h" #include "debug.h" #include "tracepoint.h" #define TXQLEN … #define TXHI … #define TXLOW … #define PRIOMASK … #define TXRETRIES … #define BRCMF_RXBOUND … #define BRCMF_TXBOUND … #define BRCMF_TXMINMAX … #define MEMBLOCK … #define MAX_DATA_BUF … #define BRCMF_FIRSTREAD … /* SBSDIO_DEVICE_CTL */ /* 1: device will assert busy signal when receiving CMD53 */ #define SBSDIO_DEVCTL_SETBUSY … /* 1: assertion of sdio interrupt is synchronous to the sdio clock */ #define SBSDIO_DEVCTL_SPI_INTR_SYNC … /* 1: mask all interrupts to host except the chipActive (rev 8) */ #define SBSDIO_DEVCTL_CA_INT_ONLY … /* 1: isolate internal sdio signals, put external pads in tri-state; requires * sdio bus power cycle to clear (rev 9) */ #define SBSDIO_DEVCTL_PADS_ISO … /* 1: enable F2 Watermark */ #define SBSDIO_DEVCTL_F2WM_ENAB … /* Force SD->SB reset mapping (rev 11) */ #define SBSDIO_DEVCTL_SB_RST_CTL … /* Determined by CoreControl bit */ #define SBSDIO_DEVCTL_RST_CORECTL … /* Force backplane reset */ #define SBSDIO_DEVCTL_RST_BPRESET … /* Force no backplane reset */ #define SBSDIO_DEVCTL_RST_NOBPRESET … /* direct(mapped) cis space */ /* MAPPED common CIS address */ #define SBSDIO_CIS_BASE_COMMON … /* maximum bytes in one CIS */ #define SBSDIO_CIS_SIZE_LIMIT … /* cis offset addr is < 17 bits */ #define SBSDIO_CIS_OFT_ADDR_MASK … /* manfid tuple length, include tuple, link bytes */ #define SBSDIO_CIS_MANFID_TUPLE_LEN … #define SD_REG(field) … /* SDIO function 1 register CHIPCLKCSR */ /* Force ALP request to backplane */ #define SBSDIO_FORCE_ALP … /* Force HT request to backplane */ #define SBSDIO_FORCE_HT … /* Force ILP request to backplane */ #define SBSDIO_FORCE_ILP … /* Make ALP ready (power up xtal) */ #define SBSDIO_ALP_AVAIL_REQ … /* Make HT ready (power up PLL) */ #define SBSDIO_HT_AVAIL_REQ … /* Squelch clock requests from HW */ #define SBSDIO_FORCE_HW_CLKREQ_OFF … /* Status: ALP is ready */ #define SBSDIO_ALP_AVAIL … /* Status: HT is ready */ #define SBSDIO_HT_AVAIL … #define SBSDIO_CSR_MASK … #define SBSDIO_AVBITS … #define SBSDIO_ALPAV(regval) … #define SBSDIO_HTAV(regval) … #define SBSDIO_ALPONLY(regval) … #define SBSDIO_CLKAV(regval, alponly) … /* intstatus */ #define I_SMB_SW0 … #define I_SMB_SW1 … #define I_SMB_SW2 … #define I_SMB_SW3 … #define I_SMB_SW_MASK … #define I_SMB_SW_SHIFT … #define I_HMB_SW0 … #define I_HMB_SW1 … #define I_HMB_SW2 … #define I_HMB_SW3 … #define I_HMB_SW_MASK … #define I_HMB_SW_SHIFT … #define I_WR_OOSYNC … #define I_RD_OOSYNC … #define I_PC … #define I_PD … #define I_DE … #define I_RU … #define I_RO … #define I_XU … #define I_RI … #define I_BUSPWR … #define I_XMTDATA_AVAIL … #define I_XI … #define I_RF_TERM … #define I_WF_TERM … #define I_PCMCIA_XU … #define I_SBINT … #define I_CHIPACTIVE … #define I_SRESET … #define I_IOE2 … #define I_ERRORS … #define I_DMA … /* corecontrol */ #define CC_CISRDY … #define CC_BPRESEN … #define CC_F2RDY … #define CC_CLRPADSISO … #define CC_XMTDATAAVAIL_MODE … #define CC_XMTDATAAVAIL_CTRL … /* SDA_FRAMECTRL */ #define SFC_RF_TERM … #define SFC_WF_TERM … #define SFC_CRC4WOOS … #define SFC_ABORTALL … /* * Software allocation of To SB Mailbox resources */ /* tosbmailbox bits corresponding to intstatus bits */ #define SMB_NAK … #define SMB_INT_ACK … #define SMB_USE_OOB … #define SMB_DEV_INT … /* tosbmailboxdata */ #define SMB_DATA_VERSION_SHIFT … /* * Software allocation of To Host Mailbox resources */ /* intstatus bits */ #define I_HMB_FC_STATE … #define I_HMB_FC_CHANGE … #define I_HMB_FRAME_IND … #define I_HMB_HOST_INT … /* tohostmailboxdata */ #define HMB_DATA_NAKHANDLED … #define HMB_DATA_DEVREADY … #define HMB_DATA_FC … #define HMB_DATA_FWREADY … #define HMB_DATA_FWHALT … #define HMB_DATA_FCDATA_MASK … #define HMB_DATA_FCDATA_SHIFT … #define HMB_DATA_VERSION_MASK … #define HMB_DATA_VERSION_SHIFT … /* * Software-defined protocol header */ /* Current protocol version */ #define SDPCM_PROT_VERSION … /* * Shared structure between dongle and the host. * The structure contains pointers to trap or assert information. */ #define SDPCM_SHARED_VERSION … #define SDPCM_SHARED_VERSION_MASK … #define SDPCM_SHARED_ASSERT_BUILT … #define SDPCM_SHARED_ASSERT … #define SDPCM_SHARED_TRAP … /* Space for header read, limit for data packets */ #define MAX_HDR_READ … #define MAX_RX_DATASZ … /* Bump up limit on waiting for HT to account for first startup; * if the image is doing a CRC calculation before programming the PMU * for HT availability, it could take a couple hundred ms more, so * max out at a 1 second (1000000us). */ #undef PMU_MAX_TRANSITION_DLY #define PMU_MAX_TRANSITION_DLY … /* Value for ChipClockCSR during initial setup */ #define BRCMF_INIT_CLKCTL1 … /* Flags for SDH calls */ #define F2SYNC … #define BRCMF_IDLE_ACTIVE … #define BRCMF_IDLE_INTERVAL … #define KSO_WAIT_US … #define MAX_KSO_ATTEMPTS … #define BRCMF_SDIO_MAX_ACCESS_ERRORS … #ifdef DEBUG /* Device console log buffer state */ struct brcmf_console { … }; struct brcmf_trap_info { … }; #endif /* DEBUG */ struct sdpcm_shared { … }; struct sdpcm_shared_le { … }; /* dongle SDIO bus specific header info */ struct brcmf_sdio_hdrinfo { … }; /* * hold counter variables */ struct brcmf_sdio_count { … }; /* misc chip info needed by some of the routines */ /* Private data for SDIO bus interaction */ struct brcmf_sdio { … }; /* clkstate */ #define CLK_NONE … #define CLK_SDONLY … #define CLK_PENDING … #define CLK_AVAIL … #ifdef DEBUG static int qcount[NUMPRIO]; #endif /* DEBUG */ #define DEFAULT_SDIO_DRIVE_STRENGTH … #define RETRYCHAN(chan) … /* Limit on rounding up frames */ static const uint max_roundup = …; #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT #define ALIGNMENT … #else #define ALIGNMENT … #endif enum brcmf_sdio_frmtype { … }; #define SDIOD_DRVSTR_KEY(chip, pmu) … /* SDIO Pad drive strength to select value mappings */ struct sdiod_drive_str { … }; /* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = …; /* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = …; /* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = …; /* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_DEF(…) …; /* Note the names are not postfixed with a1 for backward compatibility */ BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; BRCMF_FW_CLM_DEF(…) …; /* firmware config files */ MODULE_FIRMWARE(…) …; /* per-board firmware binaries */ MODULE_FIRMWARE(…) …; static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = …; #define TXCTL_CREDITS … static void pkt_align(struct sk_buff *p, int len, int align) { … } /* To check if there's window offered */ static bool data_ok(struct brcmf_sdio *bus) { … } /* To check if there's window offered */ static bool txctl_ok(struct brcmf_sdio *bus) { … } static int brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) { … } #define HOSTINTMASK … /* Turn backplane clock on or off */ static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) { … } /* Change idle/active SD state */ static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) { … } /* Transition SD and backplane clock readiness */ static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) { … } static int brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) { … } #ifdef DEBUG static inline bool brcmf_sdio_valid_shared_address(u32 addr) { … } static int brcmf_sdio_readshared(struct brcmf_sdio *bus, struct sdpcm_shared *sh) { … } static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) { … } #else static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) { } #endif /* DEBUG */ static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) { … } static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) { … } static void brcmf_sdio_txfail(struct brcmf_sdio *bus) { … } /* return total length of buffer chain */ static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) { … } static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) { … } /* * brcmfmac sdio bus specific header * This is the lowest layer header wrapped on the packets transmitted between * host and WiFi dongle which contains information needed for SDIO core and * firmware * * It consists of 3 parts: hardware header, hardware extension header and * software header * hardware header (frame tag) - 4 bytes * Byte 0~1: Frame length * Byte 2~3: Checksum, bit-wise inverse of frame length * hardware extension header - 8 bytes * Tx glom mode only, N/A for Rx or normal Tx * Byte 0~1: Packet length excluding hw frame tag * Byte 2: Reserved * Byte 3: Frame flags, bit 0: last frame indication * Byte 4~5: Reserved * Byte 6~7: Tail padding length * software header - 8 bytes * Byte 0: Rx/Tx sequence number * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag * Byte 2: Length of next data frame, reserved for Tx * Byte 3: Data offset * Byte 4: Flow control bits, reserved for Tx * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet * Byte 6~7: Reserved */ #define SDPCM_HWHDR_LEN … #define SDPCM_HWEXT_LEN … #define SDPCM_SWHDR_LEN … #define SDPCM_HDRLEN … /* software header */ #define SDPCM_SEQ_MASK … #define SDPCM_SEQ_WRAP … #define SDPCM_CHANNEL_MASK … #define SDPCM_CHANNEL_SHIFT … #define SDPCM_CONTROL_CHANNEL … #define SDPCM_EVENT_CHANNEL … #define SDPCM_DATA_CHANNEL … #define SDPCM_GLOM_CHANNEL … #define SDPCM_TEST_CHANNEL … #define SDPCM_GLOMDESC(p) … #define SDPCM_NEXTLEN_MASK … #define SDPCM_NEXTLEN_SHIFT … #define SDPCM_DOFFSET_MASK … #define SDPCM_DOFFSET_SHIFT … #define SDPCM_FCMASK_MASK … #define SDPCM_WINDOW_MASK … #define SDPCM_WINDOW_SHIFT … static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) { … } static inline bool brcmf_sdio_fromevntchan(u8 *swheader) { … } static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, struct brcmf_sdio_hdrinfo *rd, enum brcmf_sdio_frmtype type) { … } static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) { … } static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, struct brcmf_sdio_hdrinfo *hd_info) { … } static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) { … } static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, bool *pending) { … } static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) { … } static void brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) { … } /* Pad read to blocksize for efficiency */ static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) { … } static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) { … } static void brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) { … } static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) { … } /* * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for * bus layer usage. */ /* flag marking a dummy skb added for DMA alignment requirement */ #define ALIGN_SKB_FLAG … /* bit mask of data length chopped from the previous packet */ #define ALIGN_SKB_CHOP_LEN_MASK … static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, struct sk_buff_head *pktq, struct sk_buff *pkt, u16 total_len) { … } /** * brcmf_sdio_txpkt_prep - packet preparation for transmit * @bus: brcmf_sdio structure pointer * @pktq: packet list pointer * @chan: virtual channel to transmit the packet * * Processes to be applied to the packet * - Align data buffer pointer * - Align data buffer length * - Prepare header * Return: negative value if there is error */ static int brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, uint chan) { … } /** * brcmf_sdio_txpkt_postp - packet post processing for transmit * @bus: brcmf_sdio structure pointer * @pktq: packet list pointer * * Processes to be applied to the packet * - Remove head padding * - Remove tail padding */ static void brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) { … } /* Writes a HW/SW header into the packet and sends it. */ /* Assumes: (a) header space already there, (b) caller holds lock */ static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, uint chan) { … } static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) { … } static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) { … } static bool brcmf_chip_is_ulp(struct brcmf_chip *ci) { … } static void brcmf_sdio_bus_stop(struct device *dev) { … } static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) { … } static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) { … } static void brcmf_sdio_dpc(struct brcmf_sdio *bus) { … } static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) { … } static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) { … } static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) { … } #ifdef DEBUG #define CONSOLE_LINE_MAX … static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) { … } #endif /* DEBUG */ static int brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) { … } #ifdef DEBUG static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, struct sdpcm_shared *sh) { … } static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, struct sdpcm_shared *sh) { … } static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, struct sdpcm_shared *sh) { … } static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) { … } static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) { … } static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) { … } static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) { … } static void brcmf_sdio_debugfs_create(struct device *dev) { … } #else static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) { return 0; } static void brcmf_sdio_debugfs_create(struct device *dev) { } #endif /* DEBUG */ static int brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) { … } #ifdef DEBUG static bool brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, u8 *ram_data, uint ram_sz) { … } #else /* DEBUG */ static bool brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, u8 *ram_data, uint ram_sz) { return true; } #endif /* DEBUG */ static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, const struct firmware *fw) { … } static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, void *vars, u32 varsz) { … } static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, const struct firmware *fw, void *nvram, u32 nvlen) { … } static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus) { … } static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) { … } /* enable KSO bit */ static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) { … } static int brcmf_sdio_bus_preinit(struct device *dev) { … } static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) { … } static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, size_t mem_size) { … } void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) { … } void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr) { … } static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) { … } static void brcmf_sdio_dataworker(struct work_struct *work) { … } static void brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, struct brcmf_chip *ci, u32 drivestrength) { … } static int brcmf_sdio_buscoreprep(void *ctx) { … } static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, u32 rstvec) { … } static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) { … } static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) { … } static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = …; static bool brcmf_sdio_probe_attach(struct brcmf_sdio *bus) { … } static int brcmf_sdio_watchdog_thread(void *data) { … } static void brcmf_sdio_watchdog(struct timer_list *t) { … } static int brcmf_sdio_get_blob(struct device *dev, const struct firmware **fw, enum brcmf_blob_type type) { … } static int brcmf_sdio_bus_reset(struct device *dev) { … } static void brcmf_sdio_bus_remove(struct device *dev) { … } static const struct brcmf_bus_ops brcmf_sdio_bus_ops = …; #define BRCMF_SDIO_FW_CODE … #define BRCMF_SDIO_FW_NVRAM … #define BRCMF_SDIO_FW_CLM … static void brcmf_sdio_firmware_callback(struct device *dev, int err, struct brcmf_fw_request *fwreq) { … } static struct brcmf_fw_request * brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) { … } struct brcmf_sdio *brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) { … } /* Detach and free everything */ void brcmf_sdio_remove(struct brcmf_sdio *bus) { … } void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) { … } int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) { … }
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