/* * Copyright (c) 2010 Broadcom Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef _BRCM_TYPES_H_ #define _BRCM_TYPES_H_ #include <linux/types.h> #include <linux/io.h> #define WL_CHAN_FREQ_RANGE_2G … #define WL_CHAN_FREQ_RANGE_5GL … #define WL_CHAN_FREQ_RANGE_5GM … #define WL_CHAN_FREQ_RANGE_5GH … /* boardflags */ /* Board has gpio 9 controlling the PA */ #define BFL_PACTRL … /* Not ok to power down the chip pll and oscillator */ #define BFL_NOPLLDOWN … /* Board supports the Front End Module */ #define BFL_FEM … /* Board has an external LNA in 2.4GHz band */ #define BFL_EXTLNA … /* Board has no PA */ #define BFL_NOPA … /* Power topology uses BUCKBOOST */ #define BFL_BUCKBOOST … /* Board has FEM and switch to share antenna w/ BT */ #define BFL_FEM_BT … /* Power topology doesn't use CBUCK */ #define BFL_NOCBUCK … /* Power topology uses PALDO */ #define BFL_PALDO … /* Board has an external LNA in 5GHz band */ #define BFL_EXTLNA_5GHz … /* boardflags2 */ /* Board has an external rxbb regulator */ #define BFL2_RXBB_INT_REG_DIS … /* Flag to implement alternative A-band PLL settings */ #define BFL2_APLL_WAR … /* Board permits enabling TX Power Control */ #define BFL2_TXPWRCTRL_EN … /* Board supports the 2X4 diversity switch */ #define BFL2_2X4_DIV … /* Board supports 5G band power gain */ #define BFL2_5G_PWRGAIN … /* Board overrides ASPM and Clkreq settings */ #define BFL2_PCIEWAR_OVR … #define BFL2_LEGACY … /* 4321mcm93 board uses Skyworks FEM */ #define BFL2_SKWRKFEM_BRD … /* Board has a WAR for clock-harmonic spurs */ #define BFL2_SPUR_WAR … /* Flag to narrow G-band PLL loop b/w */ #define BFL2_GPLL_WAR … /* Tx CCK pkts on Ant 0 only */ #define BFL2_SINGLEANT_CCK … /* WAR to reduce and avoid clock-harmonic spurs in 2G */ #define BFL2_2G_SPUR_WAR … /* Flag to widen G-band PLL loop b/w */ #define BFL2_GPLL_WAR2 … #define BFL2_IPALVLSHIFT_3P3 … /* Use internal envelope detector for TX IQCAL */ #define BFL2_INTERNDET_TXIQCAL … /* Keep the buffered Xtal output from radio "ON". Most drivers will turn it * off without this flag to save power. */ #define BFL2_XTALBUFOUTEN … /* * board specific GPIO assignment, gpio 0-3 are also customer-configurable * led */ /* bit 9 controls the PA on new 4306 boards */ #define BOARD_GPIO_PACTRL … #define BOARD_GPIO_12 … #define BOARD_GPIO_13 … /* **** Core type/rev defaults **** */ #define D11CONF … #define NCONF … #define LCNCONF … #define SSLPNCONF … /******************************************************************** * Phy/Core Configuration. Defines macros to check core phy/rev * * compile-time configuration. Defines default core support. * * ****************************************************************** */ /* Basic macros to check a configuration bitmask */ #define CONF_HAS(config, val) … #define CONF_MSK(config, mask) … #define MSK_RANGE(low, hi) … #define CONF_RANGE(config, low, hi) … #define CONF_IS(config, val) … #define CONF_GE(config, val) … #define CONF_GT(config, val) … #define CONF_LT(config, val) … #define CONF_LE(config, val) … /* Wrappers for some of the above, specific to config constants */ #define NCONF_HAS(val) … #define NCONF_MSK(mask) … #define NCONF_IS(val) … #define NCONF_GE(val) … #define NCONF_GT(val) … #define NCONF_LT(val) … #define NCONF_LE(val) … #define LCNCONF_HAS(val) … #define LCNCONF_MSK(mask) … #define LCNCONF_IS(val) … #define LCNCONF_GE(val) … #define LCNCONF_GT(val) … #define LCNCONF_LT(val) … #define LCNCONF_LE(val) … #define D11CONF_HAS(val) … #define D11CONF_MSK(mask) … #define D11CONF_IS(val) … #define D11CONF_GE(val) … #define D11CONF_GT(val) … #define D11CONF_LT(val) … #define D11CONF_LE(val) … #define PHYCONF_HAS(val) … #define PHYCONF_IS(val) … #define NREV_IS(var, val) … #define NREV_GE(var, val) … #define NREV_GT(var, val) … #define NREV_LT(var, val) … #define NREV_LE(var, val) … #define LCNREV_IS(var, val) … #define LCNREV_GE(var, val) … #define LCNREV_GT(var, val) … #define LCNREV_LT(var, val) … #define LCNREV_LE(var, val) … #define D11REV_IS(var, val) … #define D11REV_GE(var, val) … #define D11REV_GT(var, val) … #define D11REV_LT(var, val) … #define D11REV_LE(var, val) … #define PHYTYPE_IS(var, val) … /* Set up PHYTYPE automatically: (depends on PHY_TYPE_X, from d11.h) */ #define _PHYCONF_N … #define _PHYCONF_LCN … #define _PHYCONF_SSLPN … #define PHYTYPE … /* Utility macro to identify 802.11n (HT) capable PHYs */ #define PHYTYPE_11N_CAP(phytype) … /* Last but not least: shorter wlc-specific var checks */ #define BRCMS_ISNPHY(band) … #define BRCMS_ISLCNPHY(band) … #define BRCMS_ISSSLPNPHY(band) … #define BRCMS_PHY_11N_CAP(band) … /********************************************************************** * ------------- End of Core phy/rev configuration. ----------------- * * ******************************************************************** */ #define BCMMSG(dev, fmt, args...) … #ifdef CONFIG_BCM47XX /* * bcm4716 (which includes 4717 & 4718), plus 4706 on PCIe can reorder * transactions. As a fix, a read after write is performed on certain places * in the code. Older chips and the newer 5357 family don't require this fix. */ #define bcma_wflush16 … #else #define bcma_wflush16(c, o, v) … #endif /* CONFIG_BCM47XX */ /* multi-bool data type: set of bools, mbool is true if any is set */ /* set one bool */ #define mboolset(mb, bit) … /* clear one bool */ #define mboolclr(mb, bit) … /* true if one bool is set */ #define mboolisset(mb, bit) … #define mboolmaskset(mb, mask, val) … #define CEIL(x, y) … /* forward declarations */ struct wiphy; struct ieee80211_sta; struct ieee80211_tx_queue_params; struct brcms_info; struct brcms_c_info; struct brcms_hardware; struct brcms_band; struct dma_pub; struct si_pub; struct tx_status; struct d11rxhdr; struct txpwr_limits; /* brcm_msg_level is a bit vector with defs in defs.h */ extern u32 brcm_msg_level; #endif /* _BRCM_TYPES_H_ */
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