/* * Copyright (c) 2010 Broadcom Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ #ifndef _BRCM_D11_H_ #define _BRCM_D11_H_ #include <linux/ieee80211.h> #include <defs.h> #include "pub.h" #include "dma.h" /* RX FIFO numbers */ #define RX_FIFO … #define RX_TXSTATUS_FIFO … /* TX FIFO numbers using WME Access Category */ #define TX_AC_BK_FIFO … #define TX_AC_BE_FIFO … #define TX_AC_VI_FIFO … #define TX_AC_VO_FIFO … #define TX_BCMC_FIFO … #define TX_ATIM_FIFO … /* Addr is byte address used by SW; offset is word offset used by uCode */ /* Per AC TX limit settings */ #define M_AC_TXLMT_BASE_ADDR … #define M_AC_TXLMT_ADDR(_ac) … /* Legacy TX FIFO numbers */ #define TX_DATA_FIFO … #define TX_CTL_FIFO … #define WL_RSSI_ANT_MAX … struct intctrlregs { … }; /* PIO structure, * support two PIO format: 2 bytes access and 4 bytes access * basic FIFO register set is per channel(transmit or receive) * a pair of channels is defined for convenience */ /* 2byte-wide pio register set per channel(xmt or rcv) */ struct pio2regs { … }; /* a pair of pio channels(tx and rx) */ struct pio2regp { … }; /* 4byte-wide pio register set per channel(xmt or rcv) */ struct pio4regs { … }; /* a pair of pio channels(tx and rx) */ struct pio4regp { … }; /* read: 32-bit register that can be read as 32-bit or as 2 16-bit * write: only low 16b-it half can be written */ pmqreg; struct fifo64 { … }; /* * Host Interface Registers */ struct d11regs { … }; /* d11 register field offset */ #define D11REGOFFS(field) … #define PIHR_BASE … /* biststatus */ #define BT_DONE … #define BT_B2S … /* intstatus and intmask */ #define I_PC … #define I_PD … #define I_DE … #define I_RU … #define I_RO … #define I_XU … #define I_RI … #define I_XI … /* interrupt receive lazy */ #define IRL_TO_MASK … #define IRL_FC_MASK … #define IRL_FC_SHIFT … /*== maccontrol register ==*/ #define MCTL_GMODE … #define MCTL_DISCARD_PMQ … #define MCTL_TBTTHOLD … #define MCTL_WAKE … #define MCTL_HPS … #define MCTL_PROMISC … #define MCTL_KEEPBADFCS … #define MCTL_KEEPCONTROL … #define MCTL_PHYLOCK … #define MCTL_BCNS_PROMISC … #define MCTL_LOCK_RADIO … #define MCTL_AP … #define MCTL_INFRA … #define MCTL_BIGEND … #define MCTL_GPOUT_SEL_MASK … #define MCTL_GPOUT_SEL_SHIFT … #define MCTL_EN_PSMDBG … #define MCTL_IHR_EN … #define MCTL_SHM_UPPER … #define MCTL_SHM_EN … #define MCTL_PSM_JMP_0 … #define MCTL_PSM_RUN … #define MCTL_EN_MAC … /*== maccommand register ==*/ #define MCMD_BCN0VLD … #define MCMD_BCN1VLD … #define MCMD_DIRFRMQVAL … #define MCMD_CCA … #define MCMD_BG_NOISE … #define MCMD_SKIP_SHMINIT … #define MCMD_SAMPLECOLL … /*== macintstatus/macintmask ==*/ /* gracefully suspended */ #define MI_MACSSPNDD … /* beacon template available */ #define MI_BCNTPL … /* TBTT indication */ #define MI_TBTT … /* beacon successfully tx'd */ #define MI_BCNSUCCESS … /* beacon canceled (IBSS) */ #define MI_BCNCANCLD … /* end of ATIM-window (IBSS) */ #define MI_ATIMWINEND … /* PMQ entries available */ #define MI_PMQ … /* non-specific gen-stat bits that are set by PSM */ #define MI_NSPECGEN_0 … /* non-specific gen-stat bits that are set by PSM */ #define MI_NSPECGEN_1 … /* MAC level Tx error */ #define MI_MACTXERR … /* non-specific gen-stat bits that are set by PSM */ #define MI_NSPECGEN_3 … /* PHY Tx error */ #define MI_PHYTXERR … /* Power Management Event */ #define MI_PME … /* General-purpose timer0 */ #define MI_GP0 … /* General-purpose timer1 */ #define MI_GP1 … /* (ORed) DMA-interrupts */ #define MI_DMAINT … /* MAC has completed a TX FIFO Suspend/Flush */ #define MI_TXSTOP … /* MAC has completed a CCA measurement */ #define MI_CCA … /* MAC has collected background noise samples */ #define MI_BG_NOISE … /* MBSS DTIM TBTT indication */ #define MI_DTIM_TBTT … /* Probe response queue needs attention */ #define MI_PRQ … /* Radio/PHY has been powered back up. */ #define MI_PWRUP … #define MI_RESERVED3 … #define MI_RESERVED2 … #define MI_RESERVED1 … /* MAC detected change on RF Disable input*/ #define MI_RFDISABLE … /* MAC has completed a TX */ #define MI_TFS … /* A phy status change wrt G mode */ #define MI_PHYCHANGED … /* general purpose timeout */ #define MI_TO … /* Mac capabilities registers */ /*== machwcap ==*/ #define MCAP_TKIPMIC … /*== pmqhost data ==*/ /* data entry of head pmq entry */ #define PMQH_DATA_MASK … /* PM entry for BSS config */ #define PMQH_BSSCFG … /* PM Mode OFF: power save off */ #define PMQH_PMOFF … /* PM Mode ON: power save on */ #define PMQH_PMON … /* Dis-associated or De-authenticated */ #define PMQH_DASAT … /* ATIM not acknowledged */ #define PMQH_ATIMFAIL … /* delete head entry */ #define PMQH_DEL_ENTRY … /* delete head entry to cur read pointer -1 */ #define PMQH_DEL_MULT … /* pmq overflow indication */ #define PMQH_OFLO … /* entries are present in pmq */ #define PMQH_NOT_EMPTY … /*== phydebug ==*/ /* phy is asserting carrier sense */ #define PDBG_CRS … /* phy is taking xmit byte from mac this cycle */ #define PDBG_TXA … /* mac is instructing the phy to transmit a frame */ #define PDBG_TXF … /* phy is signalling a transmit Error to the mac */ #define PDBG_TXE … /* phy detected the end of a valid frame preamble */ #define PDBG_RXF … /* phy detected the end of a valid PLCP header */ #define PDBG_RXS … /* rx start not asserted */ #define PDBG_RXFRG … /* mac is taking receive byte from phy this cycle */ #define PDBG_RXV … /* RF portion of the radio is disabled */ #define PDBG_RFD … /*== objaddr register ==*/ #define OBJADDR_SEL_MASK … #define OBJADDR_UCM_SEL … #define OBJADDR_SHM_SEL … #define OBJADDR_SCR_SEL … #define OBJADDR_IHR_SEL … #define OBJADDR_RCMTA_SEL … #define OBJADDR_SRCHM_SEL … #define OBJADDR_WINC … #define OBJADDR_RINC … #define OBJADDR_AUTO_INC … #define WEP_PCMADDR … #define WEP_PCMDATA … /*== frmtxstatus ==*/ #define TXS_V … #define TXS_STATUS_MASK … #define TXS_FID_MASK … #define TXS_FID_SHIFT … /*== frmtxstatus2 ==*/ #define TXS_SEQ_MASK … #define TXS_PTX_MASK … #define TXS_PTX_SHIFT … #define TXS_MU_MASK … #define TXS_MU_SHIFT … /*== clk_ctl_st ==*/ #define CCS_ERSRC_REQ_D11PLL … #define CCS_ERSRC_REQ_PHYPLL … #define CCS_ERSRC_AVAIL_D11PLL … #define CCS_ERSRC_AVAIL_PHYPLL … /* HT Cloclk Ctrl and Clock Avail for 4313 */ #define CCS_ERSRC_REQ_HT … #define CCS_ERSRC_AVAIL_HT … /* tsf_cfprep register */ #define CFPREP_CBI_MASK … #define CFPREP_CBI_SHIFT … #define CFPREP_CFPP … /* tx fifo sizes values are in terms of 256 byte blocks */ #define TXFIFOCMD_RESET_MASK … #define TXFIFOCMD_FIFOSEL_SHIFT … #define TXFIFO_FIFOTOP_SHIFT … #define TXFIFO_START_BLK16 … #define TXFIFO_START_BLK … #define TXFIFO_SIZE_UNIT … #define MBSS16_TEMPLMEM_MINBLKS … /*== phy versions (PhyVersion:Revision field) ==*/ /* analog block version */ #define PV_AV_MASK … /* analog block version bitfield offset */ #define PV_AV_SHIFT … /* phy type */ #define PV_PT_MASK … /* phy type bitfield offset */ #define PV_PT_SHIFT … /* phy version */ #define PV_PV_MASK … #define PHY_TYPE(v) … /*== phy types (PhyVersion:PhyType field) ==*/ #define PHY_TYPE_N … #define PHY_TYPE_SSN … #define PHY_TYPE_LCN … #define PHY_TYPE_LCNXN … #define PHY_TYPE_NULL … /*== analog types (PhyVersion:AnalogType field) ==*/ #define ANA_11N_013 … /* 802.11a PLCP header def */ struct ofdm_phy_hdr { … } __packed; #define D11A_PHY_HDR_GRATE(phdr) … #define D11A_PHY_HDR_GRES(phdr) … #define D11A_PHY_HDR_GLENGTH(phdr) … #define D11A_PHY_HDR_GPARITY(phdr) … #define D11A_PHY_HDR_GTAIL(phdr) … /* rate encoded per 802.11a-1999 sec 17.3.4.1 */ #define D11A_PHY_HDR_SRATE(phdr, rate) … /* set reserved field to zero */ #define D11A_PHY_HDR_SRES(phdr) … /* length is number of octets in PSDU */ #define D11A_PHY_HDR_SLENGTH(phdr, length) … /* set the tail to all zeros */ #define D11A_PHY_HDR_STAIL(phdr) … #define D11A_PHY_HDR_LEN_L … #define D11A_PHY_HDR_LEN_R … #define D11A_PHY_TX_DELAY … #define D11A_PHY_HDR_TIME … #define D11A_PHY_PRE_TIME … #define D11A_PHY_PREHDR_TIME … /* 802.11b PLCP header def */ struct cck_phy_hdr { … } __packed; #define D11B_PHY_HDR_LEN … #define D11B_PHY_TX_DELAY … #define D11B_PHY_LHDR_TIME … #define D11B_PHY_LPRE_TIME … #define D11B_PHY_LPREHDR_TIME … #define D11B_PHY_SHDR_TIME … #define D11B_PHY_SPRE_TIME … #define D11B_PHY_SPREHDR_TIME … #define D11B_PLCP_SIGNAL_LOCKED … #define D11B_PLCP_SIGNAL_LE … #define MIMO_PLCP_MCS_MASK … #define MIMO_PLCP_40MHZ … #define MIMO_PLCP_AMPDU … #define BRCMS_GET_CCK_PLCP_LEN(plcp) … #define BRCMS_GET_MIMO_PLCP_LEN(plcp) … #define BRCMS_SET_MIMO_PLCP_LEN(plcp, len) … #define BRCMS_SET_MIMO_PLCP_AMPDU(plcp) … #define BRCMS_CLR_MIMO_PLCP_AMPDU(plcp) … #define BRCMS_IS_MIMO_PLCP_AMPDU(plcp) … /* * The dot11a PLCP header is 5 bytes. To simplify the software (so that we * don't need e.g. different tx DMA headers for 11a and 11b), the PLCP header * has padding added in the ucode. */ #define D11_PHY_HDR_LEN … /* TX DMA buffer header */ struct d11txh { … } __packed __aligned(…); #define D11_TXH_LEN … /* Frame Types */ #define FT_CCK … #define FT_OFDM … #define FT_HT … #define FT_N … /* * Position of MPDU inside A-MPDU; indicated with bits 10:9 * of MacTxControlLow */ #define TXC_AMPDU_SHIFT … #define TXC_AMPDU_NONE … #define TXC_AMPDU_FIRST … #define TXC_AMPDU_MIDDLE … #define TXC_AMPDU_LAST … /*== MacTxControlLow ==*/ #define TXC_AMIC … #define TXC_SENDCTS … #define TXC_AMPDU_MASK … #define TXC_BW_40 … #define TXC_FREQBAND_5G … #define TXC_DFCS … #define TXC_IGNOREPMQ … #define TXC_HWSEQ … #define TXC_STARTMSDU … #define TXC_SENDRTS … #define TXC_LONGFRAME … #define TXC_IMMEDACK … /*== MacTxControlHigh ==*/ /* RTS fallback preamble type 1 = SHORT 0 = LONG */ #define TXC_PREAMBLE_RTS_FB_SHORT … /* RTS main rate preamble type 1 = SHORT 0 = LONG */ #define TXC_PREAMBLE_RTS_MAIN_SHORT … /* * Main fallback rate preamble type * 1 = SHORT for OFDM/GF for MIMO * 0 = LONG for CCK/MM for MIMO */ #define TXC_PREAMBLE_DATA_FB_SHORT … /* TXC_PREAMBLE_DATA_MAIN is in PhyTxControl bit 5 */ /* use fallback rate for this AMPDU */ #define TXC_AMPDU_FBR … #define TXC_SECKEY_MASK … #define TXC_SECKEY_SHIFT … /* Use alternate txpwr defined at loc. M_ALT_TXPWR_IDX */ #define TXC_ALT_TXPWR … #define TXC_SECTYPE_MASK … #define TXC_SECTYPE_SHIFT … /* Null delimiter for Fallback rate */ #define AMPDU_FBR_NULL_DELIM … /* PhyTxControl for Mimophy */ #define PHY_TXC_PWR_MASK … #define PHY_TXC_PWR_SHIFT … #define PHY_TXC_ANT_MASK … #define PHY_TXC_ANT_SHIFT … #define PHY_TXC_ANT_0_1 … #define PHY_TXC_LCNPHY_ANT_LAST … #define PHY_TXC_ANT_3 … #define PHY_TXC_ANT_2 … #define PHY_TXC_ANT_1 … #define PHY_TXC_ANT_0 … #define PHY_TXC_SHORT_HDR … #define PHY_TXC_OLD_ANT_0 … #define PHY_TXC_OLD_ANT_1 … #define PHY_TXC_OLD_ANT_LAST … /* PhyTxControl_1 for Mimophy */ #define PHY_TXC1_BW_MASK … #define PHY_TXC1_BW_10MHZ … #define PHY_TXC1_BW_10MHZ_UP … #define PHY_TXC1_BW_20MHZ … #define PHY_TXC1_BW_20MHZ_UP … #define PHY_TXC1_BW_40MHZ … #define PHY_TXC1_BW_40MHZ_DUP … #define PHY_TXC1_MODE_SHIFT … #define PHY_TXC1_MODE_MASK … #define PHY_TXC1_MODE_SISO … #define PHY_TXC1_MODE_CDD … #define PHY_TXC1_MODE_STBC … #define PHY_TXC1_MODE_SDM … /* PhyTxControl for HTphy that are different from Mimophy */ #define PHY_TXC_HTANT_MASK … /* XtraFrameTypes */ #define XFTS_RTS_FT_SHIFT … #define XFTS_FBRRTS_FT_SHIFT … #define XFTS_CHANNEL_SHIFT … /* Antenna diversity bit in ant_wr_settle */ #define PHY_AWS_ANTDIV … /* IFS ctl */ #define IFS_USEEDCF … /* IFS ctl1 */ #define IFS_CTL1_EDCRS … #define IFS_CTL1_EDCRS_20L … #define IFS_CTL1_EDCRS_40 … /* ABI_MimoAntSel */ #define ABI_MAS_ADDR_BMP_IDX_MASK … #define ABI_MAS_ADDR_BMP_IDX_SHIFT … #define ABI_MAS_FBR_ANT_PTN_MASK … #define ABI_MAS_FBR_ANT_PTN_SHIFT … #define ABI_MAS_MRT_ANT_PTN_MASK … /* tx status packet */ struct tx_status { … } __packed; #define TXSTATUS_LEN … /* status field bit definitions */ #define TX_STATUS_FRM_RTX_MASK … #define TX_STATUS_FRM_RTX_SHIFT … #define TX_STATUS_RTS_RTX_MASK … #define TX_STATUS_RTS_RTX_SHIFT … #define TX_STATUS_MASK … #define TX_STATUS_PMINDCTD … #define TX_STATUS_INTERMEDIATE … #define TX_STATUS_AMPDU … #define TX_STATUS_SUPR_MASK … #define TX_STATUS_SUPR_SHIFT … #define TX_STATUS_ACK_RCV … #define TX_STATUS_VALID … #define TX_STATUS_NO_ACK … /* suppress status reason codes */ #define TX_STATUS_SUPR_PMQ … #define TX_STATUS_SUPR_FLUSH … #define TX_STATUS_SUPR_FRAG … #define TX_STATUS_SUPR_TBTT … #define TX_STATUS_SUPR_BADCH … #define TX_STATUS_SUPR_EXPTIME … #define TX_STATUS_SUPR_UF … /* Unexpected tx status for rate update */ #define TX_STATUS_UNEXP(status) … /* Unexpected tx status for A-MPDU rate update */ #define TX_STATUS_UNEXP_AMPDU(status) … #define TX_STATUS_BA_BMAP03_MASK … #define TX_STATUS_BA_BMAP03_SHIFT … #define TX_STATUS_BA_BMAP47_MASK … #define TX_STATUS_BA_BMAP47_SHIFT … /* RXE (Receive Engine) */ /* RCM_CTL */ #define RCM_INC_MASK_H … #define RCM_INC_MASK_L … #define RCM_INC_DATA … #define RCM_INDEX_MASK … #define RCM_SIZE … #define RCM_MAC_OFFSET … #define RCM_BSSID_OFFSET … #define RCM_F_BSSID_0_OFFSET … #define RCM_F_BSSID_1_OFFSET … #define RCM_F_BSSID_2_OFFSET … #define RCM_WEP_TA0_OFFSET … #define RCM_WEP_TA1_OFFSET … #define RCM_WEP_TA2_OFFSET … #define RCM_WEP_TA3_OFFSET … /* PSM Block */ /* psm_phy_hdr_param bits */ #define MAC_PHY_RESET … #define MAC_PHY_CLOCK_EN … #define MAC_PHY_FORCE_CLK … /* WEP Block */ /* WEP_WKEY */ #define WKEY_START … #define WKEY_SEL_MASK … /* WEP data formats */ /* the number of RCMTA entries */ #define RCMTA_SIZE … #define M_ADDR_BMP_BLK … #define M_ADDR_BMP_BLK_SZ … #define ADDR_BMP_RA … #define ADDR_BMP_TA … #define ADDR_BMP_BSSID … #define ADDR_BMP_AP … #define ADDR_BMP_STA … #define ADDR_BMP_RESERVED1 … #define ADDR_BMP_RESERVED2 … #define ADDR_BMP_RESERVED3 … #define ADDR_BMP_BSS_IDX_MASK … #define ADDR_BMP_BSS_IDX_SHIFT … #define WSEC_MAX_RCMTA_KEYS … /* max keys in M_TKMICKEYS_BLK */ #define WSEC_MAX_TKMIC_ENGINE_KEYS … /* max RXE match registers */ #define WSEC_MAX_RXE_KEYS … /* SECKINDXALGO (Security Key Index & Algorithm Block) word format */ /* SKL (Security Key Lookup) */ #define SKL_ALGO_MASK … #define SKL_ALGO_SHIFT … #define SKL_KEYID_MASK … #define SKL_KEYID_SHIFT … #define SKL_INDEX_MASK … #define SKL_INDEX_SHIFT … #define SKL_GRP_ALGO_MASK … #define SKL_GRP_ALGO_SHIFT … /* additional bits defined for IBSS group key support */ #define SKL_IBSS_INDEX_MASK … #define SKL_IBSS_INDEX_SHIFT … #define SKL_IBSS_KEYID1_MASK … #define SKL_IBSS_KEYID1_SHIFT … #define SKL_IBSS_KEYID2_MASK … #define SKL_IBSS_KEYID2_SHIFT … #define SKL_IBSS_KEYALGO_MASK … #define SKL_IBSS_KEYALGO_SHIFT … #define WSEC_MODE_OFF … #define WSEC_MODE_HW … #define WSEC_MODE_SW … #define WSEC_ALGO_OFF … #define WSEC_ALGO_WEP1 … #define WSEC_ALGO_TKIP … #define WSEC_ALGO_AES … #define WSEC_ALGO_WEP128 … #define WSEC_ALGO_AES_LEGACY … #define WSEC_ALGO_NALG … #define AES_MODE_NONE … #define AES_MODE_CCM … /* WEP_CTL (Rev 0) */ #define WECR0_KEYREG_SHIFT … #define WECR0_KEYREG_MASK … #define WECR0_DECRYPT … #define WECR0_IVINLINE … #define WECR0_WEPALG_SHIFT … #define WECR0_WEPALG_MASK … #define WECR0_WKEYSEL_SHIFT … #define WECR0_WKEYSEL_MASK … #define WECR0_WKEYSTART … #define WECR0_WEPINIT … #define WECR0_ICVERR … /* Frame template map byte offsets */ #define T_ACTS_TPL_BASE … #define T_NULL_TPL_BASE … #define T_QNULL_TPL_BASE … #define T_RR_TPL_BASE … #define T_BCN0_TPL_BASE … #define T_PRS_TPL_BASE … #define T_BCN1_TPL_BASE … #define T_TX_FIFO_TXRAM_BASE … #define T_BA_TPL_BASE … #define T_RAM_ACCESS_SZ … /* Shared Mem byte offsets */ /* Location where the ucode expects the corerev */ #define M_MACHW_VER … /* Location where the ucode expects the MAC capabilities */ #define M_MACHW_CAP_L … #define M_MACHW_CAP_H … /* WME shared memory */ #define M_EDCF_STATUS_OFF … #define M_TXF_CUR_INDEX … #define M_EDCF_QINFO … /* PS-mode related parameters */ #define M_DOT11_SLOT … #define M_DOT11_DTIMPERIOD … #define M_NOSLPZNATDTIM … /* Beacon-related parameters */ #define M_BCN0_FRM_BYTESZ … #define M_BCN1_FRM_BYTESZ … #define M_BCN_TXTSF_OFFSET … #define M_TIMBPOS_INBEACON … #define M_SFRMTXCNTFBRTHSD … #define M_LFRMTXCNTFBRTHSD … #define M_BCN_PCTLWD … #define M_BCN_LI … /* MAX Rx Frame len */ #define M_MAXRXFRM_LEN … /* ACK/CTS related params */ #define M_RSP_PCTLWD … /* Hardware Power Control */ #define M_TXPWR_N … #define M_TXPWR_TARGET … #define M_TXPWR_MAX … #define M_TXPWR_CUR … /* Rx-related parameters */ #define M_RX_PAD_DATA_OFFSET … /* WEP Shared mem data */ #define M_SEC_DEFIVLOC … #define M_SEC_VALNUMSOFTMCHTA … #define M_PHYVER … #define M_PHYTYPE … #define M_SECRXKEYS_PTR … #define M_TKMICKEYS_PTR … #define M_SECKINDXALGO_BLK … #define M_SECKINDXALGO_BLK_SZ … #define M_SECPSMRXTAMCH_BLK … #define M_TKIP_TSC_TTAK … #define D11_MAX_KEY_SIZE … #define M_MAX_ANTCNT … /* Probe response related parameters */ #define M_SSIDLEN … #define M_PRB_RESP_FRM_LEN … #define M_PRS_MAXTIME … #define M_SSID … #define M_CTXPRS_BLK … #define C_CTX_PCTLWD_POS … /* Delta between OFDM and CCK power in CCK power boost mode */ #define M_OFDM_OFFSET … /* TSSI for last 4 11b/g CCK packets transmitted */ #define M_B_TSSI_0 … #define M_B_TSSI_1 … /* Host flags to turn on ucode options */ #define M_HOST_FLAGS1 … #define M_HOST_FLAGS2 … #define M_HOST_FLAGS3 … #define M_HOST_FLAGS4 … #define M_HOST_FLAGS5 … #define M_HOST_FLAGS_SZ … #define M_RADAR_REG … /* TSSI for last 4 11a OFDM packets transmitted */ #define M_A_TSSI_0 … #define M_A_TSSI_1 … /* noise interference measurement */ #define M_NOISE_IF_COUNT … #define M_NOISE_IF_TIMEOUT … #define M_RF_RX_SP_REG1 … /* TSSI for last 4 11g OFDM packets transmitted */ #define M_G_TSSI_0 … #define M_G_TSSI_1 … /* Background noise measure */ #define M_JSSI_0 … #define M_JSSI_1 … #define M_JSSI_AUX … #define M_CUR_2050_RADIOCODE … /* TX fifo sizes */ #define M_FIFOSIZE0 … #define M_FIFOSIZE1 … #define M_FIFOSIZE2 … #define M_FIFOSIZE3 … #define D11_MAX_TX_FRMS … /* Current channel number plus upper bits */ #define M_CURCHANNEL … #define D11_CURCHANNEL_5G … #define D11_CURCHANNEL_40 … #define D11_CURCHANNEL_MAX … /* last posted frameid on the bcmc fifo */ #define M_BCMC_FID … #define INVALIDFID … /* extended beacon phyctl bytes for 11N */ #define M_BCN_PCTL1WD … /* idle busy ratio to duty_cycle requirement */ #define M_TX_IDLE_BUSY_RATIO_X_16_CCK … #define M_TX_IDLE_BUSY_RATIO_X_16_OFDM … /* CW RSSI for LCNPHY */ #define M_LCN_RSSI_0 … #define M_LCN_RSSI_1 … #define M_LCN_RSSI_2 … #define M_LCN_RSSI_3 … /* SNR for LCNPHY */ #define M_LCN_SNR_A_0 … #define M_LCN_SNR_B_0 … #define M_LCN_SNR_A_1 … #define M_LCN_SNR_B_1 … #define M_LCN_SNR_A_2 … #define M_LCN_SNR_B_2 … #define M_LCN_SNR_A_3 … #define M_LCN_SNR_B_3 … #define M_LCN_LAST_RESET … #define M_LCN_LAST_LOC … #define M_LCNPHY_RESET_STATUS … #define M_LCNPHY_DSC_TIME … #define M_LCNPHY_RESET_CNT_DSC … #define M_LCNPHY_RESET_CNT … /* Rate table offsets */ #define M_RT_DIRMAP_A … #define M_RT_BBRSMAP_A … #define M_RT_DIRMAP_B … #define M_RT_BBRSMAP_B … /* Rate table entry offsets */ #define M_RT_PRS_PLCP_POS … #define M_RT_PRS_DUR_POS … #define M_RT_OFDM_PCTL1_POS … #define M_20IN40_IQ … /* SHM locations where ucode stores the current power index */ #define M_CURR_IDX1 … #define M_CURR_IDX2 … #define M_BSCALE_ANT0 … #define M_BSCALE_ANT1 … /* Antenna Diversity Testing */ #define M_MIMO_ANTSEL_RXDFLT … #define M_ANTSEL_CLKDIV … #define M_MIMO_ANTSEL_TXDFLT … #define M_MIMO_MAXSYM … #define MIMO_MAXSYM_DEF … #define MIMO_MAXSYM_MAX … #define M_WATCHDOG_8TU … #define WATCHDOG_8TU_DEF … #define WATCHDOG_8TU_MAX … /* Manufacturing Test Variables */ /* PER test mode */ #define M_PKTENG_CTRL … /* IFS for TX mode */ #define M_PKTENG_IFS … /* Lower word of tx frmcnt/rx lostcnt */ #define M_PKTENG_FRMCNT_LO … /* Upper word of tx frmcnt/rx lostcnt */ #define M_PKTENG_FRMCNT_HI … /* Index variation in vbat ripple */ #define M_LCN_PWR_IDX_MAX … #define M_LCN_PWR_IDX_MIN … /* M_PKTENG_CTRL bit definitions */ #define M_PKTENG_MODE_TX … #define M_PKTENG_MODE_TX_RIFS … #define M_PKTENG_MODE_TX_CTS … #define M_PKTENG_MODE_RX … #define M_PKTENG_MODE_RX_WITH_ACK … #define M_PKTENG_MODE_MASK … /* TX frames indicated in the frmcnt reg */ #define M_PKTENG_FRMCNT_VLD … /* Sample Collect parameters (bitmap and type) */ /* Trigger bitmap for sample collect */ #define M_SMPL_COL_BMP … /* Sample collect type */ #define M_SMPL_COL_CTL … #define ANTSEL_CLKDIV_4MHZ … #define MIMO_ANTSEL_BUSY … #define MIMO_ANTSEL_SEL … #define MIMO_ANTSEL_WAIT … #define MIMO_ANTSEL_OVERRIDE … struct shm_acparams { … } __packed; #define M_EDCF_QLEN … #define WME_STATUS_NEWAC … /* M_HOST_FLAGS */ #define MHFMAX … #define MHF1 … #define MHF2 … #define MHF3 … #define MHF4 … #define MHF5 … /* Flags in M_HOST_FLAGS */ /* Enable ucode antenna diversity help */ #define MHF1_ANTDIV … /* Enable EDCF access control */ #define MHF1_EDCF … #define MHF1_IQSWAP_WAR … /* Disable Slow clock request, for corerev < 11 */ #define MHF1_FORCEFASTCLK … /* Flags in M_HOST_FLAGS2 */ /* Flush BCMC FIFO immediately */ #define MHF2_TXBCMC_NOW … /* Enable ucode/hw power control */ #define MHF2_HWPWRCTL … #define MHF2_NPHY40MHZ_WAR … /* Flags in M_HOST_FLAGS3 */ /* enabled mimo antenna selection */ #define MHF3_ANTSEL_EN … /* antenna selection mode: 0: 2x3, 1: 2x4 */ #define MHF3_ANTSEL_MODE … #define MHF3_RESERVED1 … #define MHF3_RESERVED2 … #define MHF3_NPHY_MLADV_WAR … /* Flags in M_HOST_FLAGS4 */ /* force bphy Tx on core 0 (board level WAR) */ #define MHF4_BPHY_TXCORE0 … /* for 4313A0 FEM boards */ #define MHF4_EXTPA_ENABLE … /* Flags in M_HOST_FLAGS5 */ #define MHF5_4313_GPIOCTRL … #define MHF5_RESERVED1 … #define MHF5_RESERVED2 … /* Radio power setting for ucode */ #define M_RADIO_PWR … /* phy noise recorded by ucode right after tx */ #define M_PHY_NOISE … #define PHY_NOISE_MASK … /* * Receive Frame Data Header for 802.11b DCF-only frames * * RxFrameSize: Actual byte length of the frame data received * PAD: padding (not used) * PhyRxStatus_0: PhyRxStatus 15:0 * PhyRxStatus_1: PhyRxStatus 31:16 * PhyRxStatus_2: PhyRxStatus 47:32 * PhyRxStatus_3: PhyRxStatus 63:48 * PhyRxStatus_4: PhyRxStatus 79:64 * PhyRxStatus_5: PhyRxStatus 95:80 * RxStatus1: MAC Rx Status * RxStatus2: extended MAC Rx status * RxTSFTime: RxTSFTime time of first MAC symbol + M_PHY_PLCPRX_DLY * RxChan: gain code, channel radio code, and phy type */ struct d11rxhdr_le { … } __packed; struct d11rxhdr { … } __packed; /* PhyRxStatus_0: */ /* NPHY only: CCK, OFDM, preN, N */ #define PRXS0_FT_MASK … /* NPHY only: clip count adjustment steps by AGC */ #define PRXS0_CLIP_MASK … #define PRXS0_CLIP_SHIFT … /* PHY received a frame with unsupported rate */ #define PRXS0_UNSRATE … /* GPHY: rx ant, NPHY: upper sideband */ #define PRXS0_RXANT_UPSUBBAND … /* CCK frame only: lost crs during cck frame reception */ #define PRXS0_LCRS … /* Short Preamble */ #define PRXS0_SHORTH … /* PLCP violation */ #define PRXS0_PLCPFV … /* PLCP header integrity check failed */ #define PRXS0_PLCPHCF … /* legacy PHY gain control */ #define PRXS0_GAIN_CTL … /* NPHY: Antennas used for received frame, bitmask */ #define PRXS0_ANTSEL_MASK … #define PRXS0_ANTSEL_SHIFT … /* subfield PRXS0_FT_MASK */ #define PRXS0_CCK … /* valid only for G phy, use rxh->RxChan for A phy */ #define PRXS0_OFDM … #define PRXS0_PREN … #define PRXS0_STDN … /* subfield PRXS0_ANTSEL_MASK */ #define PRXS0_ANTSEL_0 … #define PRXS0_ANTSEL_1 … #define PRXS0_ANTSEL_2 … #define PRXS0_ANTSEL_3 … /* PhyRxStatus_1: */ #define PRXS1_JSSI_MASK … #define PRXS1_JSSI_SHIFT … #define PRXS1_SQ_MASK … #define PRXS1_SQ_SHIFT … /* nphy PhyRxStatus_1: */ #define PRXS1_nphy_PWR0_MASK … #define PRXS1_nphy_PWR1_MASK … /* HTPHY Rx Status defines */ /* htphy PhyRxStatus_0: those bit are overlapped with PhyRxStatus_0 */ #define PRXS0_BAND … #define PRXS0_RSVD … #define PRXS0_UNUSED … /* htphy PhyRxStatus_1: */ /* core enables for {3..0}, 0=disabled, 1=enabled */ #define PRXS1_HTPHY_CORE_MASK … /* antenna configuration */ #define PRXS1_HTPHY_ANTCFG_MASK … /* Mixmode PLCP Length low byte mask */ #define PRXS1_HTPHY_MMPLCPLenL_MASK … /* htphy PhyRxStatus_2: */ /* Mixmode PLCP Length high byte maskw */ #define PRXS2_HTPHY_MMPLCPLenH_MASK … /* Mixmode PLCP rate mask */ #define PRXS2_HTPHY_MMPLCH_RATE_MASK … /* Rx power on core 0 */ #define PRXS2_HTPHY_RXPWR_ANT0 … /* htphy PhyRxStatus_3: */ /* Rx power on core 1 */ #define PRXS3_HTPHY_RXPWR_ANT1 … /* Rx power on core 2 */ #define PRXS3_HTPHY_RXPWR_ANT2 … /* htphy PhyRxStatus_4: */ /* Rx power on core 3 */ #define PRXS4_HTPHY_RXPWR_ANT3 … /* Coarse frequency offset */ #define PRXS4_HTPHY_CFO … /* htphy PhyRxStatus_5: */ /* Fine frequency offset */ #define PRXS5_HTPHY_FFO … /* Advance Retard */ #define PRXS5_HTPHY_AR … #define HTPHY_MMPLCPLen(rxs) … /* Get Rx power on core 0 */ #define HTPHY_RXPWR_ANT0(rxs) … /* Get Rx power on core 1 */ #define HTPHY_RXPWR_ANT1(rxs) … /* Get Rx power on core 2 */ #define HTPHY_RXPWR_ANT2(rxs) … /* ucode RxStatus1: */ #define RXS_BCNSENT … #define RXS_SECKINDX_MASK … #define RXS_SECKINDX_SHIFT … #define RXS_DECERR … #define RXS_DECATMPT … /* PAD bytes to make IP data 4 bytes aligned */ #define RXS_PBPRES … #define RXS_RESPFRAMETX … #define RXS_FCSERR … /* ucode RxStatus2: */ #define RXS_AMSDU_MASK … #define RXS_AGGTYPE_MASK … #define RXS_AGGTYPE_SHIFT … #define RXS_PHYRXST_VALID … #define RXS_RXANT_MASK … #define RXS_RXANT_SHIFT … /* RxChan */ #define RXS_CHAN_40 … #define RXS_CHAN_5G … #define RXS_CHAN_ID_MASK … #define RXS_CHAN_ID_SHIFT … #define RXS_CHAN_PHYTYPE_MASK … #define RXS_CHAN_PHYTYPE_SHIFT … /* Index of attenuations used during ucode power control. */ #define M_PWRIND_BLKS … #define M_PWRIND_MAP0 … #define M_PWRIND_MAP1 … #define M_PWRIND_MAP2 … #define M_PWRIND_MAP3 … /* M_PWRIND_MAP(core) macro */ #define M_PWRIND_MAP(core) … /* PSM SHM variable offsets */ #define M_PSM_SOFT_REGS … #define M_BOM_REV_MAJOR … #define M_BOM_REV_MINOR … #define M_UCODE_DBGST … #define M_UCODE_MACSTAT … #define M_AGING_THRSH … #define M_MBURST_SIZE … #define M_MBURST_TXOP … #define M_SYNTHPU_DLY … #define M_PRETBTT … /* offset to the target txpwr */ #define M_ALT_TXPWR_IDX … #define M_PHY_TX_FLT_PTR … #define M_CTS_DURATION … #define M_LP_RCCAL_OVR … /* PKTENG Rx Stats Block */ #define M_RXSTATS_BLK_PTR … /* ucode debug status codes */ /* not valid really */ #define DBGST_INACTIVE … /* after zeroing SHM, before suspending at init */ #define DBGST_INIT … /* "normal" state */ #define DBGST_ACTIVE … /* suspended */ #define DBGST_SUSPENDED … /* asleep (PS mode) */ #define DBGST_ASLEEP … /* Scratch Reg defs */ enum _ePsmScratchPadRegDefinitions { … }; #define S_BEACON_INDX … #define S_PRS_INDX … #define S_PHYTYPE … #define S_PHYVER … /* IHR SLOW_CTRL values */ #define SLOW_CTRL_PDE … #define SLOW_CTRL_FD … /* ucode mac statistic counters in shared memory */ struct macstat { … }; /* dot11 core-specific control flags */ #define SICF_PCLKE … #define SICF_PRST … #define SICF_MPCLKE … #define SICF_FREF … /* NOTE: the following bw bits only apply when the core is attached * to a NPHY */ #define SICF_BWMASK … #define SICF_BW40 … #define SICF_BW20 … #define SICF_BW10 … #define SICF_GMODE … /* dot11 core-specific status flags */ #define SISF_2G_PHY … #define SISF_5G_PHY … #define SISF_FCLKA … #define SISF_DB_PHY … /* === End of MAC reg, Beginning of PHY(b/a/g/n) reg === */ /* radio and LPPHY regs are separated */ #define BPHY_REG_OFT_BASE … /* offsets for indirect access to bphy registers */ #define BPHY_BB_CONFIG … #define BPHY_ADCBIAS … #define BPHY_ANACORE … #define BPHY_PHYCRSTH … #define BPHY_TEST … #define BPHY_PA_TX_TO … #define BPHY_SYNTH_DC_TO … #define BPHY_PA_TX_TIME_UP … #define BPHY_RX_FLTR_TIME_UP … #define BPHY_TX_POWER_OVERRIDE … #define BPHY_RF_OVERRIDE … #define BPHY_RF_TR_LOOKUP1 … #define BPHY_RF_TR_LOOKUP2 … #define BPHY_COEFFS … #define BPHY_PLL_OUT … #define BPHY_REFRESH_MAIN … #define BPHY_REFRESH_TO0 … #define BPHY_REFRESH_TO1 … #define BPHY_RSSI_TRESH … #define BPHY_IQ_TRESH_HH … #define BPHY_IQ_TRESH_H … #define BPHY_IQ_TRESH_L … #define BPHY_IQ_TRESH_LL … #define BPHY_GAIN … #define BPHY_LNA_GAIN_RANGE … #define BPHY_JSSI … #define BPHY_TSSI_CTL … #define BPHY_TSSI … #define BPHY_TR_LOSS_CTL … #define BPHY_LO_LEAKAGE … #define BPHY_LO_RSSI_ACC … #define BPHY_LO_IQMAG_ACC … #define BPHY_TX_DC_OFF1 … #define BPHY_TX_DC_OFF2 … #define BPHY_PEAK_CNT_THRESH … #define BPHY_FREQ_OFFSET … #define BPHY_DIVERSITY_CTL … #define BPHY_PEAK_ENERGY_LO … #define BPHY_PEAK_ENERGY_HI … #define BPHY_SYNC_CTL … #define BPHY_TX_PWR_CTRL … #define BPHY_TX_EST_PWR … #define BPHY_STEP … #define BPHY_WARMUP … #define BPHY_LMS_CFF_READ … #define BPHY_LMS_COEFF_I … #define BPHY_LMS_COEFF_Q … #define BPHY_SIG_POW … #define BPHY_RFDC_CANCEL_CTL … #define BPHY_HDR_TYPE … #define BPHY_SFD_TO … #define BPHY_SFD_CTL … #define BPHY_DEBUG … #define BPHY_RX_DELAY_COMP … #define BPHY_CRS_DROP_TO … #define BPHY_SHORT_SFD_NZEROS … #define BPHY_DSSS_COEFF1 … #define BPHY_DSSS_COEFF2 … #define BPHY_CCK_COEFF1 … #define BPHY_CCK_COEFF2 … #define BPHY_TR_CORR … #define BPHY_ANGLE_SCALE … #define BPHY_TX_PWR_BASE_IDX … #define BPHY_OPTIONAL_MODES2 … #define BPHY_CCK_LMS_STEP … #define BPHY_BYPASS … #define BPHY_CCK_DELAY_LONG … #define BPHY_CCK_DELAY_SHORT … #define BPHY_PPROC_CHAN_DELAY … #define BPHY_DDFS_ENABLE … #define BPHY_PHASE_SCALE … #define BPHY_FREQ_CONTROL … #define BPHY_LNA_GAIN_RANGE_10 … #define BPHY_LNA_GAIN_RANGE_32 … #define BPHY_OPTIONAL_MODES … #define BPHY_RX_STATUS2 … #define BPHY_RX_STATUS3 … #define BPHY_DAC_CONTROL … #define BPHY_ANA11G_FILT_CTRL … #define BPHY_REFRESH_CTRL … #define BPHY_RF_OVERRIDE2 … #define BPHY_SPUR_CANCEL_CTRL … #define BPHY_FINE_DIGIGAIN_CTRL … #define BPHY_RSSI_LUT … #define BPHY_RSSI_LUT_END … #define BPHY_TSSI_LUT … #define BPHY_TSSI_LUT_END … #define BPHY_TSSI2PWR_LUT … #define BPHY_TSSI2PWR_LUT_END … #define BPHY_LOCOMP_LUT … #define BPHY_LOCOMP_LUT_END … #define BPHY_TXGAIN_LUT … #define BPHY_TXGAIN_LUT_END … /* Bits in BB_CONFIG: */ #define PHY_BBC_ANT_MASK … #define PHY_BBC_ANT_SHIFT … #define BB_DARWIN … #define BBCFG_RESETCCA … #define BBCFG_RESETRX … /* Bits in phytest(0x0a): */ #define TST_DDFS … #define TST_TXFILT1 … #define TST_UNSCRAM … #define TST_CARR_SUPP … #define TST_DC_COMP_LOOP … #define TST_LOOPBACK … #define TST_TXFILT0 … #define TST_TXTEST_ENABLE … #define TST_TXTEST_RATE … #define TST_TXTEST_PHASE … /* phytest txTestRate values */ #define TST_TXTEST_RATE_1MBPS … #define TST_TXTEST_RATE_2MBPS … #define TST_TXTEST_RATE_5_5MBPS … #define TST_TXTEST_RATE_11MBPS … #define TST_TXTEST_RATE_SHIFT … #define SHM_BYT_CNT … #define MAX_BYT_CNT … struct d11cnt { … }; #endif /* _BRCM_D11_H_ */
Codebase Browser
linux