/* * Copyright (c) 2010 Broadcom Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. */ /* * phy_shim.h: stuff defined in phy_shim.c and included only by the phy */ #ifndef _BRCM_PHY_SHIM_H_ #define _BRCM_PHY_SHIM_H_ #include "types.h" #define RADAR_TYPE_NONE … #define RADAR_TYPE_ETSI_1 … #define RADAR_TYPE_ETSI_2 … #define RADAR_TYPE_ETSI_3 … #define RADAR_TYPE_ITU_E … #define RADAR_TYPE_ITU_K … #define RADAR_TYPE_UNCLASSIFIED … #define RADAR_TYPE_BIN5 … #define RADAR_TYPE_STG2 … #define RADAR_TYPE_STG3 … #define RADAR_TYPE_FRA … /* French radar pulse widths */ #define FRA_T1_20MHZ … #define FRA_T2_20MHZ … #define FRA_T3_20MHZ … #define FRA_T1_40MHZ … #define FRA_T2_40MHZ … #define FRA_T3_40MHZ … #define FRA_ERR_20MHZ … #define FRA_ERR_40MHZ … #define ANTSEL_NA … #define ANTSEL_2x4 … #define ANTSEL_2x3 … /* Rx Antenna diversity control values */ #define ANT_RX_DIV_FORCE_0 … #define ANT_RX_DIV_FORCE_1 … #define ANT_RX_DIV_START_1 … #define ANT_RX_DIV_START_0 … #define ANT_RX_DIV_ENABLE … #define ANT_RX_DIV_DEF … #define WL_ANT_RX_MAX … #define WL_ANT_HT_RX_MAX … #define WL_ANT_IDX_1 … #define WL_ANT_IDX_2 … /* values for n_preamble_type */ #define BRCMS_N_PREAMBLE_MIXEDMODE … #define BRCMS_N_PREAMBLE_GF … #define BRCMS_N_PREAMBLE_GF_BRCM … #define WL_TX_POWER_RATES_LEGACY … #define WL_TX_POWER_MCS20_FIRST … #define WL_TX_POWER_MCS20_NUM … #define WL_TX_POWER_MCS40_FIRST … #define WL_TX_POWER_MCS40_NUM … #define WL_TX_POWER_RATES … #define WL_TX_POWER_CCK_FIRST … #define WL_TX_POWER_CCK_NUM … /* Index for first 20MHz OFDM SISO rate */ #define WL_TX_POWER_OFDM_FIRST … /* Index for first 20MHz OFDM CDD rate */ #define WL_TX_POWER_OFDM20_CDD_FIRST … /* Index for first 40MHz OFDM SISO rate */ #define WL_TX_POWER_OFDM40_SISO_FIRST … /* Index for first 40MHz OFDM CDD rate */ #define WL_TX_POWER_OFDM40_CDD_FIRST … #define WL_TX_POWER_OFDM_NUM … /* Index for first 20MHz MCS SISO rate */ #define WL_TX_POWER_MCS20_SISO_FIRST … /* Index for first 20MHz MCS CDD rate */ #define WL_TX_POWER_MCS20_CDD_FIRST … /* Index for first 20MHz MCS STBC rate */ #define WL_TX_POWER_MCS20_STBC_FIRST … /* Index for first 20MHz MCS SDM rate */ #define WL_TX_POWER_MCS20_SDM_FIRST … /* Index for first 40MHz MCS SISO rate */ #define WL_TX_POWER_MCS40_SISO_FIRST … /* Index for first 40MHz MCS CDD rate */ #define WL_TX_POWER_MCS40_CDD_FIRST … /* Index for first 40MHz MCS STBC rate */ #define WL_TX_POWER_MCS40_STBC_FIRST … /* Index for first 40MHz MCS SDM rate */ #define WL_TX_POWER_MCS40_SDM_FIRST … #define WL_TX_POWER_MCS_1_STREAM_NUM … #define WL_TX_POWER_MCS_2_STREAM_NUM … /* Index for 40MHz rate MCS 32 */ #define WL_TX_POWER_MCS_32 … #define WL_TX_POWER_MCS_32_NUM … /* sslpnphy specifics */ /* Index for first 20MHz MCS SISO rate */ #define WL_TX_POWER_MCS20_SISO_FIRST_SSN … /* struct tx_power::flags bits */ #define WL_TX_POWER_F_ENABLED … #define WL_TX_POWER_F_HW … #define WL_TX_POWER_F_MIMO … #define WL_TX_POWER_F_SISO … /* values to force tx/rx chain */ #define BRCMS_N_TXRX_CHAIN0 … #define BRCMS_N_TXRX_CHAIN1 … struct brcms_phy; struct phy_shim_info *wlc_phy_shim_attach(struct brcms_hardware *wlc_hw, struct brcms_info *wl, struct brcms_c_info *wlc); void wlc_phy_shim_detach(struct phy_shim_info *physhim); /* PHY to WL utility functions */ struct wlapi_timer *wlapi_init_timer(struct phy_shim_info *physhim, void (*fn)(void *pi), void *arg, const char *name); void wlapi_free_timer(struct wlapi_timer *t); void wlapi_add_timer(struct wlapi_timer *t, uint ms, int periodic); bool wlapi_del_timer(struct wlapi_timer *t); void wlapi_intrson(struct phy_shim_info *physhim); u32 wlapi_intrsoff(struct phy_shim_info *physhim); void wlapi_intrsrestore(struct phy_shim_info *physhim, u32 macintmask); void wlapi_bmac_write_shm(struct phy_shim_info *physhim, uint offset, u16 v); u16 wlapi_bmac_read_shm(struct phy_shim_info *physhim, uint offset); void wlapi_bmac_mhf(struct phy_shim_info *physhim, u8 idx, u16 mask, u16 val, int bands); void wlapi_bmac_corereset(struct phy_shim_info *physhim, u32 flags); void wlapi_suspend_mac_and_wait(struct phy_shim_info *physhim); void wlapi_switch_macfreq(struct phy_shim_info *physhim, u8 spurmode); void wlapi_enable_mac(struct phy_shim_info *physhim); void wlapi_bmac_mctrl(struct phy_shim_info *physhim, u32 mask, u32 val); void wlapi_bmac_phy_reset(struct phy_shim_info *physhim); void wlapi_bmac_bw_set(struct phy_shim_info *physhim, u16 bw); void wlapi_bmac_phyclk_fgc(struct phy_shim_info *physhim, bool clk); void wlapi_bmac_macphyclk_set(struct phy_shim_info *physhim, bool clk); void wlapi_bmac_core_phypll_ctl(struct phy_shim_info *physhim, bool on); void wlapi_bmac_core_phypll_reset(struct phy_shim_info *physhim); void wlapi_bmac_ucode_wake_override_phyreg_set(struct phy_shim_info *physhim); void wlapi_bmac_ucode_wake_override_phyreg_clear(struct phy_shim_info *physhim); void wlapi_bmac_write_template_ram(struct phy_shim_info *physhim, int o, int len, void *buf); u16 wlapi_bmac_rate_shm_offset(struct phy_shim_info *physhim, u8 rate); void wlapi_ucode_sample_init(struct phy_shim_info *physhim); void wlapi_copyfrom_objmem(struct phy_shim_info *physhim, uint, void *buf, int, u32 sel); void wlapi_copyto_objmem(struct phy_shim_info *physhim, uint, const void *buf, int, u32); void wlapi_high_update_phy_mode(struct phy_shim_info *physhim, u32 phy_mode); u16 wlapi_bmac_get_txant(struct phy_shim_info *physhim); #endif /* _BRCM_PHY_SHIM_H_ */
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