/* * Copyright (c) 2010 Broadcom Corporation * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above * copyright notice and this permission notice appear in all copies. * * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * * File contents: support functions for PCI/PCIe */ #define pr_fmt(fmt) … #include <linux/delay.h> #include <defs.h> #include <chipcommon.h> #include <brcmu_utils.h> #include <brcm_hw_ids.h> #include <soc.h> #include "types.h" #include "pub.h" #include "pmu.h" #include "aiutils.h" /* slow_clk_ctl */ /* slow clock source mask */ #define SCC_SS_MASK … /* source of slow clock is LPO */ #define SCC_SS_LPO … /* source of slow clock is crystal */ #define SCC_SS_XTAL … /* source of slow clock is PCI */ #define SCC_SS_PCI … /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ #define SCC_LF … /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */ #define SCC_LP … /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */ #define SCC_FS … /* IgnorePllOffReq, 1/0: * power logic ignores/honors PLL clock disable requests from core */ #define SCC_IP … /* XtalControlEn, 1/0: * power logic does/doesn't disable crystal when appropriate */ #define SCC_XC … /* XtalPU (RO), 1/0: crystal running/disabled */ #define SCC_XP … /* ClockDivider (SlowClk = 1/(4+divisor)) */ #define SCC_CD_MASK … #define SCC_CD_SHIFT … /* system_clk_ctl */ /* ILPen: Enable Idle Low Power */ #define SYCC_IE … /* ALPen: Enable Active Low Power */ #define SYCC_AE … /* ForcePLLOn */ #define SYCC_FP … /* Force ALP (or HT if ALPen is not set */ #define SYCC_AR … /* Force HT */ #define SYCC_HR … /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ #define SYCC_CD_MASK … #define SYCC_CD_SHIFT … #define CST4329_SPROM_OTP_SEL_MASK … /* OTP is powered up, use def. CIS, no SPROM */ #define CST4329_DEFCIS_SEL … /* OTP is powered up, SPROM is present */ #define CST4329_SPROM_SEL … /* OTP is powered up, no SPROM */ #define CST4329_OTP_SEL … /* OTP is powered down, SPROM is present */ #define CST4329_OTP_PWRDN … #define CST4329_SPI_SDIO_MODE_MASK … #define CST4329_SPI_SDIO_MODE_SHIFT … /* 43224 chip-specific ChipControl register bits */ #define CCTRL43224_GPIO_TOGGLE … /* 12 mA drive strength */ #define CCTRL_43224A0_12MA_LED_DRIVE … /* 12 mA drive strength for later 43224s */ #define CCTRL_43224B0_12MA_LED_DRIVE … /* 43236 Chip specific ChipStatus register bits */ #define CST43236_SFLASH_MASK … #define CST43236_OTP_MASK … #define CST43236_HSIC_MASK … #define CST43236_BP_CLK … #define CST43236_BOOT_MASK … #define CST43236_BOOT_SHIFT … #define CST43236_BOOT_FROM_SRAM … #define CST43236_BOOT_FROM_ROM … #define CST43236_BOOT_FROM_FLASH … #define CST43236_BOOT_FROM_INVALID … /* 4331 chip-specific ChipControl register bits */ /* 0 disable */ #define CCTRL4331_BT_COEXIST … /* 0 SECI is disabled (JTAG functional) */ #define CCTRL4331_SECI … /* 0 disable */ #define CCTRL4331_EXT_LNA … /* sprom/gpio13-15 mux */ #define CCTRL4331_SPROM_GPIO13_15 … /* 0 ext pa disable, 1 ext pa enabled */ #define CCTRL4331_EXTPA_EN … /* set drive out GPIO_CLK on sprom_cs pin */ #define CCTRL4331_GPIOCLK_ON_SPROMCS … /* use sprom_cs pin as PCIE mdio interface */ #define CCTRL4331_PCIE_MDIO_ON_SPROMCS … /* aband extpa will be at gpio2/5 and sprom_dout */ #define CCTRL4331_EXTPA_ON_GPIO2_5 … /* override core control on pipe_AuxClkEnable */ #define CCTRL4331_OVR_PIPEAUXCLKEN … /* override core control on pipe_AuxPowerDown */ #define CCTRL4331_OVR_PIPEAUXPWRDOWN … /* pcie_auxclkenable */ #define CCTRL4331_PCIE_AUXCLKEN … /* pcie_pipe_pllpowerdown */ #define CCTRL4331_PCIE_PIPE_PLLDOWN … /* enable bt_shd0 at gpio4 */ #define CCTRL4331_BT_SHD0_ON_GPIO4 … /* enable bt_shd1 at gpio5 */ #define CCTRL4331_BT_SHD1_ON_GPIO5 … /* 4331 Chip specific ChipStatus register bits */ /* crystal frequency 20/40Mhz */ #define CST4331_XTAL_FREQ … #define CST4331_SPROM_PRESENT … #define CST4331_OTP_PRESENT … #define CST4331_LDO_RF … #define CST4331_LDO_PAR … /* 4319 chip-specific ChipStatus register bits */ #define CST4319_SPI_CPULESSUSB … #define CST4319_SPI_CLK_POL … #define CST4319_SPI_CLK_PH … /* gpio [7:6], SDIO CIS selection */ #define CST4319_SPROM_OTP_SEL_MASK … #define CST4319_SPROM_OTP_SEL_SHIFT … /* use default CIS, OTP is powered up */ #define CST4319_DEFCIS_SEL … /* use SPROM, OTP is powered up */ #define CST4319_SPROM_SEL … /* use OTP, OTP is powered up */ #define CST4319_OTP_SEL … /* use SPROM, OTP is powered down */ #define CST4319_OTP_PWRDN … /* gpio [8], sdio/usb mode */ #define CST4319_SDIO_USB_MODE … #define CST4319_REMAP_SEL_MASK … #define CST4319_ILPDIV_EN … #define CST4319_XTAL_PD_POL … #define CST4319_LPO_SEL … #define CST4319_RES_INIT_MODE … /* PALDO is configured with external PNP */ #define CST4319_PALDO_EXTPNP … #define CST4319_CBUCK_MODE_MASK … #define CST4319_CBUCK_MODE_BURST … #define CST4319_CBUCK_MODE_LPBURST … #define CST4319_RCAL_VALID … #define CST4319_RCAL_VALUE_MASK … #define CST4319_RCAL_VALUE_SHIFT … /* 4336 chip-specific ChipStatus register bits */ #define CST4336_SPI_MODE_MASK … #define CST4336_SPROM_PRESENT … #define CST4336_OTP_PRESENT … #define CST4336_ARMREMAP_0 … #define CST4336_ILPDIV_EN_MASK … #define CST4336_ILPDIV_EN_SHIFT … #define CST4336_XTAL_PD_POL_MASK … #define CST4336_XTAL_PD_POL_SHIFT … #define CST4336_LPO_SEL_MASK … #define CST4336_LPO_SEL_SHIFT … #define CST4336_RES_INIT_MODE_MASK … #define CST4336_RES_INIT_MODE_SHIFT … #define CST4336_CBUCK_MODE_MASK … #define CST4336_CBUCK_MODE_SHIFT … /* 4313 chip-specific ChipStatus register bits */ #define CST4313_SPROM_PRESENT … #define CST4313_OTP_PRESENT … #define CST4313_SPROM_OTP_SEL_MASK … #define CST4313_SPROM_OTP_SEL_SHIFT … /* 4313 Chip specific ChipControl register bits */ /* 12 mA drive strengh for later 4313 */ #define CCTRL_4313_12MA_LED_DRIVE … /* Manufacturer Ids */ #define MFGID_ARM … #define MFGID_BRCM … #define MFGID_MIPS … /* Enumeration ROM registers */ #define ER_EROMENTRY … #define ER_REMAPCONTROL … #define ER_REMAPSELECT … #define ER_MASTERSELECT … #define ER_ITCR … #define ER_ITIP … /* Erom entries */ #define ER_TAG … #define ER_TAG1 … #define ER_VALID … #define ER_CI … #define ER_MP … #define ER_ADD … #define ER_END … #define ER_BAD … /* EROM CompIdentA */ #define CIA_MFG_MASK … #define CIA_MFG_SHIFT … #define CIA_CID_MASK … #define CIA_CID_SHIFT … #define CIA_CCL_MASK … #define CIA_CCL_SHIFT … /* EROM CompIdentB */ #define CIB_REV_MASK … #define CIB_REV_SHIFT … #define CIB_NSW_MASK … #define CIB_NSW_SHIFT … #define CIB_NMW_MASK … #define CIB_NMW_SHIFT … #define CIB_NSP_MASK … #define CIB_NSP_SHIFT … #define CIB_NMP_MASK … #define CIB_NMP_SHIFT … /* EROM AddrDesc */ #define AD_ADDR_MASK … #define AD_SP_MASK … #define AD_SP_SHIFT … #define AD_ST_MASK … #define AD_ST_SHIFT … #define AD_ST_SLAVE … #define AD_ST_BRIDGE … #define AD_ST_SWRAP … #define AD_ST_MWRAP … #define AD_SZ_MASK … #define AD_SZ_SHIFT … #define AD_SZ_4K … #define AD_SZ_8K … #define AD_SZ_16K … #define AD_SZ_SZD … #define AD_AG32 … #define AD_ADDR_ALIGN … #define AD_SZ_BASE … /* EROM SizeDesc */ #define SD_SZ_MASK … #define SD_SG32 … #define SD_SZ_ALIGN … /* PCI config space bit 4 for 4306c0 slow clock source */ #define PCI_CFG_GPIO_SCS … /* PCI config space GPIO 14 for Xtal power-up */ #define PCI_CFG_GPIO_XTAL … /* PCI config space GPIO 15 for PLL power-down */ #define PCI_CFG_GPIO_PLL … /* power control defines */ #define PLL_DELAY … #define FREF_DELAY … #define XTAL_ON_DELAY … /* resetctrl */ #define AIRC_RESET … #define NOREV … /* GPIO Based LED powersave defines */ #define DEFAULT_GPIO_ONTIME … #define DEFAULT_GPIO_OFFTIME … /* When Srom support present, fields in sromcontrol */ #define SRC_START … #define SRC_BUSY … #define SRC_OPCODE … #define SRC_OP_READ … #define SRC_OP_WRITE … #define SRC_OP_WRDIS … #define SRC_OP_WREN … #define SRC_OTPSEL … #define SRC_LOCK … #define SRC_SIZE_MASK … #define SRC_SIZE_1K … #define SRC_SIZE_4K … #define SRC_SIZE_16K … #define SRC_SIZE_SHIFT … #define SRC_PRESENT … /* External PA enable mask */ #define GPIO_CTRL_EPA_EN_MASK … #define DEFAULT_GPIOTIMERVAL … #define BADIDX … #define IS_SIM(chippkg) … #define GOODCOREADDR(x, b) … struct aidmp { … }; static bool ai_buscore_setup(struct si_info *sii, struct bcma_device *cc) { … } static struct si_info *ai_doattach(struct si_info *sii, struct bcma_bus *pbus) { … } /* * Allocate a si handle and do the attach. */ struct si_pub * ai_attach(struct bcma_bus *pbus) { … } /* may be called with core in reset */ void ai_detach(struct si_pub *sih) { … } /* * read/modify chipcommon core register. */ uint ai_cc_reg(struct si_pub *sih, uint regoff, u32 mask, u32 val) { … } /* return the slow clock source - LPO, XTAL, or PCI */ static uint ai_slowclk_src(struct si_pub *sih, struct bcma_device *cc) { … } /* * return the ILP (slowclock) min or max frequency * precondition: we've established the chip has dynamic clk control */ static uint ai_slowclk_freq(struct si_pub *sih, bool max_freq, struct bcma_device *cc) { … } static void ai_clkctl_setdelay(struct si_pub *sih, struct bcma_device *cc) { … } /* initialize power control delay registers */ void ai_clkctl_init(struct si_pub *sih) { … } /* * return the value suitable for writing to the * dot11 core FAST_PWRUP_DELAY register */ u16 ai_clkctl_fast_pwrup_delay(struct si_pub *sih) { … } /* * clock control policy function throught chipcommon * * set dynamic clk control mode (forceslow, forcefast, dynamic) * returns true if we are forcing fast clock * this is a wrapper over the next internal function * to allow flexible policy settings for outside caller */ bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode) { … } /* Enable BT-COEX & Ex-PA for 4313 */ void ai_epa_4313war(struct si_pub *sih) { … } /* check if the device is removed */ bool ai_deviceremoved(struct si_pub *sih) { … }
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