/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2004 - 2010 Ivo van Doorn <[email protected]> Copyright (C) 2010 Willow Garage <http://www.willowgarage.com> Copyright (C) 2009 Alban Browaeys <[email protected]> Copyright (C) 2009 Felix Fietkau <[email protected]> Copyright (C) 2009 Luis Correia <[email protected]> Copyright (C) 2009 Mattias Nissler <[email protected]> Copyright (C) 2009 Mark Asselstine <[email protected]> Copyright (C) 2009 Xose Vazquez Perez <[email protected]> Copyright (C) 2009 Bart Zolnierkiewicz <[email protected]> <http://rt2x00.serialmonkey.com> */ /* Module: rt2800 Abstract: Data structures and registers for the rt2800 modules. Supported chipsets: RT2800E, RT2800ED & RT2800U. */ #ifndef RT2800_H #define RT2800_H /* * RF chip defines. * * RF2820 2.4G 2T3R * RF2850 2.4G/5G 2T3R * RF2720 2.4G 1T2R * RF2750 2.4G/5G 1T2R * RF3020 2.4G 1T1R * RF2020 2.4G B/G * RF3021 2.4G 1T2R * RF3022 2.4G 2T2R * RF3052 2.4G/5G 2T2R * RF2853 2.4G/5G 3T3R * RF3320 2.4G 1T1R(RT3350/RT3370/RT3390) * RF3322 2.4G 2T2R(RT3352/RT3371/RT3372/RT3391/RT3392) * RF3053 2.4G/5G 3T3R(RT3563/RT3573/RT3593) * RF3853 2.4G/5G 3T3R(RT3883/RT3662) * RF5592 2.4G/5G 2T2R * RF3070 2.4G 1T1R * RF5360 2.4G 1T1R * RF5362 2.4G 1T1R * RF5370 2.4G 1T1R * RF5390 2.4G 1T1R */ #define RF2820 … #define RF2850 … #define RF2720 … #define RF2750 … #define RF3020 … #define RF2020 … #define RF3021 … #define RF3022 … #define RF3052 … #define RF2853 … #define RF3320 … #define RF3322 … #define RF3053 … #define RF5592 … #define RF3070 … #define RF3290 … #define RF3853 … #define RF5350 … #define RF5360 … #define RF5362 … #define RF5370 … #define RF5372 … #define RF5390 … #define RF5392 … #define RF7620 … /* * Chipset revisions. */ #define REV_RT2860C … #define REV_RT2860D … #define REV_RT2872E … #define REV_RT3070E … #define REV_RT3070F … #define REV_RT3071E … #define REV_RT3090E … #define REV_RT3390E … #define REV_RT3593E … #define REV_RT5390F … #define REV_RT5370G … #define REV_RT5390R … #define REV_RT5592C … #define DEFAULT_RSSI_OFFSET … /* * Register layout information. */ #define CSR_REG_BASE … #define CSR_REG_SIZE … #define EEPROM_BASE … #define EEPROM_SIZE … #define BBP_BASE … #define BBP_SIZE … #define RF_BASE … #define RF_SIZE … #define RFCSR_BASE … #define RFCSR_SIZE … /* * Number of TX queues. */ #define NUM_TX_QUEUES … /* * Registers. */ /* * MAC_CSR0_3290: MAC_CSR0 for RT3290 to identity MAC version number. */ #define MAC_CSR0_3290 … /* * E2PROM_CSR: PCI EEPROM control register. * RELOAD: Write 1 to reload eeprom content. * TYPE: 0: 93c46, 1:93c66. * LOAD_STATUS: 1:loading, 0:done. */ #define E2PROM_CSR … #define E2PROM_CSR_DATA_CLOCK … #define E2PROM_CSR_CHIP_SELECT … #define E2PROM_CSR_DATA_IN … #define E2PROM_CSR_DATA_OUT … #define E2PROM_CSR_TYPE … #define E2PROM_CSR_LOAD_STATUS … #define E2PROM_CSR_RELOAD … /* * CMB_CTRL_CFG */ #define CMB_CTRL … #define AUX_OPT_BIT0 … #define AUX_OPT_BIT1 … #define AUX_OPT_BIT2 … #define AUX_OPT_BIT3 … #define AUX_OPT_BIT4 … #define AUX_OPT_BIT5 … #define AUX_OPT_BIT6 … #define AUX_OPT_BIT7 … #define AUX_OPT_BIT8 … #define AUX_OPT_BIT9 … #define AUX_OPT_BIT10 … #define AUX_OPT_BIT11 … #define AUX_OPT_BIT12 … #define AUX_OPT_BIT13 … #define AUX_OPT_BIT14 … #define AUX_OPT_BIT15 … #define LDO25_LEVEL … #define LDO25_LARGEA … #define LDO25_FRC_ON … #define CMB_RSV … #define XTAL_RDY … #define PLL_LD … #define LDO_CORE_LEVEL … #define LDO_BGSEL … #define LDO3_EN … #define LDO0_EN … /* * EFUSE_CSR_3290: RT3290 EEPROM */ #define EFUSE_CTRL_3290 … /* * EFUSE_DATA3 of 3290 */ #define EFUSE_DATA3_3290 … /* * EFUSE_DATA2 of 3290 */ #define EFUSE_DATA2_3290 … /* * EFUSE_DATA1 of 3290 */ #define EFUSE_DATA1_3290 … /* * EFUSE_DATA0 of 3290 */ #define EFUSE_DATA0_3290 … /* * OSC_CTRL_CFG * Ring oscillator configuration */ #define OSC_CTRL … #define OSC_REF_CYCLE … #define OSC_RSV … #define OSC_CAL_CNT … #define OSC_CAL_ACK … #define OSC_CLK_32K_VLD … #define OSC_CAL_REQ … #define OSC_ROSC_EN … /* * COEX_CFG_0 */ #define COEX_CFG0 … #define COEX_CFG_ANT … /* * COEX_CFG_1 */ #define COEX_CFG1 … /* * COEX_CFG_2 */ #define COEX_CFG2 … #define BT_COEX_CFG1 … #define BT_COEX_CFG0 … #define WL_COEX_CFG1 … #define WL_COEX_CFG0 … /* * PLL_CTRL_CFG * PLL configuration register */ #define PLL_CTRL … #define PLL_RESERVED_INPUT1 … #define PLL_RESERVED_INPUT2 … #define PLL_CONTROL … #define PLL_LPF_R1 … #define PLL_LPF_C1_CTRL … #define PLL_LPF_C2_CTRL … #define PLL_CP_CURRENT_CTRL … #define PLL_PFD_DELAY_CTRL … #define PLL_LOCK_CTRL … #define PLL_VBGBK_EN … /* * WLAN_CTRL_CFG * RT3290 wlan configuration */ #define WLAN_FUN_CTRL … #define WLAN_EN … #define WLAN_CLK_EN … #define WLAN_RSV1 … #define WLAN_RESET … #define PCIE_APP0_CLK_REQ … #define FRC_WL_ANT_SET … #define INV_TR_SW0 … #define WLAN_GPIO_IN_BIT0 … #define WLAN_GPIO_IN_BIT1 … #define WLAN_GPIO_IN_BIT2 … #define WLAN_GPIO_IN_BIT3 … #define WLAN_GPIO_IN_BIT4 … #define WLAN_GPIO_IN_BIT5 … #define WLAN_GPIO_IN_BIT6 … #define WLAN_GPIO_IN_BIT7 … #define WLAN_GPIO_IN_BIT_ALL … #define WLAN_GPIO_OUT_BIT0 … #define WLAN_GPIO_OUT_BIT1 … #define WLAN_GPIO_OUT_BIT2 … #define WLAN_GPIO_OUT_BIT3 … #define WLAN_GPIO_OUT_BIT4 … #define WLAN_GPIO_OUT_BIT5 … #define WLAN_GPIO_OUT_BIT6 … #define WLAN_GPIO_OUT_BIT7 … #define WLAN_GPIO_OUT_BIT_ALL … #define WLAN_GPIO_OUT_OE_BIT0 … #define WLAN_GPIO_OUT_OE_BIT1 … #define WLAN_GPIO_OUT_OE_BIT2 … #define WLAN_GPIO_OUT_OE_BIT3 … #define WLAN_GPIO_OUT_OE_BIT4 … #define WLAN_GPIO_OUT_OE_BIT5 … #define WLAN_GPIO_OUT_OE_BIT6 … #define WLAN_GPIO_OUT_OE_BIT7 … #define WLAN_GPIO_OUT_OE_BIT_ALL … /* * AUX_CTRL: Aux/PCI-E related configuration */ #define AUX_CTRL … #define AUX_CTRL_WAKE_PCIE_EN … #define AUX_CTRL_FORCE_PCIE_CLK … /* * OPT_14: Unknown register used by rt3xxx devices. */ #define OPT_14_CSR … #define OPT_14_CSR_BIT0 … /* * INT_SOURCE_CSR: Interrupt source register. * Write one to clear corresponding bit. * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO */ #define INT_SOURCE_CSR … #define INT_SOURCE_CSR_RXDELAYINT … #define INT_SOURCE_CSR_TXDELAYINT … #define INT_SOURCE_CSR_RX_DONE … #define INT_SOURCE_CSR_AC0_DMA_DONE … #define INT_SOURCE_CSR_AC1_DMA_DONE … #define INT_SOURCE_CSR_AC2_DMA_DONE … #define INT_SOURCE_CSR_AC3_DMA_DONE … #define INT_SOURCE_CSR_HCCA_DMA_DONE … #define INT_SOURCE_CSR_MGMT_DMA_DONE … #define INT_SOURCE_CSR_MCU_COMMAND … #define INT_SOURCE_CSR_RXTX_COHERENT … #define INT_SOURCE_CSR_TBTT … #define INT_SOURCE_CSR_PRE_TBTT … #define INT_SOURCE_CSR_TX_FIFO_STATUS … #define INT_SOURCE_CSR_AUTO_WAKEUP … #define INT_SOURCE_CSR_GPTIMER … #define INT_SOURCE_CSR_RX_COHERENT … #define INT_SOURCE_CSR_TX_COHERENT … /* * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF. */ #define INT_MASK_CSR … #define INT_MASK_CSR_RXDELAYINT … #define INT_MASK_CSR_TXDELAYINT … #define INT_MASK_CSR_RX_DONE … #define INT_MASK_CSR_AC0_DMA_DONE … #define INT_MASK_CSR_AC1_DMA_DONE … #define INT_MASK_CSR_AC2_DMA_DONE … #define INT_MASK_CSR_AC3_DMA_DONE … #define INT_MASK_CSR_HCCA_DMA_DONE … #define INT_MASK_CSR_MGMT_DMA_DONE … #define INT_MASK_CSR_MCU_COMMAND … #define INT_MASK_CSR_RXTX_COHERENT … #define INT_MASK_CSR_TBTT … #define INT_MASK_CSR_PRE_TBTT … #define INT_MASK_CSR_TX_FIFO_STATUS … #define INT_MASK_CSR_AUTO_WAKEUP … #define INT_MASK_CSR_GPTIMER … #define INT_MASK_CSR_RX_COHERENT … #define INT_MASK_CSR_TX_COHERENT … /* * WPDMA_GLO_CFG */ #define WPDMA_GLO_CFG … #define WPDMA_GLO_CFG_ENABLE_TX_DMA … #define WPDMA_GLO_CFG_TX_DMA_BUSY … #define WPDMA_GLO_CFG_ENABLE_RX_DMA … #define WPDMA_GLO_CFG_RX_DMA_BUSY … #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE … #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE … #define WPDMA_GLO_CFG_BIG_ENDIAN … #define WPDMA_GLO_CFG_RX_HDR_SCATTER … #define WPDMA_GLO_CFG_HDR_SEG_LEN … /* * WPDMA_RST_IDX */ #define WPDMA_RST_IDX … #define WPDMA_RST_IDX_DTX_IDX0 … #define WPDMA_RST_IDX_DTX_IDX1 … #define WPDMA_RST_IDX_DTX_IDX2 … #define WPDMA_RST_IDX_DTX_IDX3 … #define WPDMA_RST_IDX_DTX_IDX4 … #define WPDMA_RST_IDX_DTX_IDX5 … #define WPDMA_RST_IDX_DRX_IDX0 … /* * DELAY_INT_CFG */ #define DELAY_INT_CFG … #define DELAY_INT_CFG_RXMAX_PTIME … #define DELAY_INT_CFG_RXMAX_PINT … #define DELAY_INT_CFG_RXDLY_INT_EN … #define DELAY_INT_CFG_TXMAX_PTIME … #define DELAY_INT_CFG_TXMAX_PINT … #define DELAY_INT_CFG_TXDLY_INT_EN … /* * WMM_AIFSN_CFG: Aifsn for each EDCA AC * AIFSN0: AC_VO * AIFSN1: AC_VI * AIFSN2: AC_BE * AIFSN3: AC_BK */ #define WMM_AIFSN_CFG … #define WMM_AIFSN_CFG_AIFSN0 … #define WMM_AIFSN_CFG_AIFSN1 … #define WMM_AIFSN_CFG_AIFSN2 … #define WMM_AIFSN_CFG_AIFSN3 … /* * WMM_CWMIN_CSR: CWmin for each EDCA AC * CWMIN0: AC_VO * CWMIN1: AC_VI * CWMIN2: AC_BE * CWMIN3: AC_BK */ #define WMM_CWMIN_CFG … #define WMM_CWMIN_CFG_CWMIN0 … #define WMM_CWMIN_CFG_CWMIN1 … #define WMM_CWMIN_CFG_CWMIN2 … #define WMM_CWMIN_CFG_CWMIN3 … /* * WMM_CWMAX_CSR: CWmax for each EDCA AC * CWMAX0: AC_VO * CWMAX1: AC_VI * CWMAX2: AC_BE * CWMAX3: AC_BK */ #define WMM_CWMAX_CFG … #define WMM_CWMAX_CFG_CWMAX0 … #define WMM_CWMAX_CFG_CWMAX1 … #define WMM_CWMAX_CFG_CWMAX2 … #define WMM_CWMAX_CFG_CWMAX3 … /* * AC_TXOP0: AC_VO/AC_VI TXOP register * AC0TXOP: AC_VO in unit of 32us * AC1TXOP: AC_VI in unit of 32us */ #define WMM_TXOP0_CFG … #define WMM_TXOP0_CFG_AC0TXOP … #define WMM_TXOP0_CFG_AC1TXOP … /* * AC_TXOP1: AC_BE/AC_BK TXOP register * AC2TXOP: AC_BE in unit of 32us * AC3TXOP: AC_BK in unit of 32us */ #define WMM_TXOP1_CFG … #define WMM_TXOP1_CFG_AC2TXOP … #define WMM_TXOP1_CFG_AC3TXOP … /* * GPIO_CTRL: * GPIO_CTRL_VALx: GPIO value * GPIO_CTRL_DIRx: GPIO direction: 0 = output; 1 = input */ #define GPIO_CTRL … #define GPIO_CTRL_VAL0 … #define GPIO_CTRL_VAL1 … #define GPIO_CTRL_VAL2 … #define GPIO_CTRL_VAL3 … #define GPIO_CTRL_VAL4 … #define GPIO_CTRL_VAL5 … #define GPIO_CTRL_VAL6 … #define GPIO_CTRL_VAL7 … #define GPIO_CTRL_DIR0 … #define GPIO_CTRL_DIR1 … #define GPIO_CTRL_DIR2 … #define GPIO_CTRL_DIR3 … #define GPIO_CTRL_DIR4 … #define GPIO_CTRL_DIR5 … #define GPIO_CTRL_DIR6 … #define GPIO_CTRL_DIR7 … #define GPIO_CTRL_VAL8 … #define GPIO_CTRL_VAL9 … #define GPIO_CTRL_VAL10 … #define GPIO_CTRL_DIR8 … #define GPIO_CTRL_DIR9 … #define GPIO_CTRL_DIR10 … /* * MCU_CMD_CFG */ #define MCU_CMD_CFG … /* * AC_VO register offsets */ #define TX_BASE_PTR0 … #define TX_MAX_CNT0 … #define TX_CTX_IDX0 … #define TX_DTX_IDX0 … /* * AC_VI register offsets */ #define TX_BASE_PTR1 … #define TX_MAX_CNT1 … #define TX_CTX_IDX1 … #define TX_DTX_IDX1 … /* * AC_BE register offsets */ #define TX_BASE_PTR2 … #define TX_MAX_CNT2 … #define TX_CTX_IDX2 … #define TX_DTX_IDX2 … /* * AC_BK register offsets */ #define TX_BASE_PTR3 … #define TX_MAX_CNT3 … #define TX_CTX_IDX3 … #define TX_DTX_IDX3 … /* * HCCA register offsets */ #define TX_BASE_PTR4 … #define TX_MAX_CNT4 … #define TX_CTX_IDX4 … #define TX_DTX_IDX4 … /* * MGMT register offsets */ #define TX_BASE_PTR5 … #define TX_MAX_CNT5 … #define TX_CTX_IDX5 … #define TX_DTX_IDX5 … /* * RX register offsets */ #define RX_BASE_PTR … #define RX_MAX_CNT … #define RX_CRX_IDX … #define RX_DRX_IDX … /* * USB_DMA_CFG * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns. * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes. * PHY_CLEAR: phy watch dog enable. * TX_CLEAR: Clear USB DMA TX path. * TXOP_HALT: Halt TXOP count down when TX buffer is full. * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation. * RX_BULK_EN: Enable USB DMA Rx. * TX_BULK_EN: Enable USB DMA Tx. * EP_OUT_VALID: OUT endpoint data valid. * RX_BUSY: USB DMA RX FSM busy. * TX_BUSY: USB DMA TX FSM busy. */ #define USB_DMA_CFG … #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT … #define USB_DMA_CFG_RX_BULK_AGG_LIMIT … #define USB_DMA_CFG_PHY_CLEAR … #define USB_DMA_CFG_TX_CLEAR … #define USB_DMA_CFG_TXOP_HALT … #define USB_DMA_CFG_RX_BULK_AGG_EN … #define USB_DMA_CFG_RX_BULK_EN … #define USB_DMA_CFG_TX_BULK_EN … #define USB_DMA_CFG_EP_OUT_VALID … #define USB_DMA_CFG_RX_BUSY … #define USB_DMA_CFG_TX_BUSY … /* * US_CYC_CNT * BT_MODE_EN: Bluetooth mode enable * CLOCK CYCLE: Clock cycle count in 1us. * PCI:0x21, PCIE:0x7d, USB:0x1e */ #define US_CYC_CNT … #define US_CYC_CNT_BT_MODE_EN … #define US_CYC_CNT_CLOCK_CYCLE … /* * PBF_SYS_CTRL * HOST_RAM_WRITE: enable Host program ram write selection */ #define PBF_SYS_CTRL … #define PBF_SYS_CTRL_READY … #define PBF_SYS_CTRL_HOST_RAM_WRITE … /* * HOST-MCU shared memory */ #define HOST_CMD_CSR … #define HOST_CMD_CSR_HOST_COMMAND … /* * PBF registers * Most are for debug. Driver doesn't touch PBF register. */ #define PBF_CFG … #define PBF_MAX_PCNT … #define PBF_CTRL … #define PBF_INT_STA … #define PBF_INT_ENA … /* * BCN_OFFSET0: */ #define BCN_OFFSET0 … #define BCN_OFFSET0_BCN0 … #define BCN_OFFSET0_BCN1 … #define BCN_OFFSET0_BCN2 … #define BCN_OFFSET0_BCN3 … /* * BCN_OFFSET1: */ #define BCN_OFFSET1 … #define BCN_OFFSET1_BCN4 … #define BCN_OFFSET1_BCN5 … #define BCN_OFFSET1_BCN6 … #define BCN_OFFSET1_BCN7 … /* * TXRXQ_PCNT: PBF register * PCNT_TX0Q: Page count for TX hardware queue 0 * PCNT_TX1Q: Page count for TX hardware queue 1 * PCNT_TX2Q: Page count for TX hardware queue 2 * PCNT_RX0Q: Page count for RX hardware queue */ #define TXRXQ_PCNT … #define TXRXQ_PCNT_TX0Q … #define TXRXQ_PCNT_TX1Q … #define TXRXQ_PCNT_TX2Q … #define TXRXQ_PCNT_RX0Q … /* * PBF register * Debug. Driver doesn't touch PBF register. */ #define PBF_DBG … /* * RF registers */ #define RF_CSR_CFG … #define RF_CSR_CFG_DATA … #define RF_CSR_CFG_REGNUM … #define RF_CSR_CFG_WRITE … #define RF_CSR_CFG_BUSY … /* * MT7620 RF registers (reversed order) */ #define RF_CSR_CFG_DATA_MT7620 … #define RF_CSR_CFG_REGNUM_MT7620 … #define RF_CSR_CFG_WRITE_MT7620 … #define RF_CSR_CFG_BUSY_MT7620 … /* undocumented registers for calibration of new MAC */ #define RF_CONTROL0 … #define RF_BYPASS0 … #define RF_CONTROL1 … #define RF_BYPASS1 … #define RF_CONTROL2 … #define RF_BYPASS2 … #define RF_CONTROL3 … #define RF_BYPASS3 … /* * EFUSE_CSR: RT30x0 EEPROM */ #define EFUSE_CTRL … #define EFUSE_CTRL_ADDRESS_IN … #define EFUSE_CTRL_MODE … #define EFUSE_CTRL_KICK … #define EFUSE_CTRL_PRESENT … /* * EFUSE_DATA0 */ #define EFUSE_DATA0 … /* * EFUSE_DATA1 */ #define EFUSE_DATA1 … /* * EFUSE_DATA2 */ #define EFUSE_DATA2 … /* * EFUSE_DATA3 */ #define EFUSE_DATA3 … /* * LDO_CFG0 */ #define LDO_CFG0 … #define LDO_CFG0_DELAY3 … #define LDO_CFG0_DELAY2 … #define LDO_CFG0_DELAY1 … #define LDO_CFG0_BGSEL … #define LDO_CFG0_LDO_CORE_VLEVEL … #define LD0_CFG0_LDO25_LEVEL … #define LDO_CFG0_LDO25_LARGEA … /* * GPIO_SWITCH */ #define GPIO_SWITCH … #define GPIO_SWITCH_0 … #define GPIO_SWITCH_1 … #define GPIO_SWITCH_2 … #define GPIO_SWITCH_3 … #define GPIO_SWITCH_4 … #define GPIO_SWITCH_5 … #define GPIO_SWITCH_6 … #define GPIO_SWITCH_7 … /* * FIXME: where the DEBUG_INDEX name come from? */ #define MAC_DEBUG_INDEX … #define MAC_DEBUG_INDEX_XTAL … /* * MAC Control/Status Registers(CSR). * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * MAC_CSR0: ASIC revision number. * ASIC_REV: 0 * ASIC_VER: 2860 or 2870 */ #define MAC_CSR0 … #define MAC_CSR0_REVISION … #define MAC_CSR0_CHIPSET … /* * MAC_SYS_CTRL: */ #define MAC_SYS_CTRL … #define MAC_SYS_CTRL_RESET_CSR … #define MAC_SYS_CTRL_RESET_BBP … #define MAC_SYS_CTRL_ENABLE_TX … #define MAC_SYS_CTRL_ENABLE_RX … #define MAC_SYS_CTRL_CONTINUOUS_TX … #define MAC_SYS_CTRL_LOOPBACK … #define MAC_SYS_CTRL_WLAN_HALT … #define MAC_SYS_CTRL_RX_TIMESTAMP … /* * MAC_ADDR_DW0: STA MAC register 0 */ #define MAC_ADDR_DW0 … #define MAC_ADDR_DW0_BYTE0 … #define MAC_ADDR_DW0_BYTE1 … #define MAC_ADDR_DW0_BYTE2 … #define MAC_ADDR_DW0_BYTE3 … /* * MAC_ADDR_DW1: STA MAC register 1 * UNICAST_TO_ME_MASK: * Used to mask off bits from byte 5 of the MAC address * to determine the UNICAST_TO_ME bit for RX frames. * The full mask is complemented by BSS_ID_MASK: * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK */ #define MAC_ADDR_DW1 … #define MAC_ADDR_DW1_BYTE4 … #define MAC_ADDR_DW1_BYTE5 … #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK … /* * MAC_BSSID_DW0: BSSID register 0 */ #define MAC_BSSID_DW0 … #define MAC_BSSID_DW0_BYTE0 … #define MAC_BSSID_DW0_BYTE1 … #define MAC_BSSID_DW0_BYTE2 … #define MAC_BSSID_DW0_BYTE3 … /* * MAC_BSSID_DW1: BSSID register 1 * BSS_ID_MASK: * 0: 1-BSSID mode (BSS index = 0) * 1: 2-BSSID mode (BSS index: Byte5, bit 0) * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1) * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2) * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the * BSSID. This will make sure that those bits will be ignored * when determining the MY_BSS of RX frames. */ #define MAC_BSSID_DW1 … #define MAC_BSSID_DW1_BYTE4 … #define MAC_BSSID_DW1_BYTE5 … #define MAC_BSSID_DW1_BSS_ID_MASK … #define MAC_BSSID_DW1_BSS_BCN_NUM … /* * MAX_LEN_CFG: Maximum frame length register. * MAX_MPDU: rt2860b max 16k bytes * MAX_PSDU: Maximum PSDU length * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */ #define MAX_LEN_CFG … #define MAX_LEN_CFG_MAX_MPDU … #define MAX_LEN_CFG_MAX_PSDU … #define MAX_LEN_CFG_MIN_PSDU … #define MAX_LEN_CFG_MIN_MPDU … /* * BBP_CSR_CFG: BBP serial control register * VALUE: Register value to program into BBP * REG_NUM: Selected BBP register * READ_CONTROL: 0 write BBP, 1 read BBP * BUSY: ASIC is busy executing BBP commands * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks * BBP_RW_MODE: 0 serial, 1 parallel */ #define BBP_CSR_CFG … #define BBP_CSR_CFG_VALUE … #define BBP_CSR_CFG_REGNUM … #define BBP_CSR_CFG_READ_CONTROL … #define BBP_CSR_CFG_BUSY … #define BBP_CSR_CFG_BBP_PAR_DUR … #define BBP_CSR_CFG_BBP_RW_MODE … /* * RF_CSR_CFG0: RF control register * REGID_AND_VALUE: Register value to program into RF * BITWIDTH: Selected RF register * STANDBYMODE: 0 high when standby, 1 low when standby * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate * BUSY: ASIC is busy executing RF commands */ #define RF_CSR_CFG0 … #define RF_CSR_CFG0_REGID_AND_VALUE … #define RF_CSR_CFG0_BITWIDTH … #define RF_CSR_CFG0_REG_VALUE_BW … #define RF_CSR_CFG0_STANDBYMODE … #define RF_CSR_CFG0_SEL … #define RF_CSR_CFG0_BUSY … /* * RF_CSR_CFG1: RF control register * REGID_AND_VALUE: Register value to program into RF * RFGAP: Gap between BB_CONTROL_RF and RF_LE * 0: 3 system clock cycle (37.5usec) * 1: 5 system clock cycle (62.5usec) */ #define RF_CSR_CFG1 … #define RF_CSR_CFG1_REGID_AND_VALUE … #define RF_CSR_CFG1_RFGAP … /* * RF_CSR_CFG2: RF control register * VALUE: Register value to program into RF */ #define RF_CSR_CFG2 … #define RF_CSR_CFG2_VALUE … /* * LED_CFG: LED control * ON_PERIOD: LED active time (ms) during TX (only used for LED mode 1) * OFF_PERIOD: LED inactive time (ms) during TX (only used for LED mode 1) * SLOW_BLINK_PERIOD: LED blink interval in seconds (only used for LED mode 2) * color LED's: * 0: off * 1: blinking upon TX2 * 2: periodic slow blinking * 3: always on * LED polarity: * 0: active low * 1: active high */ #define LED_CFG … #define LED_CFG_ON_PERIOD … #define LED_CFG_OFF_PERIOD … #define LED_CFG_SLOW_BLINK_PERIOD … #define LED_CFG_R_LED_MODE … #define LED_CFG_G_LED_MODE … #define LED_CFG_Y_LED_MODE … #define LED_CFG_LED_POLAR … /* * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7 * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15 * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7 * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15 * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes */ #define AMPDU_MAX_LEN_20M1S … #define AMPDU_MAX_LEN_20M2S … #define AMPDU_MAX_LEN_40M1S … #define AMPDU_MAX_LEN_40M2S … /* * AMPDU_BA_WINSIZE: Force BlockAck window size * FORCE_WINSIZE_ENABLE: * 0: Disable forcing of BlockAck window size * 1: Enable forcing of BlockAck window size, overwrites values BlockAck * window size values in the TXWI * FORCE_WINSIZE: BlockAck window size */ #define AMPDU_BA_WINSIZE … #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE … #define AMPDU_BA_WINSIZE_FORCE_WINSIZE … /* * XIFS_TIME_CFG: MAC timing * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX * when MAC doesn't reference BBP signal BBRXEND * EIFS: unit 1us * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer * */ #define XIFS_TIME_CFG … #define XIFS_TIME_CFG_CCKM_SIFS_TIME … #define XIFS_TIME_CFG_OFDM_SIFS_TIME … #define XIFS_TIME_CFG_OFDM_XIFS_TIME … #define XIFS_TIME_CFG_EIFS … #define XIFS_TIME_CFG_BB_RXEND_ENABLE … /* * BKOFF_SLOT_CFG: */ #define BKOFF_SLOT_CFG … #define BKOFF_SLOT_CFG_SLOT_TIME … #define BKOFF_SLOT_CFG_CC_DELAY_TIME … /* * NAV_TIME_CFG: */ #define NAV_TIME_CFG … #define NAV_TIME_CFG_SIFS … #define NAV_TIME_CFG_SLOT_TIME … #define NAV_TIME_CFG_EIFS … #define NAV_TIME_ZERO_SIFS … /* * CH_TIME_CFG: count as channel busy * EIFS_BUSY: Count EIFS as channel busy * NAV_BUSY: Count NAS as channel busy * RX_BUSY: Count RX as channel busy * TX_BUSY: Count TX as channel busy * TMR_EN: Enable channel statistics timer */ #define CH_TIME_CFG … #define CH_TIME_CFG_EIFS_BUSY … #define CH_TIME_CFG_NAV_BUSY … #define CH_TIME_CFG_RX_BUSY … #define CH_TIME_CFG_TX_BUSY … #define CH_TIME_CFG_TMR_EN … /* * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us */ #define PBF_LIFE_TIMER … /* * BCN_TIME_CFG: * BEACON_INTERVAL: in unit of 1/16 TU * TSF_TICKING: Enable TSF auto counting * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode * BEACON_GEN: Enable beacon generator */ #define BCN_TIME_CFG … #define BCN_TIME_CFG_BEACON_INTERVAL … #define BCN_TIME_CFG_TSF_TICKING … #define BCN_TIME_CFG_TSF_SYNC … #define BCN_TIME_CFG_TBTT_ENABLE … #define BCN_TIME_CFG_BEACON_GEN … #define BCN_TIME_CFG_TX_TIME_COMPENSATE … /* * TBTT_SYNC_CFG: * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots */ #define TBTT_SYNC_CFG … #define TBTT_SYNC_CFG_TBTT_ADJUST … #define TBTT_SYNC_CFG_BCN_EXP_WIN … #define TBTT_SYNC_CFG_BCN_AIFSN … #define TBTT_SYNC_CFG_BCN_CWMIN … /* * TSF_TIMER_DW0: Local lsb TSF timer, read-only */ #define TSF_TIMER_DW0 … #define TSF_TIMER_DW0_LOW_WORD … /* * TSF_TIMER_DW1: Local msb TSF timer, read-only */ #define TSF_TIMER_DW1 … #define TSF_TIMER_DW1_HIGH_WORD … /* * TBTT_TIMER: TImer remains till next TBTT, read-only */ #define TBTT_TIMER … /* * INT_TIMER_CFG: timer configuration * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU * GP_TIMER: period of general purpose timer in units of 1/16 TU */ #define INT_TIMER_CFG … #define INT_TIMER_CFG_PRE_TBTT_TIMER … #define INT_TIMER_CFG_GP_TIMER … /* * INT_TIMER_EN: GP-timer and pre-tbtt Int enable */ #define INT_TIMER_EN … #define INT_TIMER_EN_PRE_TBTT_TIMER … #define INT_TIMER_EN_GP_TIMER … /* * CH_IDLE_STA: channel idle time (in us) */ #define CH_IDLE_STA … /* * CH_BUSY_STA: channel busy time on primary channel (in us) */ #define CH_BUSY_STA … /* * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us) */ #define CH_BUSY_STA_SEC … /* * MAC_STATUS_CFG: * BBP_RF_BUSY: When set to 0, BBP and RF are stable. * if 1 or higher one of the 2 registers is busy. */ #define MAC_STATUS_CFG … #define MAC_STATUS_CFG_BBP_RF_BUSY … #define MAC_STATUS_CFG_BBP_RF_BUSY_TX … #define MAC_STATUS_CFG_BBP_RF_BUSY_RX … /* * PWR_PIN_CFG: */ #define PWR_PIN_CFG … /* * AUTOWAKEUP_CFG: Manual power control / status register * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set * AUTOWAKE: 0:sleep, 1:awake */ #define AUTOWAKEUP_CFG … #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME … #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE … #define AUTOWAKEUP_CFG_AUTOWAKE … /* * MIMO_PS_CFG: MIMO Power-save Configuration */ #define MIMO_PS_CFG … #define MIMO_PS_CFG_MMPS_BB_EN … #define MIMO_PS_CFG_MMPS_RX_ANT_NUM … #define MIMO_PS_CFG_MMPS_RF_EN … #define MIMO_PS_CFG_RX_STBY_POL … #define MIMO_PS_CFG_RX_RX_STBY0 … /* * EDCA_AC0_CFG: */ #define EDCA_AC0_CFG … #define EDCA_AC0_CFG_TX_OP … #define EDCA_AC0_CFG_AIFSN … #define EDCA_AC0_CFG_CWMIN … #define EDCA_AC0_CFG_CWMAX … /* * EDCA_AC1_CFG: */ #define EDCA_AC1_CFG … #define EDCA_AC1_CFG_TX_OP … #define EDCA_AC1_CFG_AIFSN … #define EDCA_AC1_CFG_CWMIN … #define EDCA_AC1_CFG_CWMAX … /* * EDCA_AC2_CFG: */ #define EDCA_AC2_CFG … #define EDCA_AC2_CFG_TX_OP … #define EDCA_AC2_CFG_AIFSN … #define EDCA_AC2_CFG_CWMIN … #define EDCA_AC2_CFG_CWMAX … /* * EDCA_AC3_CFG: */ #define EDCA_AC3_CFG … #define EDCA_AC3_CFG_TX_OP … #define EDCA_AC3_CFG_AIFSN … #define EDCA_AC3_CFG_CWMIN … #define EDCA_AC3_CFG_CWMAX … /* * EDCA_TID_AC_MAP: */ #define EDCA_TID_AC_MAP … /* * TX_PWR_CFG: */ #define TX_PWR_CFG_RATE0 … #define TX_PWR_CFG_RATE1 … #define TX_PWR_CFG_RATE2 … #define TX_PWR_CFG_RATE3 … #define TX_PWR_CFG_RATE4 … #define TX_PWR_CFG_RATE5 … #define TX_PWR_CFG_RATE6 … #define TX_PWR_CFG_RATE7 … /* * TX_PWR_CFG_0: */ #define TX_PWR_CFG_0 … #define TX_PWR_CFG_0_1MBS … #define TX_PWR_CFG_0_2MBS … #define TX_PWR_CFG_0_55MBS … #define TX_PWR_CFG_0_11MBS … #define TX_PWR_CFG_0_6MBS … #define TX_PWR_CFG_0_9MBS … #define TX_PWR_CFG_0_12MBS … #define TX_PWR_CFG_0_18MBS … /* bits for 3T devices */ #define TX_PWR_CFG_0_CCK1_CH0 … #define TX_PWR_CFG_0_CCK1_CH1 … #define TX_PWR_CFG_0_CCK5_CH0 … #define TX_PWR_CFG_0_CCK5_CH1 … #define TX_PWR_CFG_0_OFDM6_CH0 … #define TX_PWR_CFG_0_OFDM6_CH1 … #define TX_PWR_CFG_0_OFDM12_CH0 … #define TX_PWR_CFG_0_OFDM12_CH1 … /* bits for new 2T devices */ #define TX_PWR_CFG_0B_1MBS_2MBS … #define TX_PWR_CFG_0B_5MBS_11MBS … #define TX_PWR_CFG_0B_6MBS_9MBS … #define TX_PWR_CFG_0B_12MBS_18MBS … /* * TX_PWR_CFG_1: */ #define TX_PWR_CFG_1 … #define TX_PWR_CFG_1_24MBS … #define TX_PWR_CFG_1_36MBS … #define TX_PWR_CFG_1_48MBS … #define TX_PWR_CFG_1_54MBS … #define TX_PWR_CFG_1_MCS0 … #define TX_PWR_CFG_1_MCS1 … #define TX_PWR_CFG_1_MCS2 … #define TX_PWR_CFG_1_MCS3 … /* bits for 3T devices */ #define TX_PWR_CFG_1_OFDM24_CH0 … #define TX_PWR_CFG_1_OFDM24_CH1 … #define TX_PWR_CFG_1_OFDM48_CH0 … #define TX_PWR_CFG_1_OFDM48_CH1 … #define TX_PWR_CFG_1_MCS0_CH0 … #define TX_PWR_CFG_1_MCS0_CH1 … #define TX_PWR_CFG_1_MCS2_CH0 … #define TX_PWR_CFG_1_MCS2_CH1 … /* bits for new 2T devices */ #define TX_PWR_CFG_1B_24MBS_36MBS … #define TX_PWR_CFG_1B_48MBS … #define TX_PWR_CFG_1B_MCS0_MCS1 … #define TX_PWR_CFG_1B_MCS2_MCS3 … /* * TX_PWR_CFG_2: */ #define TX_PWR_CFG_2 … #define TX_PWR_CFG_2_MCS4 … #define TX_PWR_CFG_2_MCS5 … #define TX_PWR_CFG_2_MCS6 … #define TX_PWR_CFG_2_MCS7 … #define TX_PWR_CFG_2_MCS8 … #define TX_PWR_CFG_2_MCS9 … #define TX_PWR_CFG_2_MCS10 … #define TX_PWR_CFG_2_MCS11 … /* bits for 3T devices */ #define TX_PWR_CFG_2_MCS4_CH0 … #define TX_PWR_CFG_2_MCS4_CH1 … #define TX_PWR_CFG_2_MCS6_CH0 … #define TX_PWR_CFG_2_MCS6_CH1 … #define TX_PWR_CFG_2_MCS8_CH0 … #define TX_PWR_CFG_2_MCS8_CH1 … #define TX_PWR_CFG_2_MCS10_CH0 … #define TX_PWR_CFG_2_MCS10_CH1 … /* bits for new 2T devices */ #define TX_PWR_CFG_2B_MCS4_MCS5 … #define TX_PWR_CFG_2B_MCS6_MCS7 … #define TX_PWR_CFG_2B_MCS8_MCS9 … #define TX_PWR_CFG_2B_MCS10_MCS11 … /* * TX_PWR_CFG_3: */ #define TX_PWR_CFG_3 … #define TX_PWR_CFG_3_MCS12 … #define TX_PWR_CFG_3_MCS13 … #define TX_PWR_CFG_3_MCS14 … #define TX_PWR_CFG_3_MCS15 … #define TX_PWR_CFG_3_UNKNOWN1 … #define TX_PWR_CFG_3_UNKNOWN2 … #define TX_PWR_CFG_3_UNKNOWN3 … #define TX_PWR_CFG_3_UNKNOWN4 … /* bits for 3T devices */ #define TX_PWR_CFG_3_MCS12_CH0 … #define TX_PWR_CFG_3_MCS12_CH1 … #define TX_PWR_CFG_3_MCS14_CH0 … #define TX_PWR_CFG_3_MCS14_CH1 … #define TX_PWR_CFG_3_STBC0_CH0 … #define TX_PWR_CFG_3_STBC0_CH1 … #define TX_PWR_CFG_3_STBC2_CH0 … #define TX_PWR_CFG_3_STBC2_CH1 … /* bits for new 2T devices */ #define TX_PWR_CFG_3B_MCS12_MCS13 … #define TX_PWR_CFG_3B_MCS14 … #define TX_PWR_CFG_3B_STBC_MCS0_MCS1 … #define TX_PWR_CFG_3B_STBC_MCS2_MSC3 … /* * TX_PWR_CFG_4: */ #define TX_PWR_CFG_4 … #define TX_PWR_CFG_4_UNKNOWN5 … #define TX_PWR_CFG_4_UNKNOWN6 … #define TX_PWR_CFG_4_UNKNOWN7 … #define TX_PWR_CFG_4_UNKNOWN8 … /* bits for 3T devices */ #define TX_PWR_CFG_4_STBC4_CH0 … #define TX_PWR_CFG_4_STBC4_CH1 … #define TX_PWR_CFG_4_STBC6_CH0 … #define TX_PWR_CFG_4_STBC6_CH1 … /* bits for new 2T devices */ #define TX_PWR_CFG_4B_STBC_MCS4_MCS5 … #define TX_PWR_CFG_4B_STBC_MCS6 … /* * TX_PIN_CFG: */ #define TX_PIN_CFG … #define TX_PIN_CFG_PA_PE_DISABLE … #define TX_PIN_CFG_PA_PE_A0_EN … #define TX_PIN_CFG_PA_PE_G0_EN … #define TX_PIN_CFG_PA_PE_A1_EN … #define TX_PIN_CFG_PA_PE_G1_EN … #define TX_PIN_CFG_PA_PE_A0_POL … #define TX_PIN_CFG_PA_PE_G0_POL … #define TX_PIN_CFG_PA_PE_A1_POL … #define TX_PIN_CFG_PA_PE_G1_POL … #define TX_PIN_CFG_LNA_PE_A0_EN … #define TX_PIN_CFG_LNA_PE_G0_EN … #define TX_PIN_CFG_LNA_PE_A1_EN … #define TX_PIN_CFG_LNA_PE_G1_EN … #define TX_PIN_CFG_LNA_PE_A0_POL … #define TX_PIN_CFG_LNA_PE_G0_POL … #define TX_PIN_CFG_LNA_PE_A1_POL … #define TX_PIN_CFG_LNA_PE_G1_POL … #define TX_PIN_CFG_RFTR_EN … #define TX_PIN_CFG_RFTR_POL … #define TX_PIN_CFG_TRSW_EN … #define TX_PIN_CFG_TRSW_POL … #define TX_PIN_CFG_RFRX_EN … #define TX_PIN_CFG_RFRX_POL … #define TX_PIN_CFG_PA_PE_A2_EN … #define TX_PIN_CFG_PA_PE_G2_EN … #define TX_PIN_CFG_PA_PE_A2_POL … #define TX_PIN_CFG_PA_PE_G2_POL … #define TX_PIN_CFG_LNA_PE_A2_EN … #define TX_PIN_CFG_LNA_PE_G2_EN … #define TX_PIN_CFG_LNA_PE_A2_POL … #define TX_PIN_CFG_LNA_PE_G2_POL … /* * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz */ #define TX_BAND_CFG … #define TX_BAND_CFG_HT40_MINUS … #define TX_BAND_CFG_A … #define TX_BAND_CFG_BG … /* * TX_SW_CFG0: */ #define TX_SW_CFG0 … /* * TX_SW_CFG1: */ #define TX_SW_CFG1 … /* * TX_SW_CFG2: */ #define TX_SW_CFG2 … /* * TXOP_THRES_CFG: */ #define TXOP_THRES_CFG … /* * TXOP_CTRL_CFG: * TIMEOUT_TRUN_EN: Enable/Disable TXOP timeout truncation * AC_TRUN_EN: Enable/Disable truncation for AC change * TXRATEGRP_TRUN_EN: Enable/Disable truncation for TX rate group change * USER_MODE_TRUN_EN: Enable/Disable truncation for user TXOP mode * MIMO_PS_TRUN_EN: Enable/Disable truncation for MIMO PS RTS/CTS * RESERVED_TRUN_EN: Reserved * LSIG_TXOP_EN: Enable/Disable L-SIG TXOP protection * EXT_CCA_EN: Enable/Disable extension channel CCA reference (Defer 40Mhz * transmissions if extension CCA is clear). * EXT_CCA_DLY: Extension CCA signal delay time (unit: us) * EXT_CWMIN: CwMin for extension channel backoff * 0: Disabled * */ #define TXOP_CTRL_CFG … #define TXOP_CTRL_CFG_TIMEOUT_TRUN_EN … #define TXOP_CTRL_CFG_AC_TRUN_EN … #define TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN … #define TXOP_CTRL_CFG_USER_MODE_TRUN_EN … #define TXOP_CTRL_CFG_MIMO_PS_TRUN_EN … #define TXOP_CTRL_CFG_RESERVED_TRUN_EN … #define TXOP_CTRL_CFG_LSIG_TXOP_EN … #define TXOP_CTRL_CFG_EXT_CCA_EN … #define TXOP_CTRL_CFG_EXT_CCA_DLY … #define TXOP_CTRL_CFG_EXT_CWMIN … /* * TX_RTS_CFG: * RTS_THRES: unit:byte * RTS_FBK_EN: enable rts rate fallback */ #define TX_RTS_CFG … #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT … #define TX_RTS_CFG_RTS_THRES … #define TX_RTS_CFG_RTS_FBK_EN … /* * TX_TIMEOUT_CFG: * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation. * it is recommended that: * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */ #define TX_TIMEOUT_CFG … #define TX_TIMEOUT_CFG_MPDU_LIFETIME … #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT … #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT … /* * TX_RTY_CFG: * SHORT_RTY_LIMIT: short retry limit * LONG_RTY_LIMIT: long retry limit * LONG_RTY_THRE: Long retry threshoold * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode * 0:expired by retry limit, 1: expired by mpdu life timer * AGG_RTY_MODE: Aggregate MPDU retry mode * 0:expired by retry limit, 1: expired by mpdu life timer * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable */ #define TX_RTY_CFG … #define TX_RTY_CFG_SHORT_RTY_LIMIT … #define TX_RTY_CFG_LONG_RTY_LIMIT … #define TX_RTY_CFG_LONG_RTY_THRE … #define TX_RTY_CFG_NON_AGG_RTY_MODE … #define TX_RTY_CFG_AGG_RTY_MODE … #define TX_RTY_CFG_TX_AUTO_FB_ENABLE … /* * TX_LINK_CFG: * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us * MFB_ENABLE: TX apply remote MFB 1:enable * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable * 0: not apply remote remote unsolicit (MFS=7) * TX_MRQ_EN: MCS request TX enable * TX_RDG_EN: RDG TX enable * TX_CF_ACK_EN: Piggyback CF-ACK enable * REMOTE_MFB: remote MCS feedback * REMOTE_MFS: remote MCS feedback sequence number */ #define TX_LINK_CFG … #define TX_LINK_CFG_REMOTE_MFB_LIFETIME … #define TX_LINK_CFG_MFB_ENABLE … #define TX_LINK_CFG_REMOTE_UMFS_ENABLE … #define TX_LINK_CFG_TX_MRQ_EN … #define TX_LINK_CFG_TX_RDG_EN … #define TX_LINK_CFG_TX_CF_ACK_EN … #define TX_LINK_CFG_REMOTE_MFB … #define TX_LINK_CFG_REMOTE_MFS … /* * HT_FBK_CFG0: */ #define HT_FBK_CFG0 … #define HT_FBK_CFG0_HTMCS0FBK … #define HT_FBK_CFG0_HTMCS1FBK … #define HT_FBK_CFG0_HTMCS2FBK … #define HT_FBK_CFG0_HTMCS3FBK … #define HT_FBK_CFG0_HTMCS4FBK … #define HT_FBK_CFG0_HTMCS5FBK … #define HT_FBK_CFG0_HTMCS6FBK … #define HT_FBK_CFG0_HTMCS7FBK … /* * HT_FBK_CFG1: */ #define HT_FBK_CFG1 … #define HT_FBK_CFG1_HTMCS8FBK … #define HT_FBK_CFG1_HTMCS9FBK … #define HT_FBK_CFG1_HTMCS10FBK … #define HT_FBK_CFG1_HTMCS11FBK … #define HT_FBK_CFG1_HTMCS12FBK … #define HT_FBK_CFG1_HTMCS13FBK … #define HT_FBK_CFG1_HTMCS14FBK … #define HT_FBK_CFG1_HTMCS15FBK … /* * LG_FBK_CFG0: */ #define LG_FBK_CFG0 … #define LG_FBK_CFG0_OFDMMCS0FBK … #define LG_FBK_CFG0_OFDMMCS1FBK … #define LG_FBK_CFG0_OFDMMCS2FBK … #define LG_FBK_CFG0_OFDMMCS3FBK … #define LG_FBK_CFG0_OFDMMCS4FBK … #define LG_FBK_CFG0_OFDMMCS5FBK … #define LG_FBK_CFG0_OFDMMCS6FBK … #define LG_FBK_CFG0_OFDMMCS7FBK … /* * LG_FBK_CFG1: */ #define LG_FBK_CFG1 … #define LG_FBK_CFG0_CCKMCS0FBK … #define LG_FBK_CFG0_CCKMCS1FBK … #define LG_FBK_CFG0_CCKMCS2FBK … #define LG_FBK_CFG0_CCKMCS3FBK … /* * CCK_PROT_CFG: CCK Protection * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd) * PROTECT_CTRL: Protection control frame type for CCK TX * 0:none, 1:RTS/CTS, 2:CTS-to-self * PROTECT_NAV_SHORT: TXOP protection type for CCK TX with short NAV * PROTECT_NAV_LONG: TXOP protection type for CCK TX with long NAV * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow * RTS_TH_EN: RTS threshold enable on CCK TX */ #define CCK_PROT_CFG … #define CCK_PROT_CFG_PROTECT_RATE … #define CCK_PROT_CFG_PROTECT_CTRL … #define CCK_PROT_CFG_PROTECT_NAV_SHORT … #define CCK_PROT_CFG_PROTECT_NAV_LONG … #define CCK_PROT_CFG_TX_OP_ALLOW_CCK … #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM … #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 … #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 … #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 … #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 … #define CCK_PROT_CFG_RTS_TH_EN … /* * OFDM_PROT_CFG: OFDM Protection */ #define OFDM_PROT_CFG … #define OFDM_PROT_CFG_PROTECT_RATE … #define OFDM_PROT_CFG_PROTECT_CTRL … #define OFDM_PROT_CFG_PROTECT_NAV_SHORT … #define OFDM_PROT_CFG_PROTECT_NAV_LONG … #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK … #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM … #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 … #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 … #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 … #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 … #define OFDM_PROT_CFG_RTS_TH_EN … /* * MM20_PROT_CFG: MM20 Protection */ #define MM20_PROT_CFG … #define MM20_PROT_CFG_PROTECT_RATE … #define MM20_PROT_CFG_PROTECT_CTRL … #define MM20_PROT_CFG_PROTECT_NAV_SHORT … #define MM20_PROT_CFG_PROTECT_NAV_LONG … #define MM20_PROT_CFG_TX_OP_ALLOW_CCK … #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM … #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 … #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 … #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 … #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 … #define MM20_PROT_CFG_RTS_TH_EN … /* * MM40_PROT_CFG: MM40 Protection */ #define MM40_PROT_CFG … #define MM40_PROT_CFG_PROTECT_RATE … #define MM40_PROT_CFG_PROTECT_CTRL … #define MM40_PROT_CFG_PROTECT_NAV_SHORT … #define MM40_PROT_CFG_PROTECT_NAV_LONG … #define MM40_PROT_CFG_TX_OP_ALLOW_CCK … #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM … #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 … #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 … #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 … #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 … #define MM40_PROT_CFG_RTS_TH_EN … /* * GF20_PROT_CFG: GF20 Protection */ #define GF20_PROT_CFG … #define GF20_PROT_CFG_PROTECT_RATE … #define GF20_PROT_CFG_PROTECT_CTRL … #define GF20_PROT_CFG_PROTECT_NAV_SHORT … #define GF20_PROT_CFG_PROTECT_NAV_LONG … #define GF20_PROT_CFG_TX_OP_ALLOW_CCK … #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM … #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 … #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 … #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 … #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 … #define GF20_PROT_CFG_RTS_TH_EN … /* * GF40_PROT_CFG: GF40 Protection */ #define GF40_PROT_CFG … #define GF40_PROT_CFG_PROTECT_RATE … #define GF40_PROT_CFG_PROTECT_CTRL … #define GF40_PROT_CFG_PROTECT_NAV_SHORT … #define GF40_PROT_CFG_PROTECT_NAV_LONG … #define GF40_PROT_CFG_TX_OP_ALLOW_CCK … #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM … #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 … #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 … #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 … #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 … #define GF40_PROT_CFG_RTS_TH_EN … /* * EXP_CTS_TIME: */ #define EXP_CTS_TIME … /* * EXP_ACK_TIME: */ #define EXP_ACK_TIME … /* * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate * Not available for legacy SoCs */ #define HT_FBK_TO_LEGACY … /* TX_PWR_CFG_5 */ #define TX_PWR_CFG_5 … #define TX_PWR_CFG_5_MCS16_CH0 … #define TX_PWR_CFG_5_MCS16_CH1 … #define TX_PWR_CFG_5_MCS16_CH2 … #define TX_PWR_CFG_5_MCS18_CH0 … #define TX_PWR_CFG_5_MCS18_CH1 … #define TX_PWR_CFG_5_MCS18_CH2 … /* TX_PWR_CFG_6 */ #define TX_PWR_CFG_6 … #define TX_PWR_CFG_6_MCS20_CH0 … #define TX_PWR_CFG_6_MCS20_CH1 … #define TX_PWR_CFG_6_MCS20_CH2 … #define TX_PWR_CFG_6_MCS22_CH0 … #define TX_PWR_CFG_6_MCS22_CH1 … #define TX_PWR_CFG_6_MCS22_CH2 … /* TX_PWR_CFG_0_EXT */ #define TX_PWR_CFG_0_EXT … #define TX_PWR_CFG_0_EXT_CCK1_CH2 … #define TX_PWR_CFG_0_EXT_CCK5_CH2 … #define TX_PWR_CFG_0_EXT_OFDM6_CH2 … #define TX_PWR_CFG_0_EXT_OFDM12_CH2 … /* TX_PWR_CFG_1_EXT */ #define TX_PWR_CFG_1_EXT … #define TX_PWR_CFG_1_EXT_OFDM24_CH2 … #define TX_PWR_CFG_1_EXT_OFDM48_CH2 … #define TX_PWR_CFG_1_EXT_MCS0_CH2 … #define TX_PWR_CFG_1_EXT_MCS2_CH2 … /* TX_PWR_CFG_2_EXT */ #define TX_PWR_CFG_2_EXT … #define TX_PWR_CFG_2_EXT_MCS4_CH2 … #define TX_PWR_CFG_2_EXT_MCS6_CH2 … #define TX_PWR_CFG_2_EXT_MCS8_CH2 … #define TX_PWR_CFG_2_EXT_MCS10_CH2 … /* TX_PWR_CFG_3_EXT */ #define TX_PWR_CFG_3_EXT … #define TX_PWR_CFG_3_EXT_MCS12_CH2 … #define TX_PWR_CFG_3_EXT_MCS14_CH2 … #define TX_PWR_CFG_3_EXT_STBC0_CH2 … #define TX_PWR_CFG_3_EXT_STBC2_CH2 … /* TX_PWR_CFG_4_EXT */ #define TX_PWR_CFG_4_EXT … #define TX_PWR_CFG_4_EXT_STBC4_CH2 … #define TX_PWR_CFG_4_EXT_STBC6_CH2 … /* TXn_RF_GAIN_CORRECT: RF Gain Correction for each RF_ALC[3:2] * Unit: 0.1 dB, Range: -3.2 dB to 3.1 dB */ #define TX0_RF_GAIN_CORRECT … #define TX0_RF_GAIN_CORRECT_GAIN_CORR_0 … #define TX0_RF_GAIN_CORRECT_GAIN_CORR_1 … #define TX0_RF_GAIN_CORRECT_GAIN_CORR_2 … #define TX0_RF_GAIN_CORRECT_GAIN_CORR_3 … #define TX1_RF_GAIN_CORRECT … #define TX1_RF_GAIN_CORRECT_GAIN_CORR_0 … #define TX1_RF_GAIN_CORRECT_GAIN_CORR_1 … #define TX1_RF_GAIN_CORRECT_GAIN_CORR_2 … #define TX1_RF_GAIN_CORRECT_GAIN_CORR_3 … /* TXn_RF_GAIN_ATTEN: TXn RF Gain Attenuation Level * Format: 7-bit, signed value * Unit: 0.5 dB, Range: -20 dB to -5 dB */ #define TX0_RF_GAIN_ATTEN … #define TX0_RF_GAIN_ATTEN_LEVEL_0 … #define TX0_RF_GAIN_ATTEN_LEVEL_1 … #define TX0_RF_GAIN_ATTEN_LEVEL_2 … #define TX0_RF_GAIN_ATTEN_LEVEL_3 … #define TX1_RF_GAIN_ATTEN … #define TX1_RF_GAIN_ATTEN_LEVEL_0 … #define TX1_RF_GAIN_ATTEN_LEVEL_1 … #define TX1_RF_GAIN_ATTEN_LEVEL_2 … #define TX1_RF_GAIN_ATTEN_LEVEL_3 … /* TX_ALC_CFG_0: TX Automatic Level Control Configuration 0 * TX_ALC_LIMIT_n: TXn upper limit * TX_ALC_CH_INIT_n: TXn channel initial transmission gain * Unit: 0.5 dB, Range: 0 to 23.5 dB */ #define TX_ALC_CFG_0 … #define TX_ALC_CFG_0_CH_INIT_0 … #define TX_ALC_CFG_0_CH_INIT_1 … #define TX_ALC_CFG_0_LIMIT_0 … #define TX_ALC_CFG_0_LIMIT_1 … /* TX_ALC_CFG_1: TX Automatic Level Control Configuration 1 * TX_TEMP_COMP: TX Power Temperature Compensation * Unit: 0.5 dB, Range: -10 dB to 10 dB * TXn_GAIN_FINE: TXn Gain Fine Adjustment * Unit: 0.1 dB, Range: -0.8 dB to 0.7 dB * RF_TOS_DLY: Sets the RF_TOS_EN assertion delay after * deassertion of PA_PE. * Unit: 0.25 usec * TXn_RF_GAIN_ATTEN: TXn RF gain attentuation selector * RF_TOS_TIMEOUT: time-out value for RF_TOS_ENABLE * deassertion if RF_TOS_DONE is missing. * Unit: 0.25 usec * RF_TOS_ENABLE: TX offset calibration enable * ROS_BUSY_EN: RX offset calibration busy enable */ #define TX_ALC_CFG_1 … #define TX_ALC_CFG_1_TX_TEMP_COMP … #define TX_ALC_CFG_1_TX0_GAIN_FINE … #define TX_ALC_CFG_1_TX1_GAIN_FINE … #define TX_ALC_CFG_1_RF_TOS_DLY … #define TX_ALC_CFG_1_TX0_RF_GAIN_ATTEN … #define TX_ALC_CFG_1_TX1_RF_GAIN_ATTEN … #define TX_ALC_CFG_1_RF_TOS_TIMEOUT … #define TX_ALC_CFG_1_RF_TOS_ENABLE … #define TX_ALC_CFG_1_ROS_BUSY_EN … /* TXn_BB_GAIN_ATTEN: TXn RF Gain Attenuation Level * Format: 5-bit signed values * Unit: 0.5 dB, Range: -8 dB to 7 dB */ #define TX0_BB_GAIN_ATTEN … #define TX0_BB_GAIN_ATTEN_LEVEL_0 … #define TX0_BB_GAIN_ATTEN_LEVEL_1 … #define TX0_BB_GAIN_ATTEN_LEVEL_2 … #define TX0_BB_GAIN_ATTEN_LEVEL_3 … #define TX1_BB_GAIN_ATTEN … #define TX1_BB_GAIN_ATTEN_LEVEL_0 … #define TX1_BB_GAIN_ATTEN_LEVEL_1 … #define TX1_BB_GAIN_ATTEN_LEVEL_2 … #define TX1_BB_GAIN_ATTEN_LEVEL_3 … /* TX_ALC_VGA3: TX Automatic Level Correction Variable Gain Amplifier 3 */ #define TX_ALC_VGA3 … #define TX_ALC_VGA3_TX0_ALC_VGA3 … #define TX_ALC_VGA3_TX1_ALC_VGA3 … #define TX_ALC_VGA3_TX0_ALC_VGA2 … #define TX_ALC_VGA3_TX1_ALC_VGA2 … /* TX_PWR_CFG_7 */ #define TX_PWR_CFG_7 … #define TX_PWR_CFG_7_OFDM54_CH0 … #define TX_PWR_CFG_7_OFDM54_CH1 … #define TX_PWR_CFG_7_OFDM54_CH2 … #define TX_PWR_CFG_7_MCS7_CH0 … #define TX_PWR_CFG_7_MCS7_CH1 … #define TX_PWR_CFG_7_MCS7_CH2 … /* bits for new 2T devices */ #define TX_PWR_CFG_7B_54MBS … #define TX_PWR_CFG_7B_MCS7 … /* TX_PWR_CFG_8 */ #define TX_PWR_CFG_8 … #define TX_PWR_CFG_8_MCS15_CH0 … #define TX_PWR_CFG_8_MCS15_CH1 … #define TX_PWR_CFG_8_MCS15_CH2 … #define TX_PWR_CFG_8_MCS23_CH0 … #define TX_PWR_CFG_8_MCS23_CH1 … #define TX_PWR_CFG_8_MCS23_CH2 … /* bits for new 2T devices */ #define TX_PWR_CFG_8B_MCS15 … /* TX_PWR_CFG_9 */ #define TX_PWR_CFG_9 … #define TX_PWR_CFG_9_STBC7_CH0 … #define TX_PWR_CFG_9_STBC7_CH1 … #define TX_PWR_CFG_9_STBC7_CH2 … /* bits for new 2T devices */ #define TX_PWR_CFG_9B_STBC_MCS7 … /* * TX_TXBF_CFG: */ #define TX_TXBF_CFG_0 … #define TX_TXBF_CFG_1 … #define TX_TXBF_CFG_2 … #define TX_TXBF_CFG_3 … /* * TX_FBK_CFG_3S: */ #define TX_FBK_CFG_3S_0 … #define TX_FBK_CFG_3S_1 … /* * RX_FILTER_CFG: RX configuration register. */ #define RX_FILTER_CFG … #define RX_FILTER_CFG_DROP_CRC_ERROR … #define RX_FILTER_CFG_DROP_PHY_ERROR … #define RX_FILTER_CFG_DROP_NOT_TO_ME … #define RX_FILTER_CFG_DROP_NOT_MY_BSSD … #define RX_FILTER_CFG_DROP_VER_ERROR … #define RX_FILTER_CFG_DROP_MULTICAST … #define RX_FILTER_CFG_DROP_BROADCAST … #define RX_FILTER_CFG_DROP_DUPLICATE … #define RX_FILTER_CFG_DROP_CF_END_ACK … #define RX_FILTER_CFG_DROP_CF_END … #define RX_FILTER_CFG_DROP_ACK … #define RX_FILTER_CFG_DROP_CTS … #define RX_FILTER_CFG_DROP_RTS … #define RX_FILTER_CFG_DROP_PSPOLL … #define RX_FILTER_CFG_DROP_BA … #define RX_FILTER_CFG_DROP_BAR … #define RX_FILTER_CFG_DROP_CNTL … /* * AUTO_RSP_CFG: * AUTORESPONDER: 0: disable, 1: enable * BAC_ACK_POLICY: 0:long, 1:short preamble * CTS_40_MMODE: Response CTS 40MHz duplicate mode * CTS_40_MREF: Response CTS 40MHz duplicate mode * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble * DUAL_CTS_EN: Power bit value in control frame * ACK_CTS_PSM_BIT:Power bit value in control frame */ #define AUTO_RSP_CFG … #define AUTO_RSP_CFG_AUTORESPONDER … #define AUTO_RSP_CFG_BAC_ACK_POLICY … #define AUTO_RSP_CFG_CTS_40_MMODE … #define AUTO_RSP_CFG_CTS_40_MREF … #define AUTO_RSP_CFG_AR_PREAMBLE … #define AUTO_RSP_CFG_DUAL_CTS_EN … #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT … /* * LEGACY_BASIC_RATE: */ #define LEGACY_BASIC_RATE … /* * HT_BASIC_RATE: */ #define HT_BASIC_RATE … /* * HT_CTRL_CFG: */ #define HT_CTRL_CFG … /* * SIFS_COST_CFG: */ #define SIFS_COST_CFG … /* * RX_PARSER_CFG: * Set NAV for all received frames */ #define RX_PARSER_CFG … /* * TX_SEC_CNT0: */ #define TX_SEC_CNT0 … /* * RX_SEC_CNT0: */ #define RX_SEC_CNT0 … /* * CCMP_FC_MUTE: */ #define CCMP_FC_MUTE … /* * TXOP_HLDR_ADDR0: */ #define TXOP_HLDR_ADDR0 … /* * TXOP_HLDR_ADDR1: */ #define TXOP_HLDR_ADDR1 … /* * TXOP_HLDR_ET: */ #define TXOP_HLDR_ET … /* * QOS_CFPOLL_RA_DW0: */ #define QOS_CFPOLL_RA_DW0 … /* * QOS_CFPOLL_RA_DW1: */ #define QOS_CFPOLL_RA_DW1 … /* * QOS_CFPOLL_QC: */ #define QOS_CFPOLL_QC … /* * RX_STA_CNT0: RX PLCP error count & RX CRC error count */ #define RX_STA_CNT0 … #define RX_STA_CNT0_CRC_ERR … #define RX_STA_CNT0_PHY_ERR … /* * RX_STA_CNT1: RX False CCA count & RX LONG frame count */ #define RX_STA_CNT1 … #define RX_STA_CNT1_FALSE_CCA … #define RX_STA_CNT1_PLCP_ERR … /* * RX_STA_CNT2: */ #define RX_STA_CNT2 … #define RX_STA_CNT2_RX_DUPLI_COUNT … #define RX_STA_CNT2_RX_FIFO_OVERFLOW … /* * TX_STA_CNT0: TX Beacon count */ #define TX_STA_CNT0 … #define TX_STA_CNT0_TX_FAIL_COUNT … #define TX_STA_CNT0_TX_BEACON_COUNT … /* * TX_STA_CNT1: TX tx count */ #define TX_STA_CNT1 … #define TX_STA_CNT1_TX_SUCCESS … #define TX_STA_CNT1_TX_RETRANSMIT … /* * TX_STA_CNT2: TX tx count */ #define TX_STA_CNT2 … #define TX_STA_CNT2_TX_ZERO_LEN_COUNT … #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT … /* * TX_STA_FIFO: TX Result for specific PID status fifo register. * * This register is implemented as FIFO with 16 entries in the HW. Each * register read fetches the next tx result. If the FIFO is full because * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS) * triggered, the hw seems to simply drop further tx results. * * VALID: 1: this tx result is valid * 0: no valid tx result -> driver should stop reading * PID_TYPE: The PID latched from the PID field in the TXWI, can be used * to match a frame with its tx result (even though the PID is * only 4 bits wide). * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3) * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3) * This identification number is calculated by ((idx % 3) + 1). * TX_SUCCESS: Indicates tx success (1) or failure (0) * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0) * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0) * WCID: The wireless client ID. * MCS: The tx rate used during the last transmission of this frame, be it * successful or not. * PHYMODE: The phymode used for the transmission. */ #define TX_STA_FIFO … #define TX_STA_FIFO_VALID … #define TX_STA_FIFO_PID_TYPE … #define TX_STA_FIFO_PID_QUEUE … #define TX_STA_FIFO_PID_ENTRY … #define TX_STA_FIFO_TX_SUCCESS … #define TX_STA_FIFO_TX_AGGRE … #define TX_STA_FIFO_TX_ACK_REQUIRED … #define TX_STA_FIFO_WCID … #define TX_STA_FIFO_SUCCESS_RATE … #define TX_STA_FIFO_MCS … #define TX_STA_FIFO_BW … #define TX_STA_FIFO_SGI … #define TX_STA_FIFO_PHYMODE … /* * TX_AGG_CNT: Debug counter */ #define TX_AGG_CNT … #define TX_AGG_CNT_NON_AGG_TX_COUNT … #define TX_AGG_CNT_AGG_TX_COUNT … /* * TX_AGG_CNT0: */ #define TX_AGG_CNT0 … #define TX_AGG_CNT0_AGG_SIZE_1_COUNT … #define TX_AGG_CNT0_AGG_SIZE_2_COUNT … /* * TX_AGG_CNT1: */ #define TX_AGG_CNT1 … #define TX_AGG_CNT1_AGG_SIZE_3_COUNT … #define TX_AGG_CNT1_AGG_SIZE_4_COUNT … /* * TX_AGG_CNT2: */ #define TX_AGG_CNT2 … #define TX_AGG_CNT2_AGG_SIZE_5_COUNT … #define TX_AGG_CNT2_AGG_SIZE_6_COUNT … /* * TX_AGG_CNT3: */ #define TX_AGG_CNT3 … #define TX_AGG_CNT3_AGG_SIZE_7_COUNT … #define TX_AGG_CNT3_AGG_SIZE_8_COUNT … /* * TX_AGG_CNT4: */ #define TX_AGG_CNT4 … #define TX_AGG_CNT4_AGG_SIZE_9_COUNT … #define TX_AGG_CNT4_AGG_SIZE_10_COUNT … /* * TX_AGG_CNT5: */ #define TX_AGG_CNT5 … #define TX_AGG_CNT5_AGG_SIZE_11_COUNT … #define TX_AGG_CNT5_AGG_SIZE_12_COUNT … /* * TX_AGG_CNT6: */ #define TX_AGG_CNT6 … #define TX_AGG_CNT6_AGG_SIZE_13_COUNT … #define TX_AGG_CNT6_AGG_SIZE_14_COUNT … /* * TX_AGG_CNT7: */ #define TX_AGG_CNT7 … #define TX_AGG_CNT7_AGG_SIZE_15_COUNT … #define TX_AGG_CNT7_AGG_SIZE_16_COUNT … /* * MPDU_DENSITY_CNT: * TX_ZERO_DEL: TX zero length delimiter count * RX_ZERO_DEL: RX zero length delimiter count */ #define MPDU_DENSITY_CNT … #define MPDU_DENSITY_CNT_TX_ZERO_DEL … #define MPDU_DENSITY_CNT_RX_ZERO_DEL … /* * Security key table memory. * * The pairwise key table shares some memory with the beacon frame * buffers 6 and 7. That basically means that when beacon 6 & 7 * are used we should only use the reduced pairwise key table which * has a maximum of 222 entries. * * --------------------------------------------- * |0x4000 | Pairwise Key | Reduced Pairwise | * | | Table | Key Table | * | | Size: 256 * 32 | Size: 222 * 32 | * |0x5BC0 | |------------------- * | | | Beacon 6 | * |0x5DC0 | |------------------- * | | | Beacon 7 | * |0x5FC0 | |------------------- * |0x5FFF | | * -------------------------- * * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry * SHARED_KEY_MODE_BASE: 4-byte * 16-entry */ #define MAC_WCID_BASE … #define PAIRWISE_KEY_TABLE_BASE … #define MAC_IVEIV_TABLE_BASE … #define MAC_WCID_ATTRIBUTE_BASE … #define SHARED_KEY_TABLE_BASE … #define SHARED_KEY_MODE_BASE … #define MAC_WCID_ENTRY(__idx) … #define PAIRWISE_KEY_ENTRY(__idx) … #define MAC_IVEIV_ENTRY(__idx) … #define MAC_WCID_ATTR_ENTRY(__idx) … #define SHARED_KEY_ENTRY(__idx) … #define SHARED_KEY_MODE_ENTRY(__idx) … struct mac_wcid_entry { … } __packed; struct hw_key_entry { … } __packed; struct mac_iveiv_entry { … } __packed; /* * MAC_WCID_ATTRIBUTE: */ #define MAC_WCID_ATTRIBUTE_KEYTAB … #define MAC_WCID_ATTRIBUTE_CIPHER … #define MAC_WCID_ATTRIBUTE_BSS_IDX … #define MAC_WCID_ATTRIBUTE_RX_WIUDF … #define MAC_WCID_ATTRIBUTE_CIPHER_EXT … #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT … #define MAC_WCID_ATTRIBUTE_WAPI_MCBC … #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX … /* * SHARED_KEY_MODE: */ #define SHARED_KEY_MODE_BSS0_KEY0 … #define SHARED_KEY_MODE_BSS0_KEY1 … #define SHARED_KEY_MODE_BSS0_KEY2 … #define SHARED_KEY_MODE_BSS0_KEY3 … #define SHARED_KEY_MODE_BSS1_KEY0 … #define SHARED_KEY_MODE_BSS1_KEY1 … #define SHARED_KEY_MODE_BSS1_KEY2 … #define SHARED_KEY_MODE_BSS1_KEY3 … /* * HOST-MCU communication */ /* * H2M_MAILBOX_CSR: Host-to-MCU Mailbox. * CMD_TOKEN: Command id, 0xff disable status reporting. */ #define H2M_MAILBOX_CSR … #define H2M_MAILBOX_CSR_ARG0 … #define H2M_MAILBOX_CSR_ARG1 … #define H2M_MAILBOX_CSR_CMD_TOKEN … #define H2M_MAILBOX_CSR_OWNER … /* * H2M_MAILBOX_CID: * Free slots contain 0xff. MCU will store command's token to lowest free slot. * If all slots are occupied status will be dropped. */ #define H2M_MAILBOX_CID … #define H2M_MAILBOX_CID_CMD0 … #define H2M_MAILBOX_CID_CMD1 … #define H2M_MAILBOX_CID_CMD2 … #define H2M_MAILBOX_CID_CMD3 … /* * H2M_MAILBOX_STATUS: * Command status will be saved to same slot as command id. */ #define H2M_MAILBOX_STATUS … /* * H2M_INT_SRC: */ #define H2M_INT_SRC … /* * H2M_BBP_AGENT: */ #define H2M_BBP_AGENT … /* * MCU_LEDCS: LED control for MCU Mailbox. */ #define MCU_LEDCS_LED_MODE … #define MCU_LEDCS_POLARITY … /* * HW_CS_CTS_BASE: * Carrier-sense CTS frame base address. * It's where mac stores carrier-sense frame for carrier-sense function. */ #define HW_CS_CTS_BASE … /* * HW_DFS_CTS_BASE: * DFS CTS frame base address. It's where mac stores CTS frame for DFS. */ #define HW_DFS_CTS_BASE … /* * TXRX control registers - base address 0x3000 */ /* * TXRX_CSR1: * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */ #define TXRX_CSR1 … /* * HW_DEBUG_SETTING_BASE: * since NULL frame won't be that long (256 byte) * We steal 16 tail bytes to save debugging settings */ #define HW_DEBUG_SETTING_BASE … #define HW_DEBUG_SETTING_BASE2 … /* * HW_BEACON_BASE * In order to support maximum 8 MBSS and its maximum length * is 512 bytes for each beacon * Three section discontinue memory segments will be used. * 1. The original region for BCN 0~3 * 2. Extract memory from FCE table for BCN 4~5 * 3. Extract memory from Pair-wise key table for BCN 6~7 * It occupied those memory of wcid 238~253 for BCN 6 * and wcid 222~237 for BCN 7 (see Security key table memory * for more info). * * IMPORTANT NOTE: Not sure why legacy driver does this, * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6. */ #define HW_BEACON_BASE0 … #define HW_BEACON_BASE1 … #define HW_BEACON_BASE2 … #define HW_BEACON_BASE3 … #define HW_BEACON_BASE4 … #define HW_BEACON_BASE5 … #define HW_BEACON_BASE6 … #define HW_BEACON_BASE7 … #define HW_BEACON_BASE(__index) … #define BEACON_BASE_TO_OFFSET(_base) … /* * BBP registers. * The wordsize of the BBP is 8 bits. */ /* * BBP 1: TX Antenna & Power Control * POWER_CTRL: * 0 - normal, * 1 - drop tx power by 6dBm, * 2 - drop tx power by 12dBm, * 3 - increase tx power by 6dBm */ #define BBP1_TX_POWER_CTRL … #define BBP1_TX_ANTENNA … /* * BBP 3: RX Antenna */ #define BBP3_RX_ADC … #define BBP3_RX_ANTENNA … #define BBP3_HT40_MINUS … #define BBP3_ADC_MODE_SWITCH … #define BBP3_ADC_INIT_MODE … /* * BBP 4: Bandwidth */ #define BBP4_TX_BF … #define BBP4_BANDWIDTH … #define BBP4_MAC_IF_CTRL … /* BBP27 */ #define BBP27_RX_CHAIN_SEL … /* * BBP 47: Bandwidth */ #define BBP47_TSSI_REPORT_SEL … #define BBP47_TSSI_UPDATE_REQ … #define BBP47_TSSI_TSSI_MODE … #define BBP47_TSSI_ADC6 … /* * BBP 49 */ #define BBP49_UPDATE_FLAG … /* * BBP 105: * - bit0: detect SIG on primary channel only (on 40MHz bandwidth) * - bit1: FEQ (Feed Forward Compensation) for independend streams * - bit2: MLD (Maximum Likehood Detection) for 2 streams (reserved on single * stream) * - bit4: channel estimation updates based on remodulation of * L-SIG and HT-SIG symbols */ #define BBP105_DETECT_SIG_ON_PRIMARY … #define BBP105_FEQ … #define BBP105_MLD … #define BBP105_SIG_REMODULATION … /* * BBP 109 */ #define BBP109_TX0_POWER … #define BBP109_TX1_POWER … /* BBP 110 */ #define BBP110_TX2_POWER … /* * BBP 138: Unknown */ #define BBP138_RX_ADC1 … #define BBP138_RX_ADC2 … #define BBP138_TX_DAC1 … #define BBP138_TX_DAC2 … /* * BBP 152: Rx Ant */ #define BBP152_RX_DEFAULT_ANT … /* * BBP 254: unknown */ #define BBP254_BIT7 … /* * RFCSR registers * The wordsize of the RFCSR is 8 bits. */ /* * RFCSR 1: */ #define RFCSR1_RF_BLOCK_EN … #define RFCSR1_PLL_PD … #define RFCSR1_RX0_PD … #define RFCSR1_TX0_PD … #define RFCSR1_RX1_PD … #define RFCSR1_TX1_PD … #define RFCSR1_RX2_PD … #define RFCSR1_TX2_PD … #define RFCSR1_TX2_EN_MT7620 … /* * RFCSR 2: */ #define RFCSR2_RESCAL_BP … #define RFCSR2_RESCAL_EN … #define RFCSR2_RX2_EN_MT7620 … #define RFCSR2_TX2_EN_MT7620 … /* * RFCSR 3: */ #define RFCSR3_K … /* Bits [7-4] for RF3320 (RT3370/RT3390), on other chipsets reserved */ #define RFCSR3_PA1_BIAS_CCK … #define RFCSR3_PA2_CASCODE_BIAS_CCKK … /* Bits for RF3290/RF5360/RF5362/RF5370/RF5372/RF5390/RF5392 */ #define RFCSR3_VCOCAL_EN … /* Bits for RF3050 */ #define RFCSR3_BIT1 … #define RFCSR3_BIT2 … #define RFCSR3_BIT3 … #define RFCSR3_BIT4 … #define RFCSR3_BIT5 … /* * RFCSR 4: * VCOCAL_EN used by MT7620 */ #define RFCSR4_VCOCAL_EN … /* * FRCSR 5: */ #define RFCSR5_R1 … /* * RFCSR 6: */ #define RFCSR6_R1 … #define RFCSR6_R2 … #define RFCSR6_TXDIV … /* bits for RF3053 */ #define RFCSR6_VCO_IC … /* * RFCSR 7: */ #define RFCSR7_RF_TUNING … #define RFCSR7_BIT1 … #define RFCSR7_BIT2 … #define RFCSR7_BIT3 … #define RFCSR7_BIT4 … #define RFCSR7_BIT5 … #define RFCSR7_BITS67 … /* * RFCSR 9: */ #define RFCSR9_K … #define RFCSR9_N … #define RFCSR9_UNKNOWN … #define RFCSR9_MOD … /* * RFCSR 11: */ #define RFCSR11_R … #define RFCSR11_PLL_MOD … #define RFCSR11_MOD … /* bits for RF3053 */ /* TODO: verify RFCSR11_MOD usage on other chips */ #define RFCSR11_PLL_IDOH … /* * RFCSR 12: */ #define RFCSR12_TX_POWER … #define RFCSR12_DR0 … /* * RFCSR 13: */ #define RFCSR13_TX_POWER … #define RFCSR13_DR0 … #define RFCSR13_RDIV_MT7620 … /* * RFCSR 15: */ #define RFCSR15_TX_LO2_EN … /* * RFCSR 16: */ #define RFCSR16_TXMIXER_GAIN … #define RFCSR16_RF_PLL_FREQ_SEL_MT7620 … #define RFCSR16_SDM_MODE_MT7620 … /* * RFCSR 17: */ #define RFCSR17_TXMIXER_GAIN … #define RFCSR17_TX_LO1_EN … #define RFCSR17_R … #define RFCSR17_CODE … /* RFCSR 18 */ #define RFCSR18_XO_TUNE_BYPASS … /* RFCSR 19 */ #define RFCSR19_K … /* * RFCSR 20: */ #define RFCSR20_RX_LO1_EN … /* * RFCSR 21: */ #define RFCSR21_RX_LO2_EN … #define RFCSR21_BIT1 … #define RFCSR21_BIT8 … /* * RFCSR 22: */ #define RFCSR22_BASEBAND_LOOPBACK … #define RFCSR22_FREQPLAN_D_MT7620 … /* * RFCSR 23: */ #define RFCSR23_FREQ_OFFSET … /* * RFCSR 24: */ #define RFCSR24_TX_AGC_FC … #define RFCSR24_TX_H20M … #define RFCSR24_TX_CALIB … /* * RFCSR 27: */ #define RFCSR27_R1 … #define RFCSR27_R2 … #define RFCSR27_R3 … #define RFCSR27_R4 … /* * RFCSR 28: */ #define RFCSR28_CH11_HT40 … /* * RFCSR 29: */ #define RFCSR29_ADC6_TEST … #define RFCSR29_ADC6_INT_TEST … #define RFCSR29_RSSI_RESET … #define RFCSR29_RSSI_ON … #define RFCSR29_RSSI_RIP_CTRL … #define RFCSR29_RSSI_GAIN … /* * RFCSR 30: */ #define RFCSR30_TX_H20M … #define RFCSR30_RX_H20M … #define RFCSR30_RX_VCM … #define RFCSR30_RF_CALIBRATION … #define RF3322_RFCSR30_TX_H20M … #define RF3322_RFCSR30_RX_H20M … /* * RFCSR 31: */ #define RFCSR31_RX_AGC_FC … #define RFCSR31_RX_H20M … #define RFCSR31_RX_CALIB … /* RFCSR 32 bits for RF3053 */ #define RFCSR32_TX_AGC_FC … /* RFCSR 36 bits for RF3053 */ #define RFCSR36_RF_BS … /* * RFCSR 34: */ #define RFCSR34_TX0_EXT_PA … #define RFCSR34_TX1_EXT_PA … /* * RFCSR 38: */ #define RFCSR38_RX_LO1_EN … /* * RFCSR 39: */ #define RFCSR39_RX_DIV … #define RFCSR39_RX_LO2_EN … /* * RFCSR 41: */ #define RFCSR41_BIT1 … #define RFCSR41_BIT4 … /* * RFCSR 42: */ #define RFCSR42_BIT1 … #define RFCSR42_BIT4 … #define RFCSR42_TX2_EN_MT7620 … /* * RFCSR 49: */ #define RFCSR49_TX … #define RFCSR49_EP … /* bits for RT3593 */ #define RFCSR49_TX_LO1_IC … #define RFCSR49_TX_DIV … /* * RFCSR 50: */ #define RFCSR50_TX … #define RFCSR50_TX0_EXT_PA … #define RFCSR50_TX1_EXT_PA … #define RFCSR50_EP … /* bits for RT3593 */ #define RFCSR50_TX_LO1_EN … #define RFCSR50_TX_LO2_EN … /* RFCSR 51 */ /* bits for RT3593 */ #define RFCSR51_BITS01 … #define RFCSR51_BITS24 … #define RFCSR51_BITS57 … #define RFCSR53_TX_POWER … #define RFCSR53_UNKNOWN … #define RFCSR54_TX_POWER … #define RFCSR54_UNKNOWN … #define RFCSR55_TX_POWER … #define RFCSR55_UNKNOWN … #define RFCSR57_DRV_CC … /* * RF registers */ /* * RF 2 */ #define RF2_ANTENNA_RX2 … #define RF2_ANTENNA_TX1 … #define RF2_ANTENNA_RX1 … /* * RF 3 */ #define RF3_TXPOWER_G … #define RF3_TXPOWER_A_7DBM_BOOST … #define RF3_TXPOWER_A … /* * RF 4 */ #define RF4_TXPOWER_G … #define RF4_TXPOWER_A_7DBM_BOOST … #define RF4_TXPOWER_A … #define RF4_FREQ_OFFSET … #define RF4_HT40 … /* * EEPROM content. * The wordsize of the EEPROM is 16 bits. */ enum rt2800_eeprom_word { … }; /* * EEPROM Version */ #define EEPROM_VERSION_FAE … #define EEPROM_VERSION_VERSION … /* * HW MAC address. */ #define EEPROM_MAC_ADDR_BYTE0 … #define EEPROM_MAC_ADDR_BYTE1 … #define EEPROM_MAC_ADDR_BYTE2 … #define EEPROM_MAC_ADDR_BYTE3 … #define EEPROM_MAC_ADDR_BYTE4 … #define EEPROM_MAC_ADDR_BYTE5 … /* * EEPROM NIC Configuration 0 * RXPATH: 1: 1R, 2: 2R, 3: 3R * TXPATH: 1: 1T, 2: 2T, 3: 3T * RF_TYPE: RFIC type */ #define EEPROM_NIC_CONF0_RXPATH … #define EEPROM_NIC_CONF0_TXPATH … #define EEPROM_NIC_CONF0_RF_TYPE … /* * EEPROM NIC Configuration 1 * HW_RADIO: 0: disable, 1: enable * EXTERNAL_TX_ALC: 0: disable, 1: enable * EXTERNAL_LNA_2G: 0: disable, 1: enable * EXTERNAL_LNA_5G: 0: disable, 1: enable * CARDBUS_ACCEL: 0: enable, 1: disable * BW40M_SB_2G: 0: disable, 1: enable * BW40M_SB_5G: 0: disable, 1: enable * WPS_PBC: 0: disable, 1: enable * BW40M_2G: 0: enable, 1: disable * BW40M_5G: 0: enable, 1: disable * BROADBAND_EXT_LNA: 0: disable, 1: enable * ANT_DIVERSITY: 00: Disable, 01: Diversity, * 10: Main antenna, 11: Aux antenna * INTERNAL_TX_ALC: 0: disable, 1: enable * BT_COEXIST: 0: disable, 1: enable * DAC_TEST: 0: disable, 1: enable * EXTERNAL_TX0_PA: 0: disable, 1: enable (only on RT3352) * EXTERNAL_TX1_PA: 0: disable, 1: enable (only on RT3352) */ #define EEPROM_NIC_CONF1_HW_RADIO … #define EEPROM_NIC_CONF1_EXTERNAL_TX_ALC … #define EEPROM_NIC_CONF1_EXTERNAL_LNA_2G … #define EEPROM_NIC_CONF1_EXTERNAL_LNA_5G … #define EEPROM_NIC_CONF1_CARDBUS_ACCEL … #define EEPROM_NIC_CONF1_BW40M_SB_2G … #define EEPROM_NIC_CONF1_BW40M_SB_5G … #define EEPROM_NIC_CONF1_WPS_PBC … #define EEPROM_NIC_CONF1_BW40M_2G … #define EEPROM_NIC_CONF1_BW40M_5G … #define EEPROM_NIC_CONF1_BROADBAND_EXT_LNA … #define EEPROM_NIC_CONF1_ANT_DIVERSITY … #define EEPROM_NIC_CONF1_INTERNAL_TX_ALC … #define EEPROM_NIC_CONF1_BT_COEXIST … #define EEPROM_NIC_CONF1_DAC_TEST … #define EEPROM_NIC_CONF1_EXTERNAL_TX0_PA_3352 … #define EEPROM_NIC_CONF1_EXTERNAL_TX1_PA_3352 … /* * EEPROM frequency */ #define EEPROM_FREQ_OFFSET … #define EEPROM_FREQ_LED_MODE … #define EEPROM_FREQ_LED_POLARITY … /* * EEPROM LED * POLARITY_RDY_G: Polarity RDY_G setting. * POLARITY_RDY_A: Polarity RDY_A setting. * POLARITY_ACT: Polarity ACT setting. * POLARITY_GPIO_0: Polarity GPIO0 setting. * POLARITY_GPIO_1: Polarity GPIO1 setting. * POLARITY_GPIO_2: Polarity GPIO2 setting. * POLARITY_GPIO_3: Polarity GPIO3 setting. * POLARITY_GPIO_4: Polarity GPIO4 setting. * LED_MODE: Led mode. */ #define EEPROM_LED_POLARITY_RDY_BG … #define EEPROM_LED_POLARITY_RDY_A … #define EEPROM_LED_POLARITY_ACT … #define EEPROM_LED_POLARITY_GPIO_0 … #define EEPROM_LED_POLARITY_GPIO_1 … #define EEPROM_LED_POLARITY_GPIO_2 … #define EEPROM_LED_POLARITY_GPIO_3 … #define EEPROM_LED_POLARITY_GPIO_4 … #define EEPROM_LED_LED_MODE … /* * EEPROM NIC Configuration 2 * RX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream * TX_STREAM: 0: Reserved, 1: 1 Stream, 2: 2 Stream * CRYSTAL: 00: Reserved, 01: One crystal, 10: Two crystal, 11: Reserved */ #define EEPROM_NIC_CONF2_RX_STREAM … #define EEPROM_NIC_CONF2_TX_STREAM … #define EEPROM_NIC_CONF2_CRYSTAL … #define EEPROM_NIC_CONF2_EXTERNAL_PA … /* * EEPROM LNA */ #define EEPROM_LNA_BG … #define EEPROM_LNA_A0 … /* * EEPROM RSSI BG offset */ #define EEPROM_RSSI_BG_OFFSET0 … #define EEPROM_RSSI_BG_OFFSET1 … /* * EEPROM RSSI BG2 offset */ #define EEPROM_RSSI_BG2_OFFSET2 … #define EEPROM_RSSI_BG2_LNA_A1 … /* * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2). */ #define EEPROM_TXMIXER_GAIN_BG_VAL … /* * EEPROM RSSI A offset */ #define EEPROM_RSSI_A_OFFSET0 … #define EEPROM_RSSI_A_OFFSET1 … /* * EEPROM RSSI A2 offset */ #define EEPROM_RSSI_A2_OFFSET2 … #define EEPROM_RSSI_A2_LNA_A2 … /* * EEPROM TXMIXER GAIN A offset (note overlaps with EEPROM RSSI A2). */ #define EEPROM_TXMIXER_GAIN_A_VAL … /* * EEPROM EIRP Maximum TX power values(unit: dbm) */ #define EEPROM_EIRP_MAX_TX_POWER_2GHZ … #define EEPROM_EIRP_MAX_TX_POWER_5GHZ … /* * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power. * This is delta in 40MHZ. * VALUE: Tx Power dalta value, MAX=4(unit: dbm) * TYPE: 1: Plus the delta value, 0: minus the delta value * ENABLE: enable tx power compensation for 40BW */ #define EEPROM_TXPOWER_DELTA_VALUE_2G … #define EEPROM_TXPOWER_DELTA_TYPE_2G … #define EEPROM_TXPOWER_DELTA_ENABLE_2G … #define EEPROM_TXPOWER_DELTA_VALUE_5G … #define EEPROM_TXPOWER_DELTA_TYPE_5G … #define EEPROM_TXPOWER_DELTA_ENABLE_5G … /* * EEPROM TXPOWER 802.11BG */ #define EEPROM_TXPOWER_BG_SIZE … #define EEPROM_TXPOWER_BG_1 … #define EEPROM_TXPOWER_BG_2 … /* * EEPROM temperature compensation boundaries 802.11BG * MINUS4: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -4) * MINUS3: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -3) */ #define EEPROM_TSSI_BOUND_BG1_MINUS4 … #define EEPROM_TSSI_BOUND_BG1_MINUS3 … /* * EEPROM temperature compensation boundaries 802.11BG * MINUS2: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -2) * MINUS1: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -1) */ #define EEPROM_TSSI_BOUND_BG2_MINUS2 … #define EEPROM_TSSI_BOUND_BG2_MINUS1 … /* * EEPROM temperature compensation boundaries 802.11BG * REF: Reference TSSI value, no tx power changes needed * PLUS1: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 1) */ #define EEPROM_TSSI_BOUND_BG3_REF … #define EEPROM_TSSI_BOUND_BG3_PLUS1 … /* * EEPROM temperature compensation boundaries 802.11BG * PLUS2: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 2) * PLUS3: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 3) */ #define EEPROM_TSSI_BOUND_BG4_PLUS2 … #define EEPROM_TSSI_BOUND_BG4_PLUS3 … /* * EEPROM temperature compensation boundaries 802.11BG * PLUS4: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 4) * AGC_STEP: Temperature compensation step. */ #define EEPROM_TSSI_BOUND_BG5_PLUS4 … #define EEPROM_TSSI_BOUND_BG5_AGC_STEP … /* * EEPROM TXPOWER 802.11A */ #define EEPROM_TXPOWER_A_SIZE … #define EEPROM_TXPOWER_A_1 … #define EEPROM_TXPOWER_A_2 … /* EEPROM_TXPOWER_{A,G} fields for RT3593 */ #define EEPROM_TXPOWER_ALC … #define EEPROM_TXPOWER_FINE_CTRL … /* * EEPROM temperature compensation boundaries 802.11A * MINUS4: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -4) * MINUS3: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -3) */ #define EEPROM_TSSI_BOUND_A1_MINUS4 … #define EEPROM_TSSI_BOUND_A1_MINUS3 … /* * EEPROM temperature compensation boundaries 802.11A * MINUS2: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -2) * MINUS1: If the actual TSSI is below this boundary, tx power needs to be * reduced by (agc_step * -1) */ #define EEPROM_TSSI_BOUND_A2_MINUS2 … #define EEPROM_TSSI_BOUND_A2_MINUS1 … /* * EEPROM temperature compensation boundaries 802.11A * REF: Reference TSSI value, no tx power changes needed * PLUS1: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 1) */ #define EEPROM_TSSI_BOUND_A3_REF … #define EEPROM_TSSI_BOUND_A3_PLUS1 … /* * EEPROM temperature compensation boundaries 802.11A * PLUS2: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 2) * PLUS3: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 3) */ #define EEPROM_TSSI_BOUND_A4_PLUS2 … #define EEPROM_TSSI_BOUND_A4_PLUS3 … /* * EEPROM temperature compensation boundaries 802.11A * PLUS4: If the actual TSSI is above this boundary, tx power needs to be * increased by (agc_step * 4) * AGC_STEP: Temperature compensation step. */ #define EEPROM_TSSI_BOUND_A5_PLUS4 … #define EEPROM_TSSI_BOUND_A5_AGC_STEP … /* * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode */ #define EEPROM_TXPOWER_BYRATE_SIZE … #define EEPROM_TXPOWER_BYRATE_RATE0 … #define EEPROM_TXPOWER_BYRATE_RATE1 … #define EEPROM_TXPOWER_BYRATE_RATE2 … #define EEPROM_TXPOWER_BYRATE_RATE3 … /* * EEPROM BBP. */ #define EEPROM_BBP_SIZE … #define EEPROM_BBP_VALUE … #define EEPROM_BBP_REG_ID … /* EEPROM_EXT_LNA2 */ #define EEPROM_EXT_LNA2_A1 … #define EEPROM_EXT_LNA2_A2 … /* * EEPROM IQ Calibration, unlike other entries those are byte addresses. */ #define EEPROM_IQ_GAIN_CAL_TX0_2G … #define EEPROM_IQ_PHASE_CAL_TX0_2G … #define EEPROM_IQ_GROUPDELAY_CAL_TX0_2G … #define EEPROM_IQ_GAIN_CAL_TX1_2G … #define EEPROM_IQ_PHASE_CAL_TX1_2G … #define EEPROM_IQ_GROUPDELAY_CAL_TX1_2G … #define EEPROM_IQ_GAIN_CAL_RX0_2G … #define EEPROM_IQ_PHASE_CAL_RX0_2G … #define EEPROM_IQ_GROUPDELAY_CAL_RX0_2G … #define EEPROM_IQ_GAIN_CAL_RX1_2G … #define EEPROM_IQ_PHASE_CAL_RX1_2G … #define EEPROM_IQ_GROUPDELAY_CAL_RX1_2G … #define EEPROM_RF_IQ_COMPENSATION_CONTROL … #define EEPROM_RF_IQ_IMBALANCE_COMPENSATION_CONTROL … #define EEPROM_IQ_GAIN_CAL_TX0_CH36_TO_CH64_5G … #define EEPROM_IQ_PHASE_CAL_TX0_CH36_TO_CH64_5G … #define EEPROM_IQ_GAIN_CAL_TX0_CH100_TO_CH138_5G … #define EEPROM_IQ_PHASE_CAL_TX0_CH100_TO_CH138_5G … #define EEPROM_IQ_GAIN_CAL_TX0_CH140_TO_CH165_5G … #define EEPROM_IQ_PHASE_CAL_TX0_CH140_TO_CH165_5G … #define EEPROM_IQ_GAIN_CAL_TX1_CH36_TO_CH64_5G … #define EEPROM_IQ_PHASE_CAL_TX1_CH36_TO_CH64_5G … #define EEPROM_IQ_GAIN_CAL_TX1_CH100_TO_CH138_5G … #define EEPROM_IQ_PHASE_CAL_TX1_CH100_TO_CH138_5G … #define EEPROM_IQ_GAIN_CAL_TX1_CH140_TO_CH165_5G … #define EEPROM_IQ_PHASE_CAL_TX1_CH140_TO_CH165_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH36_TO_CH64_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH36_TO_CH64_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH100_TO_CH138_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH100_TO_CH138_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX0_CH140_TO_CH165_5G … #define EEPROM_IQ_GROUPDELAY_CAL_TX1_CH140_TO_CH165_5G … #define EEPROM_IQ_GAIN_CAL_RX0_CH36_TO_CH64_5G … #define EEPROM_IQ_PHASE_CAL_RX0_CH36_TO_CH64_5G … #define EEPROM_IQ_GAIN_CAL_RX0_CH100_TO_CH138_5G … #define EEPROM_IQ_PHASE_CAL_RX0_CH100_TO_CH138_5G … #define EEPROM_IQ_GAIN_CAL_RX0_CH140_TO_CH165_5G … #define EEPROM_IQ_PHASE_CAL_RX0_CH140_TO_CH165_5G … #define EEPROM_IQ_GAIN_CAL_RX1_CH36_TO_CH64_5G … #define EEPROM_IQ_PHASE_CAL_RX1_CH36_TO_CH64_5G … #define EEPROM_IQ_GAIN_CAL_RX1_CH100_TO_CH138_5G … #define EEPROM_IQ_PHASE_CAL_RX1_CH100_TO_CH138_5G … #define EEPROM_IQ_GAIN_CAL_RX1_CH140_TO_CH165_5G … #define EEPROM_IQ_PHASE_CAL_RX1_CH140_TO_CH165_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH36_TO_CH64_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH36_TO_CH64_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH100_TO_CH138_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH100_TO_CH138_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX0_CH140_TO_CH165_5G … #define EEPROM_IQ_GROUPDELAY_CAL_RX1_CH140_TO_CH165_5G … /* * MCU mailbox commands. * MCU_SLEEP - go to power-save mode. * arg1: 1: save as much power as possible, 0: save less power. * status: 1: success, 2: already asleep, * 3: maybe MAC is busy so can't finish this task. * MCU_RADIO_OFF * arg0: 0: do power-saving, NOT turn off radio. */ #define MCU_SLEEP … #define MCU_WAKEUP … #define MCU_RADIO_OFF … #define MCU_CURRENT … #define MCU_LED … #define MCU_LED_STRENGTH … #define MCU_LED_AG_CONF … #define MCU_LED_ACT_CONF … #define MCU_LED_LED_POLARITY … #define MCU_RADAR … #define MCU_BOOT_SIGNAL … #define MCU_ANT_SELECT … #define MCU_FREQ_OFFSET … #define MCU_BBP_SIGNAL … #define MCU_POWER_SAVE … #define MCU_BAND_SELECT … /* * MCU mailbox tokens */ #define TOKEN_SLEEP … #define TOKEN_RADIO_OFF … #define TOKEN_WAKEUP … /* * DMA descriptor defines. */ #define TXWI_DESC_SIZE_4WORDS … #define TXWI_DESC_SIZE_5WORDS … #define RXWI_DESC_SIZE_4WORDS … #define RXWI_DESC_SIZE_5WORDS … #define RXWI_DESC_SIZE_6WORDS … /* * TX WI structure */ /* * Word0 * FRAG: 1 To inform TKIP engine this is a fragment. * MIMO_PS: The remote peer is in dynamic MIMO-PS mode * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will * duplicate the frame to both channels). * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will * aggregate consecutive frames with the same RA and QoS TID. If * a frame A with the same RA and QoS TID but AMPDU=0 is queued * directly after a frame B with AMPDU=1, frame A might still * get aggregated into the AMPDU started by frame B. So, setting * AMPDU to 0 does _not_ necessarily mean the frame is sent as * MPDU, it can still end up in an AMPDU if the previous frame * was tagged as AMPDU. */ #define TXWI_W0_FRAG … #define TXWI_W0_MIMO_PS … #define TXWI_W0_CF_ACK … #define TXWI_W0_TS … #define TXWI_W0_AMPDU … #define TXWI_W0_MPDU_DENSITY … #define TXWI_W0_TX_OP … #define TXWI_W0_MCS … #define TXWI_W0_BW … #define TXWI_W0_SHORT_GI … #define TXWI_W0_STBC … #define TXWI_W0_IFS … #define TXWI_W0_PHYMODE … /* * Word1 * ACK: 0: No Ack needed, 1: Ack needed * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number * BW_WIN_SIZE: BA windows size of the recipient * WIRELESS_CLI_ID: Client ID for WCID table access * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame * PACKETID: Will be latched into the TX_STA_FIFO register once the according * frame was processed. If multiple frames are aggregated together * (AMPDU==1) the reported tx status will always contain the packet * id of the first frame. 0: Don't report tx status for this frame. * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3) * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3) * This identification number is calculated by ((idx % 3) + 1). * The (+1) is required to prevent PACKETID to become 0. */ #define TXWI_W1_ACK … #define TXWI_W1_NSEQ … #define TXWI_W1_BW_WIN_SIZE … #define TXWI_W1_WIRELESS_CLI_ID … #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT … #define TXWI_W1_PACKETID … #define TXWI_W1_PACKETID_QUEUE … #define TXWI_W1_PACKETID_ENTRY … /* * Word2 */ #define TXWI_W2_IV … /* * Word3 */ #define TXWI_W3_EIV … /* * RX WI structure */ /* * Word0 */ #define RXWI_W0_WIRELESS_CLI_ID … #define RXWI_W0_KEY_INDEX … #define RXWI_W0_BSSID … #define RXWI_W0_UDF … #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT … #define RXWI_W0_TID … /* * Word1 */ #define RXWI_W1_FRAG … #define RXWI_W1_SEQUENCE … #define RXWI_W1_MCS … #define RXWI_W1_BW … #define RXWI_W1_SHORT_GI … #define RXWI_W1_STBC … #define RXWI_W1_PHYMODE … /* * Word2 */ #define RXWI_W2_RSSI0 … #define RXWI_W2_RSSI1 … #define RXWI_W2_RSSI2 … /* * Word3 */ #define RXWI_W3_SNR0 … #define RXWI_W3_SNR1 … /* * Macros for converting txpower from EEPROM to mac80211 value * and from mac80211 value to register value. */ #define MIN_G_TXPOWER … #define MIN_A_TXPOWER … #define MAX_G_TXPOWER … #define MAX_A_TXPOWER … #define DEFAULT_TXPOWER … #define MIN_A_TXPOWER_3593 … #define MAX_A_TXPOWER_3593 … #define TXPOWER_G_FROM_DEV(__txpower) … #define TXPOWER_A_FROM_DEV(__txpower) … /* * Board's maximun TX power limitation */ #define EIRP_MAX_TX_POWER_LIMIT … /* * Number of TBTT intervals after which we have to adjust * the hw beacon timer. */ #define BCN_TBTT_OFFSET … /* Watchdog type mask */ #define RT2800_WATCHDOG_HANG … #define RT2800_WATCHDOG_DMA_BUSY … #endif /* RT2800_H */
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