/* SPDX-License-Identifier: GPL-2.0-or-later */ /* Copyright (C) 2004 - 2009 Ivo van Doorn <[email protected]> <http://rt2x00.serialmonkey.com> */ /* Module: rt2500usb Abstract: Data structures and registers for the rt2500usb module. Supported chipsets: RT2570. */ #ifndef RT2500USB_H #define RT2500USB_H /* * RF chip defines. */ #define RF2522 … #define RF2523 … #define RF2524 … #define RF2525 … #define RF2525E … #define RF5222 … /* * RT2570 version */ #define RT2570_VERSION_B … #define RT2570_VERSION_C … #define RT2570_VERSION_D … /* * Signal information. * Default offset is required for RSSI <-> dBm conversion. */ #define DEFAULT_RSSI_OFFSET … /* * Register layout information. */ #define CSR_REG_BASE … #define CSR_REG_SIZE … #define EEPROM_BASE … #define EEPROM_SIZE … #define BBP_BASE … #define BBP_SIZE … #define RF_BASE … #define RF_SIZE … /* * Number of TX queues. */ #define NUM_TX_QUEUES … /* * Control/Status Registers(CSR). * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * MAC_CSR0: ASIC revision number. */ #define MAC_CSR0 … /* * MAC_CSR1: System control. * SOFT_RESET: Software reset, 1: reset, 0: normal. * BBP_RESET: Hardware reset, 1: reset, 0, release. * HOST_READY: Host ready after initialization. */ #define MAC_CSR1 … #define MAC_CSR1_SOFT_RESET … #define MAC_CSR1_BBP_RESET … #define MAC_CSR1_HOST_READY … /* * MAC_CSR2: STA MAC register 0. */ #define MAC_CSR2 … #define MAC_CSR2_BYTE0 … #define MAC_CSR2_BYTE1 … /* * MAC_CSR3: STA MAC register 1. */ #define MAC_CSR3 … #define MAC_CSR3_BYTE2 … #define MAC_CSR3_BYTE3 … /* * MAC_CSR4: STA MAC register 2. */ #define MAC_CSR4 … #define MAC_CSR4_BYTE4 … #define MAC_CSR4_BYTE5 … /* * MAC_CSR5: BSSID register 0. */ #define MAC_CSR5 … #define MAC_CSR5_BYTE0 … #define MAC_CSR5_BYTE1 … /* * MAC_CSR6: BSSID register 1. */ #define MAC_CSR6 … #define MAC_CSR6_BYTE2 … #define MAC_CSR6_BYTE3 … /* * MAC_CSR7: BSSID register 2. */ #define MAC_CSR7 … #define MAC_CSR7_BYTE4 … #define MAC_CSR7_BYTE5 … /* * MAC_CSR8: Max frame length. */ #define MAC_CSR8 … #define MAC_CSR8_MAX_FRAME_UNIT … /* * Misc MAC_CSR registers. * MAC_CSR9: Timer control. * MAC_CSR10: Slot time. * MAC_CSR11: SIFS. * MAC_CSR12: EIFS. * MAC_CSR13: Power mode0. * MAC_CSR14: Power mode1. * MAC_CSR15: Power saving transition0 * MAC_CSR16: Power saving transition1 */ #define MAC_CSR9 … #define MAC_CSR10 … #define MAC_CSR11 … #define MAC_CSR12 … #define MAC_CSR13 … #define MAC_CSR14 … #define MAC_CSR15 … #define MAC_CSR16 … /* * MAC_CSR17: Manual power control / status register. * Allowed state: 0 deep_sleep, 1: sleep, 2: standby, 3: awake. * SET_STATE: Set state. Write 1 to trigger, self cleared. * BBP_DESIRE_STATE: BBP desired state. * RF_DESIRE_STATE: RF desired state. * BBP_CURRENT_STATE: BBP current state. * RF_CURRENT_STATE: RF current state. * PUT_TO_SLEEP: Put to sleep. Write 1 to trigger, self cleared. */ #define MAC_CSR17 … #define MAC_CSR17_SET_STATE … #define MAC_CSR17_BBP_DESIRE_STATE … #define MAC_CSR17_RF_DESIRE_STATE … #define MAC_CSR17_BBP_CURR_STATE … #define MAC_CSR17_RF_CURR_STATE … #define MAC_CSR17_PUT_TO_SLEEP … /* * MAC_CSR18: Wakeup timer register. * DELAY_AFTER_BEACON: Delay after Tbcn expired in units of 1/16 TU. * BEACONS_BEFORE_WAKEUP: Number of beacon before wakeup. * AUTO_WAKE: Enable auto wakeup / sleep mechanism. */ #define MAC_CSR18 … #define MAC_CSR18_DELAY_AFTER_BEACON … #define MAC_CSR18_BEACONS_BEFORE_WAKEUP … #define MAC_CSR18_AUTO_WAKE … /* * MAC_CSR19: GPIO control register. * MAC_CSR19_VALx: GPIO value * MAC_CSR19_DIRx: GPIO direction: 0 = input; 1 = output */ #define MAC_CSR19 … #define MAC_CSR19_VAL0 … #define MAC_CSR19_VAL1 … #define MAC_CSR19_VAL2 … #define MAC_CSR19_VAL3 … #define MAC_CSR19_VAL4 … #define MAC_CSR19_VAL5 … #define MAC_CSR19_VAL6 … #define MAC_CSR19_VAL7 … #define MAC_CSR19_DIR0 … #define MAC_CSR19_DIR1 … #define MAC_CSR19_DIR2 … #define MAC_CSR19_DIR3 … #define MAC_CSR19_DIR4 … #define MAC_CSR19_DIR5 … #define MAC_CSR19_DIR6 … #define MAC_CSR19_DIR7 … /* * MAC_CSR20: LED control register. * ACTIVITY: 0: idle, 1: active. * LINK: 0: linkoff, 1: linkup. * ACTIVITY_POLARITY: 0: active low, 1: active high. */ #define MAC_CSR20 … #define MAC_CSR20_ACTIVITY … #define MAC_CSR20_LINK … #define MAC_CSR20_ACTIVITY_POLARITY … /* * MAC_CSR21: LED control register. * ON_PERIOD: On period, default 70ms. * OFF_PERIOD: Off period, default 30ms. */ #define MAC_CSR21 … #define MAC_CSR21_ON_PERIOD … #define MAC_CSR21_OFF_PERIOD … /* * MAC_CSR22: Collision window control register. */ #define MAC_CSR22 … /* * Transmit related CSRs. * Some values are set in TU, whereas 1 TU == 1024 us. */ /* * TXRX_CSR0: Security control register. */ #define TXRX_CSR0 … #define TXRX_CSR0_ALGORITHM … #define TXRX_CSR0_IV_OFFSET … #define TXRX_CSR0_KEY_ID … /* * TXRX_CSR1: TX configuration. * ACK_TIMEOUT: ACK Timeout in unit of 1-us. * TSF_OFFSET: TSF offset in MAC header. * AUTO_SEQUENCE: Let ASIC control frame sequence number. */ #define TXRX_CSR1 … #define TXRX_CSR1_ACK_TIMEOUT … #define TXRX_CSR1_TSF_OFFSET … #define TXRX_CSR1_AUTO_SEQUENCE … /* * TXRX_CSR2: RX control. * DISABLE_RX: Disable rx engine. * DROP_CRC: Drop crc error. * DROP_PHYSICAL: Drop physical error. * DROP_CONTROL: Drop control frame. * DROP_NOT_TO_ME: Drop not to me unicast frame. * DROP_TODS: Drop frame tods bit is true. * DROP_VERSION_ERROR: Drop version error frame. * DROP_MCAST: Drop multicast frames. * DROP_BCAST: Drop broadcast frames. */ #define TXRX_CSR2 … #define TXRX_CSR2_DISABLE_RX … #define TXRX_CSR2_DROP_CRC … #define TXRX_CSR2_DROP_PHYSICAL … #define TXRX_CSR2_DROP_CONTROL … #define TXRX_CSR2_DROP_NOT_TO_ME … #define TXRX_CSR2_DROP_TODS … #define TXRX_CSR2_DROP_VERSION_ERROR … #define TXRX_CSR2_DROP_MULTICAST … #define TXRX_CSR2_DROP_BROADCAST … /* * RX BBP ID registers * TXRX_CSR3: CCK RX BBP ID. * TXRX_CSR4: OFDM RX BBP ID. */ #define TXRX_CSR3 … #define TXRX_CSR4 … /* * TXRX_CSR5: CCK TX BBP ID0. */ #define TXRX_CSR5 … #define TXRX_CSR5_BBP_ID0 … #define TXRX_CSR5_BBP_ID0_VALID … #define TXRX_CSR5_BBP_ID1 … #define TXRX_CSR5_BBP_ID1_VALID … /* * TXRX_CSR6: CCK TX BBP ID1. */ #define TXRX_CSR6 … #define TXRX_CSR6_BBP_ID0 … #define TXRX_CSR6_BBP_ID0_VALID … #define TXRX_CSR6_BBP_ID1 … #define TXRX_CSR6_BBP_ID1_VALID … /* * TXRX_CSR7: OFDM TX BBP ID0. */ #define TXRX_CSR7 … #define TXRX_CSR7_BBP_ID0 … #define TXRX_CSR7_BBP_ID0_VALID … #define TXRX_CSR7_BBP_ID1 … #define TXRX_CSR7_BBP_ID1_VALID … /* * TXRX_CSR8: OFDM TX BBP ID1. */ #define TXRX_CSR8 … #define TXRX_CSR8_BBP_ID0 … #define TXRX_CSR8_BBP_ID0_VALID … #define TXRX_CSR8_BBP_ID1 … #define TXRX_CSR8_BBP_ID1_VALID … /* * TXRX_CSR9: TX ACK time-out. */ #define TXRX_CSR9 … /* * TXRX_CSR10: Auto responder control. */ #define TXRX_CSR10 … #define TXRX_CSR10_AUTORESPOND_PREAMBLE … /* * TXRX_CSR11: Auto responder basic rate. */ #define TXRX_CSR11 … /* * ACK/CTS time registers. */ #define TXRX_CSR12 … #define TXRX_CSR13 … #define TXRX_CSR14 … #define TXRX_CSR15 … #define TXRX_CSR16 … #define TXRX_CSR17 … /* * TXRX_CSR18: Synchronization control register. */ #define TXRX_CSR18 … #define TXRX_CSR18_OFFSET … #define TXRX_CSR18_INTERVAL … /* * TXRX_CSR19: Synchronization control register. * TSF_COUNT: Enable TSF auto counting. * TSF_SYNC: Tsf sync, 0: disable, 1: infra, 2: ad-hoc/master mode. * TBCN: Enable Tbcn with reload value. * BEACON_GEN: Enable beacon generator. */ #define TXRX_CSR19 … #define TXRX_CSR19_TSF_COUNT … #define TXRX_CSR19_TSF_SYNC … #define TXRX_CSR19_TBCN … #define TXRX_CSR19_BEACON_GEN … /* * TXRX_CSR20: Tx BEACON offset time control register. * OFFSET: In units of usec. * BCN_EXPECT_WINDOW: Default: 2^CWmin */ #define TXRX_CSR20 … #define TXRX_CSR20_OFFSET … #define TXRX_CSR20_BCN_EXPECT_WINDOW … /* * TXRX_CSR21 */ #define TXRX_CSR21 … /* * Encryption related CSRs. * */ /* * SEC_CSR0: Shared key 0, word 0 * SEC_CSR1: Shared key 0, word 1 * SEC_CSR2: Shared key 0, word 2 * SEC_CSR3: Shared key 0, word 3 * SEC_CSR4: Shared key 0, word 4 * SEC_CSR5: Shared key 0, word 5 * SEC_CSR6: Shared key 0, word 6 * SEC_CSR7: Shared key 0, word 7 */ #define SEC_CSR0 … #define SEC_CSR1 … #define SEC_CSR2 … #define SEC_CSR3 … #define SEC_CSR4 … #define SEC_CSR5 … #define SEC_CSR6 … #define SEC_CSR7 … /* * SEC_CSR8: Shared key 1, word 0 * SEC_CSR9: Shared key 1, word 1 * SEC_CSR10: Shared key 1, word 2 * SEC_CSR11: Shared key 1, word 3 * SEC_CSR12: Shared key 1, word 4 * SEC_CSR13: Shared key 1, word 5 * SEC_CSR14: Shared key 1, word 6 * SEC_CSR15: Shared key 1, word 7 */ #define SEC_CSR8 … #define SEC_CSR9 … #define SEC_CSR10 … #define SEC_CSR11 … #define SEC_CSR12 … #define SEC_CSR13 … #define SEC_CSR14 … #define SEC_CSR15 … /* * SEC_CSR16: Shared key 2, word 0 * SEC_CSR17: Shared key 2, word 1 * SEC_CSR18: Shared key 2, word 2 * SEC_CSR19: Shared key 2, word 3 * SEC_CSR20: Shared key 2, word 4 * SEC_CSR21: Shared key 2, word 5 * SEC_CSR22: Shared key 2, word 6 * SEC_CSR23: Shared key 2, word 7 */ #define SEC_CSR16 … #define SEC_CSR17 … #define SEC_CSR18 … #define SEC_CSR19 … #define SEC_CSR20 … #define SEC_CSR21 … #define SEC_CSR22 … #define SEC_CSR23 … /* * SEC_CSR24: Shared key 3, word 0 * SEC_CSR25: Shared key 3, word 1 * SEC_CSR26: Shared key 3, word 2 * SEC_CSR27: Shared key 3, word 3 * SEC_CSR28: Shared key 3, word 4 * SEC_CSR29: Shared key 3, word 5 * SEC_CSR30: Shared key 3, word 6 * SEC_CSR31: Shared key 3, word 7 */ #define SEC_CSR24 … #define SEC_CSR25 … #define SEC_CSR26 … #define SEC_CSR27 … #define SEC_CSR28 … #define SEC_CSR29 … #define SEC_CSR30 … #define SEC_CSR31 … #define KEY_ENTRY(__idx) … /* * PHY control registers. */ /* * PHY_CSR0: RF switching timing control. */ #define PHY_CSR0 … /* * PHY_CSR1: TX PA configuration. */ #define PHY_CSR1 … /* * MAC configuration registers. */ /* * PHY_CSR2: TX MAC configuration. * NOTE: Both register fields are complete dummy, * documentation and legacy drivers are unclear un * what this register means or what fields exists. */ #define PHY_CSR2 … #define PHY_CSR2_LNA … #define PHY_CSR2_LNA_MODE … /* * PHY_CSR3: RX MAC configuration. */ #define PHY_CSR3 … /* * PHY_CSR4: Interface configuration. */ #define PHY_CSR4 … #define PHY_CSR4_LOW_RF_LE … /* * BBP pre-TX registers. * PHY_CSR5: BBP pre-TX CCK. */ #define PHY_CSR5 … #define PHY_CSR5_CCK … #define PHY_CSR5_CCK_FLIP … /* * BBP pre-TX registers. * PHY_CSR6: BBP pre-TX OFDM. */ #define PHY_CSR6 … #define PHY_CSR6_OFDM … #define PHY_CSR6_OFDM_FLIP … /* * PHY_CSR7: BBP access register 0. * BBP_DATA: BBP data. * BBP_REG_ID: BBP register ID. * BBP_READ_CONTROL: 0: write, 1: read. */ #define PHY_CSR7 … #define PHY_CSR7_DATA … #define PHY_CSR7_REG_ID … #define PHY_CSR7_READ_CONTROL … /* * PHY_CSR8: BBP access register 1. * BBP_BUSY: ASIC is busy execute BBP programming. */ #define PHY_CSR8 … #define PHY_CSR8_BUSY … /* * PHY_CSR9: RF access register. * RF_VALUE: Register value + id to program into rf/if. */ #define PHY_CSR9 … #define PHY_CSR9_RF_VALUE … /* * PHY_CSR10: RF access register. * RF_VALUE: Register value + id to program into rf/if. * RF_NUMBER_OF_BITS: Number of bits used in value (i:20, rfmd:22). * RF_IF_SELECT: Chip to program: 0: rf, 1: if. * RF_PLL_LD: Rf pll_ld status. * RF_BUSY: 1: asic is busy execute rf programming. */ #define PHY_CSR10 … #define PHY_CSR10_RF_VALUE … #define PHY_CSR10_RF_NUMBER_OF_BITS … #define PHY_CSR10_RF_IF_SELECT … #define PHY_CSR10_RF_PLL_LD … #define PHY_CSR10_RF_BUSY … /* * STA_CSR0: FCS error count. * FCS_ERROR: FCS error count, cleared when read. */ #define STA_CSR0 … #define STA_CSR0_FCS_ERROR … /* * STA_CSR1: PLCP error count. */ #define STA_CSR1 … /* * STA_CSR2: LONG error count. */ #define STA_CSR2 … /* * STA_CSR3: CCA false alarm. * FALSE_CCA_ERROR: False CCA error count, cleared when read. */ #define STA_CSR3 … #define STA_CSR3_FALSE_CCA_ERROR … /* * STA_CSR4: RX FIFO overflow. */ #define STA_CSR4 … /* * STA_CSR5: Beacon sent counter. */ #define STA_CSR5 … /* * Statistics registers */ #define STA_CSR6 … #define STA_CSR7 … #define STA_CSR8 … #define STA_CSR9 … #define STA_CSR10 … /* * BBP registers. * The wordsize of the BBP is 8 bits. */ /* * R2: TX antenna control */ #define BBP_R2_TX_ANTENNA … #define BBP_R2_TX_IQ_FLIP … /* * R14: RX antenna control */ #define BBP_R14_RX_ANTENNA … #define BBP_R14_RX_IQ_FLIP … /* * RF registers. */ /* * RF 1 */ #define RF1_TUNER … /* * RF 3 */ #define RF3_TUNER … #define RF3_TXPOWER … /* * EEPROM contents. */ /* * HW MAC address. */ #define EEPROM_MAC_ADDR_0 … #define EEPROM_MAC_ADDR_BYTE0 … #define EEPROM_MAC_ADDR_BYTE1 … #define EEPROM_MAC_ADDR1 … #define EEPROM_MAC_ADDR_BYTE2 … #define EEPROM_MAC_ADDR_BYTE3 … #define EEPROM_MAC_ADDR_2 … #define EEPROM_MAC_ADDR_BYTE4 … #define EEPROM_MAC_ADDR_BYTE5 … /* * EEPROM antenna. * ANTENNA_NUM: Number of antenna's. * TX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * RX_DEFAULT: Default antenna 0: diversity, 1: A, 2: B. * LED_MODE: 0: default, 1: TX/RX activity, 2: Single (ignore link), 3: rsvd. * DYN_TXAGC: Dynamic TX AGC control. * HARDWARE_RADIO: 1: Hardware controlled radio. Read GPIO0. * RF_TYPE: Rf_type of this adapter. */ #define EEPROM_ANTENNA … #define EEPROM_ANTENNA_NUM … #define EEPROM_ANTENNA_TX_DEFAULT … #define EEPROM_ANTENNA_RX_DEFAULT … #define EEPROM_ANTENNA_LED_MODE … #define EEPROM_ANTENNA_DYN_TXAGC … #define EEPROM_ANTENNA_HARDWARE_RADIO … #define EEPROM_ANTENNA_RF_TYPE … /* * EEPROM NIC config. * CARDBUS_ACCEL: 0: enable, 1: disable. * DYN_BBP_TUNE: 0: enable, 1: disable. * CCK_TX_POWER: CCK TX power compensation. */ #define EEPROM_NIC … #define EEPROM_NIC_CARDBUS_ACCEL … #define EEPROM_NIC_DYN_BBP_TUNE … #define EEPROM_NIC_CCK_TX_POWER … /* * EEPROM geography. * GEO: Default geography setting for device. */ #define EEPROM_GEOGRAPHY … #define EEPROM_GEOGRAPHY_GEO … /* * EEPROM BBP. */ #define EEPROM_BBP_START … #define EEPROM_BBP_SIZE … #define EEPROM_BBP_VALUE … #define EEPROM_BBP_REG_ID … /* * EEPROM TXPOWER */ #define EEPROM_TXPOWER_START … #define EEPROM_TXPOWER_SIZE … #define EEPROM_TXPOWER_1 … #define EEPROM_TXPOWER_2 … /* * EEPROM Tuning threshold */ #define EEPROM_BBPTUNE … #define EEPROM_BBPTUNE_THRESHOLD … /* * EEPROM BBP R24 Tuning. */ #define EEPROM_BBPTUNE_R24 … #define EEPROM_BBPTUNE_R24_LOW … #define EEPROM_BBPTUNE_R24_HIGH … /* * EEPROM BBP R25 Tuning. */ #define EEPROM_BBPTUNE_R25 … #define EEPROM_BBPTUNE_R25_LOW … #define EEPROM_BBPTUNE_R25_HIGH … /* * EEPROM BBP R24 Tuning. */ #define EEPROM_BBPTUNE_R61 … #define EEPROM_BBPTUNE_R61_LOW … #define EEPROM_BBPTUNE_R61_HIGH … /* * EEPROM BBP VGC Tuning. */ #define EEPROM_BBPTUNE_VGC … #define EEPROM_BBPTUNE_VGCUPPER … #define EEPROM_BBPTUNE_VGCLOWER … /* * EEPROM BBP R17 Tuning. */ #define EEPROM_BBPTUNE_R17 … #define EEPROM_BBPTUNE_R17_LOW … #define EEPROM_BBPTUNE_R17_HIGH … /* * RSSI <-> dBm offset calibration */ #define EEPROM_CALIBRATE_OFFSET … #define EEPROM_CALIBRATE_OFFSET_RSSI … /* * DMA descriptor defines. */ #define TXD_DESC_SIZE … #define RXD_DESC_SIZE … /* * TX descriptor format for TX, PRIO, ATIM and Beacon Ring. */ /* * Word0 */ #define TXD_W0_PACKET_ID … #define TXD_W0_RETRY_LIMIT … #define TXD_W0_MORE_FRAG … #define TXD_W0_ACK … #define TXD_W0_TIMESTAMP … #define TXD_W0_OFDM … #define TXD_W0_NEW_SEQ … #define TXD_W0_IFS … #define TXD_W0_DATABYTE_COUNT … #define TXD_W0_CIPHER … #define TXD_W0_KEY_ID … /* * Word1 */ #define TXD_W1_IV_OFFSET … #define TXD_W1_AIFS … #define TXD_W1_CWMIN … #define TXD_W1_CWMAX … /* * Word2: PLCP information */ #define TXD_W2_PLCP_SIGNAL … #define TXD_W2_PLCP_SERVICE … #define TXD_W2_PLCP_LENGTH_LOW … #define TXD_W2_PLCP_LENGTH_HIGH … /* * Word3 */ #define TXD_W3_IV … /* * Word4 */ #define TXD_W4_EIV … /* * RX descriptor format for RX Ring. */ /* * Word0 */ #define RXD_W0_UNICAST_TO_ME … #define RXD_W0_MULTICAST … #define RXD_W0_BROADCAST … #define RXD_W0_MY_BSS … #define RXD_W0_CRC_ERROR … #define RXD_W0_OFDM … #define RXD_W0_PHYSICAL_ERROR … #define RXD_W0_CIPHER … #define RXD_W0_CIPHER_ERROR … #define RXD_W0_DATABYTE_COUNT … /* * Word1 */ #define RXD_W1_RSSI … #define RXD_W1_SIGNAL … /* * Word2 */ #define RXD_W2_IV … /* * Word3 */ #define RXD_W3_EIV … /* * Macros for converting txpower from EEPROM to mac80211 value * and from mac80211 value to register value. */ #define MIN_TXPOWER … #define MAX_TXPOWER … #define DEFAULT_TXPOWER … #define TXPOWER_FROM_DEV(__txpower) … #define TXPOWER_TO_DEV(__txpower) … #endif /* RT2500USB_H */
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