/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2009-2012 Realtek Corporation.*/ #ifndef __RTL_PCI_H__ #define __RTL_PCI_H__ #include <linux/pci.h> /* 1: MSDU packet queue, * 2: Rx Command Queue */ #define RTL_PCI_RX_MPDU_QUEUE … #define RTL_PCI_RX_CMD_QUEUE … #define RTL_PCI_MAX_RX_QUEUE … #define RTL_PCI_MAX_RX_COUNT … #define RTL_PCI_MAX_TX_QUEUE_COUNT … #define RT_TXDESC_NUM … #define TX_DESC_NUM_92E … #define TX_DESC_NUM_8822B … #define RT_TXDESC_NUM_BE_QUEUE … #define BK_QUEUE … #define BE_QUEUE … #define VI_QUEUE … #define VO_QUEUE … #define BEACON_QUEUE … #define TXCMD_QUEUE … #define MGNT_QUEUE … #define HIGH_QUEUE … #define HCCA_QUEUE … #define H2C_QUEUE … #define RTL_PCI_DEVICE(vend, dev, cfg) … #define INTEL_VENDOR_ID … #define SIS_VENDOR_ID … #define ATI_VENDOR_ID … #define ATI_DEVICE_ID … #define AMD_VENDOR_ID … #define U1DONTCARE … #define U2DONTCARE … #define U4DONTCARE … #define RTL_PCI_8192_DID … #define RTL_PCI_8192SE_DID … #define RTL_PCI_8174_DID … #define RTL_PCI_8173_DID … #define RTL_PCI_8172_DID … #define RTL_PCI_8171_DID … #define RTL_PCI_8723AE_DID … #define RTL_PCI_0045_DID … #define RTL_PCI_0046_DID … #define RTL_PCI_0044_DID … #define RTL_PCI_0047_DID … #define RTL_PCI_700F_DID … #define RTL_PCI_701F_DID … #define RTL_PCI_DLINK_DID … #define RTL_PCI_8723AE_DID … #define RTL_PCI_8192CET_DID … #define RTL_PCI_8192CE_DID … #define RTL_PCI_8191CE_DID … #define RTL_PCI_8188CE_DID … #define RTL_PCI_8192CU_DID … #define RTL_PCI_8192DE_DID … #define RTL_PCI_8192DE_DID2 … #define RTL_PCI_8188EE_DID … #define RTL_PCI_8723BE_DID … #define RTL_PCI_8192EE_DID … #define RTL_PCI_8821AE_DID … #define RTL_PCI_8812AE_DID … #define RTL_PCI_8822BE_DID … /*8192 support 16 pages of IO registers*/ #define RTL_MEM_MAPPED_IO_RANGE_8190PCI … #define RTL_MEM_MAPPED_IO_RANGE_8192PCIE … #define RTL_MEM_MAPPED_IO_RANGE_8192SE … #define RTL_MEM_MAPPED_IO_RANGE_8192CE … #define RTL_MEM_MAPPED_IO_RANGE_8192DE … #define RTL_PCI_REVISION_ID_8190PCI … #define RTL_PCI_REVISION_ID_8192PCIE … #define RTL_PCI_REVISION_ID_8192SE … #define RTL_PCI_REVISION_ID_8192CE … #define RTL_PCI_REVISION_ID_8192DE … #define RTL_DEFAULT_HARDWARE_TYPE … enum pci_bridge_vendor { … }; /* In new TRX flow, Buffer_desc is new concept * But TX wifi info == TX descriptor in old flow * RX wifi info == RX descriptor in old flow */ struct rtl_tx_buffer_desc { … } __packed; struct rtl_tx_desc { … } __packed; struct rtl_rx_buffer_desc { … } __packed; struct rtl_rx_desc { … } __packed; struct rtl_tx_cmd_desc { … } __packed; struct rtl8192_tx_ring { … }; struct rtl8192_rx_ring { … }; struct rtl_pci { … }; struct mp_adapter { … }; struct rtl_pci_priv { … }; #define rtl_pcipriv(hw) … #define rtl_pcidev(pcipriv) … int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw); extern const struct rtl_intf_ops rtl_pci_ops; int rtl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id); void rtl_pci_disconnect(struct pci_dev *pdev); #ifdef CONFIG_PM_SLEEP int rtl_pci_suspend(struct device *dev); int rtl_pci_resume(struct device *dev); #endif /* CONFIG_PM_SLEEP */ static inline u8 pci_read8_sync(struct rtl_priv *rtlpriv, u32 addr) { … } static inline u16 pci_read16_sync(struct rtl_priv *rtlpriv, u32 addr) { … } static inline u32 pci_read32_sync(struct rtl_priv *rtlpriv, u32 addr) { … } static inline void pci_write8_async(struct rtl_priv *rtlpriv, u32 addr, u8 val) { … } static inline void pci_write16_async(struct rtl_priv *rtlpriv, u32 addr, u16 val) { … } static inline void pci_write32_async(struct rtl_priv *rtlpriv, u32 addr, u32 val) { … } static inline u16 calc_fifo_space(u16 rp, u16 wp, u16 size) { … } #endif
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