/* SPDX-License-Identifier: GPL-2.0 */ /* Copyright(c) 2009-2012 Realtek Corporation.*/ #ifndef __REALTEK_FIRMWARE92S_H__ #define __REALTEK_FIRMWARE92S_H__ #define RTL8190_MAX_FIRMWARE_CODE_SIZE … #define RTL8190_MAX_RAW_FIRMWARE_CODE_SIZE … #define RTL8190_CPU_START_OFFSET … /* Firmware Local buffer size. 64k */ #define MAX_FIRMWARE_CODE_SIZE … #define RT_8192S_FIRMWARE_HDR_SIZE … #define RT_8192S_FIRMWARE_HDR_EXCLUDE_PRI_SIZE … /* support till 64 bit bus width OS */ #define MAX_DEV_ADDR_SIZE … #define MAX_FIRMWARE_INFORMATION_SIZE … #define MAX_802_11_HEADER_LENGTH … #define ENCRYPTION_MAX_OVERHEAD … #define MAX_FRAGMENT_COUNT … #define MAX_TRANSMIT_BUFFER_SIZE … #define H2C_TX_CMD_HDR_LEN … /* The following DM control code are for Reg0x364, */ #define FW_DIG_ENABLE_CTL … #define FW_HIGH_PWR_ENABLE_CTL … #define FW_SS_CTL … #define FW_RA_INIT_CTL … #define FW_RA_BG_CTL … #define FW_RA_N_CTL … #define FW_PWR_TRK_CTL … #define FW_IQK_CTL … #define FW_FA_CTL … #define FW_DRIVER_CTRL_DM_CTL … #define FW_PAPE_CTL_BY_SW_HW … #define FW_DISABLE_ALL_DM … #define FW_PWR_TRK_PARAM_CLR … #define FW_RA_PARAM_CLR … enum desc_packet_type { … }; /* 8-bytes alignment required */ struct fw_priv { … }; /* 8-byte alinment required */ struct fw_hdr { … } ; enum fw_status { … }; struct rt_firmware { … }; struct h2c_set_pwrmode_parm { … }; struct h2c_joinbss_rpt_parm { … } ; struct h2c_wpa_ptk { … }; struct h2c_wpa_two_way_parm { … } ; enum h2c_cmd { … }; enum fw_h2c_cmd { … }; /* The following macros are used for FW * CMD map and parameter updated. */ #define FW_CMD_IO_CLR(rtlpriv, _bit) … #define FW_CMD_IO_UPDATE(rtlpriv, _val) … #define FW_CMD_IO_SET(rtlpriv, _val) … #define FW_CMD_PARA_SET(rtlpriv, _val) … #define FW_CMD_IO_QUERY(rtlpriv) … #define FW_CMD_IO_PARA_QUERY(rtlpriv) … int rtl92s_download_fw(struct ieee80211_hw *hw); void rtl92s_set_fw_pwrmode_cmd(struct ieee80211_hw *hw, u8 mode); void rtl92s_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus, u8 ps_qosinfo); #endif
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