/* SPDX-License-Identifier: GPL-2.0-only */ /* * Copyright (c) 2014 - 2017 Jes Sorensen <[email protected]> * * Register definitions taken from original Realtek rtl8723au driver */ #include <linux/average.h> #include <linux/usb.h> #include <net/mac80211.h> #define RTL8XXXU_DEBUG_REG_WRITE … #define RTL8XXXU_DEBUG_REG_READ … #define RTL8XXXU_DEBUG_RFREG_WRITE … #define RTL8XXXU_DEBUG_RFREG_READ … #define RTL8XXXU_DEBUG_CHANNEL … #define RTL8XXXU_DEBUG_TX … #define RTL8XXXU_DEBUG_TX_DUMP … #define RTL8XXXU_DEBUG_RX … #define RTL8XXXU_DEBUG_RX_DUMP … #define RTL8XXXU_DEBUG_USB … #define RTL8XXXU_DEBUG_KEY … #define RTL8XXXU_DEBUG_H2C … #define RTL8XXXU_DEBUG_ACTION … #define RTL8XXXU_DEBUG_EFUSE … #define RTL8XXXU_DEBUG_INTERRUPT … #define RTW_USB_CONTROL_MSG_TIMEOUT … #define RTL8XXXU_MAX_REG_POLL … #define USB_INTR_CONTENT_LENGTH … #define RTL8XXXU_OUT_ENDPOINTS … #define REALTEK_USB_READ … #define REALTEK_USB_WRITE … #define REALTEK_USB_CMD_REQ … #define REALTEK_USB_CMD_IDX … #define TX_TOTAL_PAGE_NUM … #define TX_TOTAL_PAGE_NUM_8188F … #define TX_TOTAL_PAGE_NUM_8188E … #define TX_TOTAL_PAGE_NUM_8192E … #define TX_TOTAL_PAGE_NUM_8723B … #define TX_TOTAL_PAGE_NUM_8192F … /* (HPQ + LPQ + NPQ + PUBQ) = TX_TOTAL_PAGE_NUM */ #define TX_PAGE_NUM_PUBQ … #define TX_PAGE_NUM_HI_PQ … #define TX_PAGE_NUM_LO_PQ … #define TX_PAGE_NUM_NORM_PQ … #define TX_PAGE_NUM_PUBQ_8188F … #define TX_PAGE_NUM_HI_PQ_8188F … #define TX_PAGE_NUM_LO_PQ_8188F … #define TX_PAGE_NUM_NORM_PQ_8188F … #define TX_PAGE_NUM_PUBQ_8188E … #define TX_PAGE_NUM_HI_PQ_8188E … #define TX_PAGE_NUM_LO_PQ_8188E … #define TX_PAGE_NUM_NORM_PQ_8188E … #define TX_PAGE_NUM_PUBQ_8192E … #define TX_PAGE_NUM_HI_PQ_8192E … #define TX_PAGE_NUM_LO_PQ_8192E … #define TX_PAGE_NUM_NORM_PQ_8192E … #define TX_PAGE_NUM_PUBQ_8723B … #define TX_PAGE_NUM_HI_PQ_8723B … #define TX_PAGE_NUM_LO_PQ_8723B … #define TX_PAGE_NUM_NORM_PQ_8723B … #define TX_PAGE_NUM_PUBQ_8192F … #define TX_PAGE_NUM_HI_PQ_8192F … #define TX_PAGE_NUM_LO_PQ_8192F … #define TX_PAGE_NUM_NORM_PQ_8192F … #define RTL_FW_PAGE_SIZE … #define RTL8XXXU_FIRMWARE_POLL_MAX … #define RTL8723A_CHANNEL_GROUPS … #define RTL8723A_MAX_RF_PATHS … #define RTL8723B_CHANNEL_GROUPS … #define RTL8723B_TX_COUNT … #define RTL8723B_MAX_RF_PATHS … #define RTL8XXXU_MAX_CHANNEL_GROUPS … #define RF6052_MAX_TX_PWR … #define EFUSE_MAP_LEN … #define EFUSE_MAX_SECTION_8723A … #define EFUSE_REAL_CONTENT_LEN_8723A … #define EFUSE_BT_MAP_LEN_8723A … #define EFUSE_MAX_WORD_UNIT … #define EFUSE_UNDEFINED … enum rtl8xxxu_rtl_chip { … }; enum rtl8xxxu_rx_type { … }; enum rtl8xxxu_rx_desc_enc { … }; struct rtl8xxxu_rxdesc16 { … }; struct rtl8xxxu_rxdesc24 { … }; struct rtl8xxxu_txdesc32 { … }; struct rtl8xxxu_txdesc40 { … }; /* CCK Rates, TxHT = 0 */ #define DESC_RATE_1M … #define DESC_RATE_2M … #define DESC_RATE_5_5M … #define DESC_RATE_11M … /* OFDM Rates, TxHT = 0 */ #define DESC_RATE_6M … #define DESC_RATE_9M … #define DESC_RATE_12M … #define DESC_RATE_18M … #define DESC_RATE_24M … #define DESC_RATE_36M … #define DESC_RATE_48M … #define DESC_RATE_54M … /* MCS Rates, TxHT = 1 */ #define DESC_RATE_MCS0 … #define DESC_RATE_MCS1 … #define DESC_RATE_MCS2 … #define DESC_RATE_MCS3 … #define DESC_RATE_MCS4 … #define DESC_RATE_MCS5 … #define DESC_RATE_MCS6 … #define DESC_RATE_MCS7 … #define DESC_RATE_MCS8 … #define DESC_RATE_MCS9 … #define DESC_RATE_MCS10 … #define DESC_RATE_MCS11 … #define DESC_RATE_MCS12 … #define DESC_RATE_MCS13 … #define DESC_RATE_MCS14 … #define DESC_RATE_MCS15 … #define DESC_RATE_MCS15_SG … #define DESC_RATE_MCS32 … #define TXDESC_OFFSET_SZ … #define TXDESC_OFFSET_SHT … #if 0 #define TXDESC_BMC … #define TXDESC_LSG … #define TXDESC_FSG … #define TXDESC_OWN … #else #define TXDESC_BROADMULTICAST … #define TXDESC_HTC … #define TXDESC_LAST_SEGMENT … #define TXDESC_FIRST_SEGMENT … #define TXDESC_LINIP … #define TXDESC_NO_ACM … #define TXDESC_GF … #define TXDESC_OWN … #endif /* Word 1 */ /* * Bits 0-7 differ dependent on chip generation. For 8723au bits 5/6 are * aggregation enable and break respectively. For 8723bu, bits 0-7 are macid. */ #define TXDESC_PKT_OFFSET_SZ … #define TXDESC32_AGG_ENABLE … #define TXDESC32_AGG_BREAK … #define TXDESC40_MACID_SHIFT … #define TXDESC40_MACID_MASK … #define TXDESC_QUEUE_SHIFT … #define TXDESC_QUEUE_MASK … #define TXDESC_QUEUE_BK … #define TXDESC_QUEUE_BE … #define TXDESC_QUEUE_VI … #define TXDESC_QUEUE_VO … #define TXDESC_QUEUE_BEACON … #define TXDESC_QUEUE_HIGH … #define TXDESC_QUEUE_MGNT … #define TXDESC_QUEUE_CMD … #define TXDESC_QUEUE_MAX … #define TXDESC40_RDG_NAV_EXT … #define TXDESC40_LSIG_TXOP_ENABLE … #define TXDESC40_PIFS … #define DESC_RATE_ID_SHIFT … #define DESC_RATE_ID_MASK … #define TXDESC_NAVUSEHDR … #define TXDESC_EN_DESC_ID … #define TXDESC_SEC_RC4 … #define TXDESC_SEC_AES … #define TXDESC_PKT_OFFSET_SHIFT … #define TXDESC_AGG_EN … #define TXDESC_HWPC … /* Word 2 */ #define TXDESC40_PAID_SHIFT … #define TXDESC40_PAID_MASK … #define TXDESC40_CCA_RTS_SHIFT … #define TXDESC40_CCA_RTS_MASK … #define TXDESC40_AGG_ENABLE … #define TXDESC40_RDG_ENABLE … #define TXDESC40_AGG_BREAK … #define TXDESC40_MORE_FRAG … #define TXDESC40_RAW … #define TXDESC32_ACK_REPORT … #define TXDESC40_SPE_RPT … #define TXDESC_AMPDU_DENSITY_SHIFT … #define TXDESC40_BT_INT … #define TXDESC40_GID_SHIFT … #define TXDESC_ANTENNA_SELECT_A … #define TXDESC_ANTENNA_SELECT_B … /* Word 3 */ #define TXDESC40_USE_DRIVER_RATE … #define TXDESC40_CTS_SELF_ENABLE … #define TXDESC40_RTS_CTS_ENABLE … #define TXDESC40_HW_RTS_ENABLE … #define TXDESC32_SEQ_SHIFT … #define TXDESC32_SEQ_MASK … /* Word 4 */ #define TXDESC32_RTS_RATE_SHIFT … #define TXDESC32_RTS_RATE_MASK … #define TXDESC32_QOS … #define TXDESC32_HW_SEQ_ENABLE … #define TXDESC32_USE_DRIVER_RATE … #define TXDESC_DISABLE_DATA_FB … #define TXDESC32_CTS_SELF_ENABLE … #define TXDESC32_RTS_CTS_ENABLE … #define TXDESC32_HW_RTS_ENABLE … #define TXDESC32_PT_STAGE_MASK … #define TXDESC_PRIME_CH_OFF_LOWER … #define TXDESC_PRIME_CH_OFF_UPPER … #define TXDESC32_SHORT_PREAMBLE … #define TXDESC_DATA_BW … #define TXDESC_RTS_DATA_BW … #define TXDESC_RTS_PRIME_CH_OFF_LOWER … #define TXDESC_RTS_PRIME_CH_OFF_UPPER … #define TXDESC40_DATA_RATE_FB_SHIFT … #define TXDESC40_DATA_RATE_FB_MASK … #define TXDESC40_RETRY_LIMIT_ENABLE … #define TXDESC40_RETRY_LIMIT_SHIFT … #define TXDESC40_RETRY_LIMIT_MASK … #define TXDESC40_RTS_RATE_SHIFT … #define TXDESC40_RTS_RATE_MASK … /* Word 5 */ #define TXDESC40_SHORT_PREAMBLE … #define TXDESC32_SHORT_GI … #define TXDESC_CCX_TAG … #define TXDESC32_RETRY_LIMIT_ENABLE … #define TXDESC32_RETRY_LIMIT_SHIFT … #define TXDESC32_RETRY_LIMIT_MASK … /* Word 6 */ #define TXDESC_MAX_AGG_SHIFT … #define TXDESC_USB_TX_AGG_SHIT … /* Word 7 */ #define TXDESC_ANTENNA_SELECT_C … /* Word 8 */ #define TXDESC40_HW_SEQ_ENABLE … /* Word 9 */ #define TXDESC40_SEQ_SHIFT … #define TXDESC40_SEQ_MASK … struct phy_rx_agc_info { … }; #define CCK_AGC_RPT_LNA_IDX_MASK … #define CCK_AGC_RPT_VGA_IDX_MASK … struct rtl8723au_phy_stats { … }; struct jaguar2_phy_stats_type0 { … } __packed; struct jaguar2_phy_stats_type1 { … } __packed; struct jaguar2_phy_stats_type2 { … } __packed; /* * Regs to backup */ #define RTL8XXXU_ADDA_REGS … #define RTL8XXXU_MAC_REGS … #define RTL8XXXU_BB_REGS … struct rtl8xxxu_firmware_header { … }; /* * 8723au/8192cu/8188ru required base power index offset tables. */ struct rtl8xxxu_power_base { … }; /* * The 8723au has 3 channel groups: 1-3, 4-9, and 10-14 */ struct rtl8723au_idx { … } __attribute__((packed)); struct rtl8723au_efuse { … }; struct rtl8192cu_efuse { … }; struct rtl8723bu_pwr_idx { … } __attribute__((packed)); struct rtl8723bu_efuse_tx_power { … }; struct rtl8723bu_efuse { … }; struct rtl8192eu_efuse_tx_power { … }; struct rtl8192eu_efuse { … }; struct rtl8188fu_efuse_tx_power { … }; struct rtl8188fu_efuse { … }; struct rtl8188eu_efuse { … } __packed; struct rtl8710bu_efuse { … } __packed; struct rtl8192fu_efuse { … } __packed; struct rtl8xxxu_reg8val { … }; struct rtl8xxxu_reg32val { … }; struct rtl8xxxu_rfregval { … }; enum rtl8xxxu_rfpath { … }; struct rtl8xxxu_rfregs { … }; #define H2C_MAX_MBOX … #define H2C_EXT … #define H2C_JOIN_BSS_DISCONNECT … #define H2C_JOIN_BSS_CONNECT … #define H2C_MACID_ROLE_STA … #define H2C_MACID_ROLE_AP … /* * H2C (firmware) commands differ between the older generation chips * 8188[cr]u, 819[12]cu, and 8723au, and the more recent chips 8723bu, * 8192[de]u, 8192eu, and 8812. */ enum h2c_cmd_8723a { … }; enum h2c_cmd_8723b { … }; struct h2c_cmd { … }; enum c2h_evt_8723b { … }; enum bt_info_src_8723b { … }; enum bt_mp_oper_opcode_8723b { … }; enum rtl8xxxu_bw_mode { … }; struct rtl8723bu_c2h { … } __packed; struct rtl8xxxu_fileops; /*mlme related.*/ enum wireless_mode { … }; /* from rtlwifi/wifi.h */ enum ratr_table_mode_new { … }; #define BT_INFO_8723B_1ANT_B_FTP … #define BT_INFO_8723B_1ANT_B_A2DP … #define BT_INFO_8723B_1ANT_B_HID … #define BT_INFO_8723B_1ANT_B_SCO_BUSY … #define BT_INFO_8723B_1ANT_B_ACL_BUSY … #define BT_INFO_8723B_1ANT_B_INQ_PAGE … #define BT_INFO_8723B_1ANT_B_SCO_ESCO … #define BT_INFO_8723B_1ANT_B_CONNECTION … enum _BT_8723B_1ANT_STATUS { … }; struct rtl8xxxu_btcoex { … }; #define RTL8XXXU_RATR_STA_INIT … #define RTL8XXXU_RATR_STA_HIGH … #define RTL8XXXU_RATR_STA_MID … #define RTL8XXXU_RATR_STA_LOW … #define RTL8XXXU_NOISE_FLOOR_MIN … #define RTL8XXXU_SNR_THRESH_HIGH … #define RTL8XXXU_SNR_THRESH_LOW … struct rtl8xxxu_ra_report { … }; struct rtl8xxxu_ra_info { … }; #define CFO_TH_XTAL_HIGH … #define CFO_TH_XTAL_LOW … #define CFO_TH_ATC … struct rtl8xxxu_cfo_tracking { … }; #define RTL8XXXU_HW_LED_CONTROL … #define RTL8XXXU_MAX_MAC_ID_NUM … #define RTL8XXXU_BC_MC_MACID … #define RTL8XXXU_BC_MC_MACID1 … #define RTL8XXXU_MAX_SEC_CAM_NUM … struct rtl8xxxu_priv { … }; DECLARE_EWMA(rssi, 10, 16); struct rtl8xxxu_sta_info { … }; struct rtl8xxxu_vif { … }; struct rtl8xxxu_rx_urb { … }; struct rtl8xxxu_tx_urb { … }; struct rtl8xxxu_fileops { … }; extern int rtl8xxxu_debug; extern const u32 rtl8xxxu_iqk_phy_iq_bb_reg[]; u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr); u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr); u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr); int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val); int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val); int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val); int rtl8xxxu_write8_set(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); int rtl8xxxu_write8_clear(struct rtl8xxxu_priv *priv, u16 addr, u8 bits); int rtl8xxxu_write16_set(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); int rtl8xxxu_write16_clear(struct rtl8xxxu_priv *priv, u16 addr, u16 bits); int rtl8xxxu_write32_set(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); int rtl8xxxu_write32_clear(struct rtl8xxxu_priv *priv, u16 addr, u32 bits); int rtl8xxxu_write32_mask(struct rtl8xxxu_priv *priv, u16 addr, u32 mask, u32 val); u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, enum rtl8xxxu_rfpath path, u8 reg); int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, enum rtl8xxxu_rfpath path, u8 reg, u32 data); int rtl8xxxu_write_rfreg_mask(struct rtl8xxxu_priv *priv, enum rtl8xxxu_rfpath path, u8 reg, u32 mask, u32 val); void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, u32 *backup, int count); void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, u32 *backup, int count); void rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup); void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup); void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, bool path_a_on); void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, const u32 *regs, u32 *backup); void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok, int result[][8], int candidate, bool tx_only); void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok, int result[][8], int candidate, bool tx_only); int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, const struct rtl8xxxu_rfregval *table, enum rtl8xxxu_rfpath path); int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, const struct rtl8xxxu_reg32val *array); int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, const char *fw_name); void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv); void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv); void rtl8xxxu_identify_vendor_1bit(struct rtl8xxxu_priv *priv, u32 vendor); void rtl8xxxu_identify_vendor_2bits(struct rtl8xxxu_priv *priv, u32 vendor); void rtl8xxxu_config_endpoints_sie(struct rtl8xxxu_priv *priv); int rtl8xxxu_config_endpoints_no_sie(struct rtl8xxxu_priv *priv); int rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data); int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv); void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv); int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start); void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv); void rtl8188f_phy_lc_calibrate(struct rtl8xxxu_priv *priv); int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv); int rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len); int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv); void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv); int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40); void rtl8188f_channel_to_group(int channel, int *group, int *cck_group); void rtl8188f_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40); void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw); void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw); void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv); void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, u8 rateid, int sgi, int txbw_40mhz, u8 macid); void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv, u8 macid, u8 role, bool connect); void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv, u8 macid, u8 role, bool connect); void rtl8xxxu_gen1_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); void rtl8xxxu_gen2_report_rssi(struct rtl8xxxu_priv *priv, u8 macid, u8 rssi); void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv); void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv); void rtl8xxxu_init_burst(struct rtl8xxxu_priv *priv); int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb); int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb); void rtl8723au_rx_parse_phystats(struct rtl8xxxu_priv *priv, struct ieee80211_rx_status *rx_status, struct rtl8723au_phy_stats *phy_stats, u32 rxmcs, struct ieee80211_hdr *hdr, bool crc_icv_err); void jaguar2_rx_parse_phystats(struct rtl8xxxu_priv *priv, struct ieee80211_rx_status *rx_status, struct rtl8723au_phy_stats *phy_stats, u32 rxmcs, struct ieee80211_hdr *hdr, bool crc_icv_err); int rtl8xxxu_gen2_channel_to_group(int channel); bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, int result[][8], int c1, int c2); bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv, int result[][8], int c1, int c2); void rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, struct ieee80211_tx_info *tx_info, struct rtl8xxxu_txdesc32 *tx_desc, bool sgi, bool short_preamble, bool ampdu_enable, u32 rts_rate, u8 macid); void rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, struct ieee80211_tx_info *tx_info, struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, bool short_preamble, bool ampdu_enable, u32 rts_rate, u8 macid); void rtl8xxxu_fill_txdesc_v3(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr, struct ieee80211_tx_info *tx_info, struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi, bool short_preamble, bool ampdu_enable, u32 rts_rate, u8 macid); void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5); void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv); void rtl8723a_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); void rtl8188f_set_crystal_cap(struct rtl8xxxu_priv *priv, u8 crystal_cap); s8 rtl8723a_cck_rssi(struct rtl8xxxu_priv *priv, struct rtl8723au_phy_stats *phy_stats); void rtl8xxxu_update_ra_report(struct rtl8xxxu_ra_report *rarpt, u8 rate, u8 sgi, u8 bw); void rtl8188e_ra_info_init_all(struct rtl8xxxu_ra_info *ra); void rtl8188e_handle_ra_tx_report2(struct rtl8xxxu_priv *priv, struct sk_buff *skb); extern struct rtl8xxxu_fileops rtl8192fu_fops; extern struct rtl8xxxu_fileops rtl8710bu_fops; extern struct rtl8xxxu_fileops rtl8188fu_fops; extern struct rtl8xxxu_fileops rtl8188eu_fops; extern struct rtl8xxxu_fileops rtl8192cu_fops; extern struct rtl8xxxu_fileops rtl8192eu_fops; extern struct rtl8xxxu_fileops rtl8723au_fops; extern struct rtl8xxxu_fileops rtl8723bu_fops;
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