/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright(c) 2019-2020 Realtek Corporation */ #ifndef __RTW89_FW_H__ #define __RTW89_FW_H__ #include "core.h" enum rtw89_fw_dl_status { … }; struct rtw89_c2hreg_hdr { … }; #define RTW89_C2HREG_HDR_FUNC_MASK … #define RTW89_C2HREG_HDR_ACK … #define RTW89_C2HREG_HDR_LEN_MASK … #define RTW89_C2HREG_HDR_SEQ_MASK … struct rtw89_c2hreg_phycap { … } __packed; #define RTW89_C2HREG_PHYCAP_W0_FUNC … #define RTW89_C2HREG_PHYCAP_W0_ACK … #define RTW89_C2HREG_PHYCAP_W0_LEN … #define RTW89_C2HREG_PHYCAP_W0_SEQ … #define RTW89_C2HREG_PHYCAP_W0_RX_NSS … #define RTW89_C2HREG_PHYCAP_W0_BW … #define RTW89_C2HREG_PHYCAP_W1_TX_NSS … #define RTW89_C2HREG_PHYCAP_W1_PROT … #define RTW89_C2HREG_PHYCAP_W1_NIC … #define RTW89_C2HREG_PHYCAP_W1_WL_FUNC … #define RTW89_C2HREG_PHYCAP_W2_HW_TYPE … #define RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM … #define RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM … #define RTW89_C2HREG_AOAC_RPT_1_W0_KEY_IDX … #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_0 … #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_1 … #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_2 … #define RTW89_C2HREG_AOAC_RPT_1_W1_IV_3 … #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_4 … #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_5 … #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_6 … #define RTW89_C2HREG_AOAC_RPT_1_W2_IV_7 … #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_0 … #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_1 … #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_2 … #define RTW89_C2HREG_AOAC_RPT_1_W3_PTK_IV_3 … #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_4 … #define RTW89_C2HREG_AOAC_RPT_2_W0_PTK_IV_5 … #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_6 … #define RTW89_C2HREG_AOAC_RPT_2_W1_PTK_IV_7 … #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_0 … #define RTW89_C2HREG_AOAC_RPT_2_W1_IGTK_IPN_IV_1 … #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_2 … #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_3 … #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_4 … #define RTW89_C2HREG_AOAC_RPT_2_W2_IGTK_IPN_IV_5 … #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_6 … #define RTW89_C2HREG_AOAC_RPT_2_W3_IGTK_IPN_IV_7 … struct rtw89_h2creg_hdr { … }; #define RTW89_H2CREG_HDR_FUNC_MASK … #define RTW89_H2CREG_HDR_LEN_MASK … struct rtw89_h2creg_sch_tx_en { … } __packed; #define RTW89_H2CREG_SCH_TX_EN_W0_EN … #define RTW89_H2CREG_SCH_TX_EN_W1_MASK … #define RTW89_H2CREG_SCH_TX_EN_W1_BAND … #define RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN … #define RTW89_H2CREG_MAX … #define RTW89_C2HREG_MAX … #define RTW89_C2HREG_HDR_LEN … #define RTW89_H2CREG_HDR_LEN … #define RTW89_C2H_TIMEOUT … struct rtw89_mac_c2h_info { … }; struct rtw89_mac_h2c_info { … }; enum rtw89_mac_h2c_type { … }; enum rtw89_mac_c2h_type { … }; enum rtw89_fw_c2h_category { … }; enum rtw89_fw_log_level { … }; enum rtw89_fw_log_path { … }; enum rtw89_fw_log_comp { … }; enum rtw89_pkt_offload_op { … }; #define RTW89_PKT_OFLD_WAIT_TAG(pkt_id, pkt_op) … enum rtw89_scanofld_notify_reason { … }; enum rtw89_scanofld_status { … }; enum rtw89_chan_type { … }; enum rtw89_p2pps_action { … }; #define RTW89_DEFAULT_CQM_HYST … #define RTW89_DEFAULT_CQM_THOLD … enum rtw89_bcn_fltr_offload_mode { … }; enum rtw89_bcn_fltr_type { … }; enum rtw89_bcn_fltr_rssi_event { … }; #define FWDL_SECTION_MAX_NUM … #define FWDL_SECTION_CHKSUM_LEN … #define FWDL_SECTION_PER_PKT_LEN … struct rtw89_fw_hdr_section_info { … }; struct rtw89_fw_bin_info { … }; struct rtw89_fw_macid_pause_grp { … } __packed; struct rtw89_fw_macid_pause_sleep_grp { … } __packed; #define RTW89_H2C_MAX_SIZE … #define RTW89_CHANNEL_TIME … #define RTW89_CHANNEL_TIME_6G … #define RTW89_DFS_CHAN_TIME … #define RTW89_OFF_CHAN_TIME … #define RTW89_DWELL_TIME … #define RTW89_DWELL_TIME_6G … #define RTW89_SCAN_WIDTH … #define RTW89_SCANOFLD_MAX_SSID … #define RTW89_SCANOFLD_MAX_IE_LEN … #define RTW89_SCANOFLD_PKT_NONE … #define RTW89_SCANOFLD_DEBUG_MASK … #define RTW89_CHAN_INVALID … #define RTW89_MAC_CHINFO_SIZE … #define RTW89_SCAN_LIST_GUARD … #define RTW89_SCAN_LIST_LIMIT … #define RTW89_BCN_LOSS_CNT … struct rtw89_mac_chinfo { … }; struct rtw89_mac_chinfo_be { … }; struct rtw89_pktofld_info { … }; struct rtw89_h2c_ra { … } __packed; #define RTW89_H2C_RA_W0_IS_DIS … #define RTW89_H2C_RA_W0_MODE … #define RTW89_H2C_RA_W0_BW_CAP … #define RTW89_H2C_RA_W0_MACID … #define RTW89_H2C_RA_W0_DCM … #define RTW89_H2C_RA_W0_ER … #define RTW89_H2C_RA_W0_INIT_RATE_LV … #define RTW89_H2C_RA_W0_UPD_ALL … #define RTW89_H2C_RA_W0_SGI … #define RTW89_H2C_RA_W0_LDPC … #define RTW89_H2C_RA_W0_STBC … #define RTW89_H2C_RA_W0_SS_NUM … #define RTW89_H2C_RA_W0_GILTF … #define RTW89_H2C_RA_W0_UPD_BW_NSS_MASK … #define RTW89_H2C_RA_W0_UPD_MASK … #define RTW89_H2C_RA_W1_RAMASK_LO32 … #define RTW89_H2C_RA_W2_RAMASK_HI32 … #define RTW89_H2C_RA_W2_BFEE_CSI_CTL … #define RTW89_H2C_RA_W3_BAND_NUM … #define RTW89_H2C_RA_W3_RA_CSI_RATE_EN … #define RTW89_H2C_RA_W3_FIXED_CSI_RATE_EN … #define RTW89_H2C_RA_W3_CR_TBL_SEL … #define RTW89_H2C_RA_W3_FIX_GILTF_EN … #define RTW89_H2C_RA_W3_FIX_GILTF … #define RTW89_H2C_RA_W3_FIXED_CSI_MCS_SS_IDX … #define RTW89_H2C_RA_W3_FIXED_CSI_MODE … #define RTW89_H2C_RA_W3_FIXED_CSI_GI_LTF … #define RTW89_H2C_RA_W3_FIXED_CSI_BW … struct rtw89_h2c_ra_v1 { … } __packed; #define RTW89_H2C_RA_V1_W4_MODE_EHT … #define RTW89_H2C_RA_V1_W4_BW_EHT … #define RTW89_H2C_RA_V1_W4_RAMASK_UHL16 … #define RTW89_H2C_RA_V1_W5_RAMASK_UHH16 … static inline void RTW89_SET_FWCMD_SEC_IDX(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_OFFSET(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_LEN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_TYPE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_EXT_KEY(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_SPP_MODE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_KEY0(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_KEY1(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_KEY2(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_SEC_KEY3(void *cmd, u32 val) { … } static inline void RTW89_SET_EDCA_SEL(void *cmd, u32 val) { … } static inline void RTW89_SET_EDCA_BAND(void *cmd, u32 val) { … } static inline void RTW89_SET_EDCA_WMM(void *cmd, u32 val) { … } static inline void RTW89_SET_EDCA_AC(void *cmd, u32 val) { … } static inline void RTW89_SET_EDCA_PARAM(void *cmd, u32 val) { … } #define FW_EDCA_PARAM_TXOPLMT_MSK … #define FW_EDCA_PARAM_CWMAX_MSK … #define FW_EDCA_PARAM_CWMIN_MSK … #define FW_EDCA_PARAM_AIFS_MSK … #define FWDL_SECURITY_SECTION_TYPE … #define FWDL_SECURITY_SIGLEN … #define FWDL_SECURITY_CHKSUM_LEN … struct rtw89_fw_dynhdr_sec { … } __packed; struct rtw89_fw_dynhdr_hdr { … } __packed; struct rtw89_fw_hdr_section { … } __packed; #define FWSECTION_HDR_W0_DL_ADDR … #define FWSECTION_HDR_W1_METADATA … #define FWSECTION_HDR_W1_SECTIONTYPE … #define FWSECTION_HDR_W1_SEC_SIZE … #define FWSECTION_HDR_W1_CHECKSUM … #define FWSECTION_HDR_W1_REDL … #define FWSECTION_HDR_W2_MSSC … struct rtw89_fw_hdr { … } __packed; #define FW_HDR_W1_MAJOR_VERSION … #define FW_HDR_W1_MINOR_VERSION … #define FW_HDR_W1_SUBVERSION … #define FW_HDR_W1_SUBINDEX … #define FW_HDR_W2_COMMITID … #define FW_HDR_W3_LEN … #define FW_HDR_W3_HDR_VER … #define FW_HDR_W4_MONTH … #define FW_HDR_W4_DATE … #define FW_HDR_W4_HOUR … #define FW_HDR_W4_MIN … #define FW_HDR_W5_YEAR … #define FW_HDR_W6_SEC_NUM … #define FW_HDR_W7_PART_SIZE … #define FW_HDR_W7_DYN_HDR … #define FW_HDR_W7_CMD_VERSERION … struct rtw89_fw_hdr_section_v1 { … } __packed; #define FWSECTION_HDR_V1_W0_DL_ADDR … #define FWSECTION_HDR_V1_W1_METADATA … #define FWSECTION_HDR_V1_W1_SECTIONTYPE … #define FWSECTION_HDR_V1_W1_SEC_SIZE … #define FWSECTION_HDR_V1_W1_CHECKSUM … #define FWSECTION_HDR_V1_W1_REDL … #define FWSECTION_HDR_V1_W2_MSSC … #define FORMATTED_MSSC … #define FWSECTION_HDR_V1_W2_BBMCU_IDX … struct rtw89_fw_hdr_v1 { … } __packed; #define FW_HDR_V1_W1_MAJOR_VERSION … #define FW_HDR_V1_W1_MINOR_VERSION … #define FW_HDR_V1_W1_SUBVERSION … #define FW_HDR_V1_W1_SUBINDEX … #define FW_HDR_V1_W2_COMMITID … #define FW_HDR_V1_W3_CMD_VERSERION … #define FW_HDR_V1_W3_HDR_VER … #define FW_HDR_V1_W4_MONTH … #define FW_HDR_V1_W4_DATE … #define FW_HDR_V1_W4_HOUR … #define FW_HDR_V1_W4_MIN … #define FW_HDR_V1_W5_YEAR … #define FW_HDR_V1_W5_HDR_SIZE … #define FW_HDR_V1_W6_SEC_NUM … #define FW_HDR_V1_W6_DSP_CHKSUM … #define FW_HDR_V1_W7_PART_SIZE … #define FW_HDR_V1_W7_DYN_HDR … enum rtw89_fw_mss_pool_rmp_tbl_type { … }; #define FWDL_MSS_POOL_DEFKEYSETS_SIZE … struct rtw89_fw_mss_pool_hdr { … } __packed; rtw89_fw_section_mssc_content __packed; static inline void SET_CTRL_INFO_MACID(void *table, u32 val) { … } static inline void SET_CTRL_INFO_OPERATION(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATARATE … static inline void SET_CMC_TBL_DATARATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_FORCE_TXOP … static inline void SET_CMC_TBL_FORCE_TXOP(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_BW … static inline void SET_CMC_TBL_DATA_BW(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_GI_LTF … static inline void SET_CMC_TBL_DATA_GI_LTF(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DARF_TC_INDEX … static inline void SET_CMC_TBL_DARF_TC_INDEX(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ARFR_CTRL … static inline void SET_CMC_TBL_ARFR_CTRL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ACQ_RPT_EN … static inline void SET_CMC_TBL_ACQ_RPT_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_MGQ_RPT_EN … static inline void SET_CMC_TBL_MGQ_RPT_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ULQ_RPT_EN … static inline void SET_CMC_TBL_ULQ_RPT_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_TWTQ_RPT_EN … static inline void SET_CMC_TBL_TWTQ_RPT_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DISRTSFB … static inline void SET_CMC_TBL_DISRTSFB(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DISDATAFB … static inline void SET_CMC_TBL_DISDATAFB(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_TRYRATE … static inline void SET_CMC_TBL_TRYRATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_AMPDU_DENSITY … static inline void SET_CMC_TBL_AMPDU_DENSITY(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_RTY_LOWEST_RATE … static inline void SET_CMC_TBL_DATA_RTY_LOWEST_RATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_AMPDU_TIME_SEL … static inline void SET_CMC_TBL_AMPDU_TIME_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_AMPDU_LEN_SEL … static inline void SET_CMC_TBL_AMPDU_LEN_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT_SEL … static inline void SET_CMC_TBL_RTS_TXCNT_LMT_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTS_TXCNT_LMT … static inline void SET_CMC_TBL_RTS_TXCNT_LMT(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTSRATE … static inline void SET_CMC_TBL_RTSRATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_VCS_STBC … static inline void SET_CMC_TBL_VCS_STBC(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTS_RTY_LOWEST_RATE … static inline void SET_CMC_TBL_RTS_RTY_LOWEST_RATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_TX_CNT_LMT … static inline void SET_CMC_TBL_DATA_TX_CNT_LMT(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_TXCNT_LMT_SEL … static inline void SET_CMC_TBL_DATA_TXCNT_LMT_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_MAX_AGG_NUM_SEL … static inline void SET_CMC_TBL_MAX_AGG_NUM_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTS_EN … static inline void SET_CMC_TBL_RTS_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CTS2SELF_EN … static inline void SET_CMC_TBL_CTS2SELF_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CCA_RTS … static inline void SET_CMC_TBL_CCA_RTS(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_HW_RTS_EN … static inline void SET_CMC_TBL_HW_RTS_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RTS_DROP_DATA_MODE … static inline void SET_CMC_TBL_RTS_DROP_DATA_MODE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_AMPDU_MAX_LEN … static inline void SET_CMC_TBL_AMPDU_MAX_LEN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_UL_MU_DIS … static inline void SET_CMC_TBL_UL_MU_DIS(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_AMPDU_MAX_TIME … static inline void SET_CMC_TBL_AMPDU_MAX_TIME(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_MAX_AGG_NUM … static inline void SET_CMC_TBL_MAX_AGG_NUM(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_BA_BMAP … static inline void SET_CMC_TBL_BA_BMAP(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_VO_LFTIME_SEL … static inline void SET_CMC_TBL_VO_LFTIME_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_VI_LFTIME_SEL … static inline void SET_CMC_TBL_VI_LFTIME_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_BE_LFTIME_SEL … static inline void SET_CMC_TBL_BE_LFTIME_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_BK_LFTIME_SEL … static inline void SET_CMC_TBL_BK_LFTIME_SEL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_SECTYPE … static inline void SET_CMC_TBL_SECTYPE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_MULTI_PORT_ID … static inline void SET_CMC_TBL_MULTI_PORT_ID(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_BMC … static inline void SET_CMC_TBL_BMC(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_MBSSID … static inline void SET_CMC_TBL_MBSSID(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NAVUSEHDR … static inline void SET_CMC_TBL_NAVUSEHDR(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_TXPWR_MODE … static inline void SET_CMC_TBL_TXPWR_MODE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_DCM … static inline void SET_CMC_TBL_DATA_DCM(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_ER … static inline void SET_CMC_TBL_DATA_ER(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_LDPC … static inline void SET_CMC_TBL_DATA_LDPC(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_STBC … static inline void SET_CMC_TBL_DATA_STBC(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_A_CTRL_BQR … static inline void SET_CMC_TBL_A_CTRL_BQR(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_A_CTRL_UPH … static inline void SET_CMC_TBL_A_CTRL_UPH(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_A_CTRL_BSR … static inline void SET_CMC_TBL_A_CTRL_BSR(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_A_CTRL_CAS … static inline void SET_CMC_TBL_A_CTRL_CAS(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DATA_BW_ER … static inline void SET_CMC_TBL_DATA_BW_ER(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_LSIG_TXOP_EN … static inline void SET_CMC_TBL_LSIG_TXOP_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CTRL_CNT_VLD … static inline void SET_CMC_TBL_CTRL_CNT_VLD(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CTRL_CNT … static inline void SET_CMC_TBL_CTRL_CNT(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_RESP_REF_RATE … static inline void SET_CMC_TBL_RESP_REF_RATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ALL_ACK_SUPPORT … static inline void SET_CMC_TBL_ALL_ACK_SUPPORT(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_BSR_QUEUE_SIZE_FORMAT … static inline void SET_CMC_TBL_BSR_QUEUE_SIZE_FORMAT(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NTX_PATH_EN … static inline void SET_CMC_TBL_NTX_PATH_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_PATH_MAP_A … static inline void SET_CMC_TBL_PATH_MAP_A(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_PATH_MAP_B … static inline void SET_CMC_TBL_PATH_MAP_B(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_PATH_MAP_C … static inline void SET_CMC_TBL_PATH_MAP_C(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_PATH_MAP_D … static inline void SET_CMC_TBL_PATH_MAP_D(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ANTSEL_A … static inline void SET_CMC_TBL_ANTSEL_A(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ANTSEL_B … static inline void SET_CMC_TBL_ANTSEL_B(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ANTSEL_C … static inline void SET_CMC_TBL_ANTSEL_C(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ANTSEL_D … static inline void SET_CMC_TBL_ANTSEL_D(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NOMINAL_PKT_PADDING … static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING_V1(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40_V1(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80_V1(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160_V1(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ADDR_CAM_INDEX … static inline void SET_CMC_TBL_ADDR_CAM_INDEX(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_PAID … static inline void SET_CMC_TBL_PAID(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_ULDL … static inline void SET_CMC_TBL_ULDL(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_DOPPLER_CTRL … static inline void SET_CMC_TBL_DOPPLER_CTRL(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING40(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_TXPWR_TOLERENCE … static inline void SET_CMC_TBL_TXPWR_TOLERENCE(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING80(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NC … static inline void SET_CMC_TBL_NC(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NR … static inline void SET_CMC_TBL_NR(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_NG … static inline void SET_CMC_TBL_NG(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CB … static inline void SET_CMC_TBL_CB(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CS … static inline void SET_CMC_TBL_CS(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_TXBF_EN … static inline void SET_CMC_TBL_CSI_TXBF_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_STBC_EN … static inline void SET_CMC_TBL_CSI_STBC_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_LDPC_EN … static inline void SET_CMC_TBL_CSI_LDPC_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_PARA_EN … static inline void SET_CMC_TBL_CSI_PARA_EN(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_FIX_RATE … static inline void SET_CMC_TBL_CSI_FIX_RATE(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_GI_LTF … static inline void SET_CMC_TBL_CSI_GI_LTF(void *table, u32 val) { … } static inline void SET_CMC_TBL_NOMINAL_PKT_PADDING160(void *table, u32 val) { … } #define SET_CMC_TBL_MASK_CSI_BW … static inline void SET_CMC_TBL_CSI_BW(void *table, u32 val) { … } struct rtw89_h2c_cctlinfo_ud_g7 { … } __packed; #define CCTLINFO_G7_C0_MACID … #define CCTLINFO_G7_C0_OP … #define CCTLINFO_G7_W0_DATARATE … #define CCTLINFO_G7_W0_DATA_GI_LTF … #define CCTLINFO_G7_W0_TRYRATE … #define CCTLINFO_G7_W0_ARFR_CTRL … #define CCTLINFO_G7_W0_DIS_HE1SS_STBC … #define CCTLINFO_G7_W0_ACQ_RPT_EN … #define CCTLINFO_G7_W0_MGQ_RPT_EN … #define CCTLINFO_G7_W0_ULQ_RPT_EN … #define CCTLINFO_G7_W0_TWTQ_RPT_EN … #define CCTLINFO_G7_W0_FORCE_TXOP … #define CCTLINFO_G7_W0_DISRTSFB … #define CCTLINFO_G7_W0_DISDATAFB … #define CCTLINFO_G7_W0_NSTR_EN … #define CCTLINFO_G7_W0_AMPDU_DENSITY … #define CCTLINFO_G7_W0_ALL … #define CCTLINFO_G7_W1_DATA_RTY_LOWEST_RATE … #define CCTLINFO_G7_W1_RTS_TXCNT_LMT … #define CCTLINFO_G7_W1_RTSRATE … #define CCTLINFO_G7_W1_RTS_RTY_LOWEST_RATE … #define CCTLINFO_G7_W1_ALL … #define CCTLINFO_G7_W2_DATA_TX_CNT_LMT … #define CCTLINFO_G7_W2_DATA_TXCNT_LMT_SEL … #define CCTLINFO_G7_W2_MAX_AGG_NUM_SEL … #define CCTLINFO_G7_W2_RTS_EN … #define CCTLINFO_G7_W2_CTS2SELF_EN … #define CCTLINFO_G7_W2_CCA_RTS … #define CCTLINFO_G7_W2_HW_RTS_EN … #define CCTLINFO_G7_W2_RTS_DROP_DATA_MODE … #define CCTLINFO_G7_W2_PRELD_EN … #define CCTLINFO_G7_W2_AMPDU_MAX_LEN … #define CCTLINFO_G7_W2_UL_MU_DIS … #define CCTLINFO_G7_W2_AMPDU_MAX_TIME … #define CCTLINFO_G7_W2_ALL … #define CCTLINFO_G7_W3_MAX_AGG_NUM … #define CCTLINFO_G7_W3_DATA_BW … #define CCTLINFO_G7_W3_DATA_BW_ER … #define CCTLINFO_G7_W3_BA_BMAP … #define CCTLINFO_G7_W3_VCS_STBC … #define CCTLINFO_G7_W3_VO_LFTIME_SEL … #define CCTLINFO_G7_W3_VI_LFTIME_SEL … #define CCTLINFO_G7_W3_BE_LFTIME_SEL … #define CCTLINFO_G7_W3_BK_LFTIME_SEL … #define CCTLINFO_G7_W3_AMPDU_TIME_SEL … #define CCTLINFO_G7_W3_AMPDU_LEN_SEL … #define CCTLINFO_G7_W3_RTS_TXCNT_LMT_SEL … #define CCTLINFO_G7_W3_LSIG_TXOP_EN … #define CCTLINFO_G7_W3_ALL … #define CCTLINFO_G7_W4_MULTI_PORT_ID … #define CCTLINFO_G7_W4_BYPASS_PUNC … #define CCTLINFO_G7_W4_MBSSID … #define CCTLINFO_G7_W4_DATA_DCM … #define CCTLINFO_G7_W4_DATA_ER … #define CCTLINFO_G7_W4_DATA_LDPC … #define CCTLINFO_G7_W4_DATA_STBC … #define CCTLINFO_G7_W4_A_CTRL_BQR … #define CCTLINFO_G7_W4_A_CTRL_BSR … #define CCTLINFO_G7_W4_A_CTRL_CAS … #define CCTLINFO_G7_W4_ACT_SUBCH_CBW … #define CCTLINFO_G7_W4_ALL … #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING0 … #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING1 … #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING2 … #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING3 … #define CCTLINFO_G7_W5_NOMINAL_PKT_PADDING4 … #define CCTLINFO_G7_W5_SR_RATE … #define CCTLINFO_G7_W5_TID_DISABLE … #define CCTLINFO_G7_W5_ADDR_CAM_INDEX … #define CCTLINFO_G7_W5_ALL … #define CCTLINFO_G7_W6_AID12_PAID … #define CCTLINFO_G7_W6_RESP_REF_RATE … #define CCTLINFO_G7_W6_ULDL … #define CCTLINFO_G7_W6_ALL … #define CCTLINFO_G7_W7_NC … #define CCTLINFO_G7_W7_NR … #define CCTLINFO_G7_W7_NG … #define CCTLINFO_G7_W7_CB … #define CCTLINFO_G7_W7_CS … #define CCTLINFO_G7_W7_CSI_STBC_EN … #define CCTLINFO_G7_W7_CSI_LDPC_EN … #define CCTLINFO_G7_W7_CSI_PARA_EN … #define CCTLINFO_G7_W7_CSI_FIX_RATE … #define CCTLINFO_G7_W7_CSI_BW … #define CCTLINFO_G7_W7_ALL … #define CCTLINFO_G7_W8_ALL_ACK_SUPPORT … #define CCTLINFO_G7_W8_BSR_QUEUE_SIZE_FORMAT … #define CCTLINFO_G7_W8_BSR_OM_UPD_EN … #define CCTLINFO_G7_W8_MACID_FWD_IDC … #define CCTLINFO_G7_W8_AZ_SEC_EN … #define CCTLINFO_G7_W8_CSI_SEC_EN … #define CCTLINFO_G7_W8_FIX_UL_ADDRCAM_IDX … #define CCTLINFO_G7_W8_CTRL_CNT_VLD … #define CCTLINFO_G7_W8_CTRL_CNT … #define CCTLINFO_G7_W8_RESP_SEC_TYPE … #define CCTLINFO_G7_W8_ALL … /* W9~13 are reserved */ #define CCTLINFO_G7_W14_VO_CURR_RATE … #define CCTLINFO_G7_W14_VI_CURR_RATE … #define CCTLINFO_G7_W14_BE_CURR_RATE_L … #define CCTLINFO_G7_W14_ALL … #define CCTLINFO_G7_W15_BE_CURR_RATE_H … #define CCTLINFO_G7_W15_BK_CURR_RATE … #define CCTLINFO_G7_W15_MGNT_CURR_RATE … #define CCTLINFO_G7_W15_ALL … struct rtw89_h2c_bcn_upd { … } __packed; #define RTW89_H2C_BCN_UPD_W0_PORT … #define RTW89_H2C_BCN_UPD_W0_MBSSID … #define RTW89_H2C_BCN_UPD_W0_BAND … #define RTW89_H2C_BCN_UPD_W0_GRP_IE_OFST … #define RTW89_H2C_BCN_UPD_W1_MACID … #define RTW89_H2C_BCN_UPD_W1_SSN_SEL … #define RTW89_H2C_BCN_UPD_W1_SSN_MODE … #define RTW89_H2C_BCN_UPD_W1_RATE … #define RTW89_H2C_BCN_UPD_W1_TXPWR … #define RTW89_H2C_BCN_UPD_W2_TXINFO_CTRL_EN … #define RTW89_H2C_BCN_UPD_W2_NTX_PATH_EN … #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_A … #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_B … #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_C … #define RTW89_H2C_BCN_UPD_W2_PATH_MAP_D … #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_A … #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_B … #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_C … #define RTW89_H2C_BCN_UPD_W2_PATH_ANTSEL_D … #define RTW89_H2C_BCN_UPD_W2_CSA_OFST … struct rtw89_h2c_bcn_upd_be { … } __packed; #define RTW89_H2C_BCN_UPD_BE_W0_PORT … #define RTW89_H2C_BCN_UPD_BE_W0_MBSSID … #define RTW89_H2C_BCN_UPD_BE_W0_BAND … #define RTW89_H2C_BCN_UPD_BE_W0_GRP_IE_OFST … #define RTW89_H2C_BCN_UPD_BE_W1_MACID … #define RTW89_H2C_BCN_UPD_BE_W1_SSN_SEL … #define RTW89_H2C_BCN_UPD_BE_W1_SSN_MODE … #define RTW89_H2C_BCN_UPD_BE_W1_RATE … #define RTW89_H2C_BCN_UPD_BE_W1_TXPWR … #define RTW89_H2C_BCN_UPD_BE_W1_MACID_EXT … #define RTW89_H2C_BCN_UPD_BE_W2_TXINFO_CTRL_EN … #define RTW89_H2C_BCN_UPD_BE_W2_NTX_PATH_EN … #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_A … #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_B … #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_C … #define RTW89_H2C_BCN_UPD_BE_W2_PATH_MAP_D … #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_A … #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_B … #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_C … #define RTW89_H2C_BCN_UPD_BE_W2_ANTSEL_D … #define RTW89_H2C_BCN_UPD_BE_W2_CSA_OFST … #define RTW89_H2C_BCN_UPD_BE_W3_MLIE_CSA_OFST … #define RTW89_H2C_BCN_UPD_BE_W3_CRITICAL_UPD_FLAG_OFST … #define RTW89_H2C_BCN_UPD_BE_W4_VAP1_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W4_VAP2_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W5_VAP3_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W5_VAP4_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W6_VAP5_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W6_VAP6_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W7_VAP7_DTIM_CNT_OFST … #define RTW89_H2C_BCN_UPD_BE_W7_ECSA_OFST … #define RTW89_H2C_BCN_UPD_BE_W7_PROTECTION_KEY_ID … static inline void SET_FWROLE_MAINTAIN_MACID(void *h2c, u32 val) { … } static inline void SET_FWROLE_MAINTAIN_SELF_ROLE(void *h2c, u32 val) { … } static inline void SET_FWROLE_MAINTAIN_UPD_MODE(void *h2c, u32 val) { … } static inline void SET_FWROLE_MAINTAIN_WIFI_ROLE(void *h2c, u32 val) { … } enum rtw89_fw_sta_type { … }; struct rtw89_h2c_join { … } __packed; struct rtw89_h2c_join_v1 { … } __packed; #define RTW89_H2C_JOININFO_W0_MACID … #define RTW89_H2C_JOININFO_W0_OP … #define RTW89_H2C_JOININFO_W0_BAND … #define RTW89_H2C_JOININFO_W0_WMM … #define RTW89_H2C_JOININFO_W0_TGR … #define RTW89_H2C_JOININFO_W0_ISHESTA … #define RTW89_H2C_JOININFO_W0_DLBW … #define RTW89_H2C_JOININFO_W0_TF_MAC_PAD … #define RTW89_H2C_JOININFO_W0_DL_T_PE … #define RTW89_H2C_JOININFO_W0_PORT_ID … #define RTW89_H2C_JOININFO_W0_NET_TYPE … #define RTW89_H2C_JOININFO_W0_WIFI_ROLE … #define RTW89_H2C_JOININFO_W0_SELF_ROLE … #define RTW89_H2C_JOININFO_W1_STA_TYPE … #define RTW89_H2C_JOININFO_W1_IS_MLD … #define RTW89_H2C_JOININFO_W1_MAIN_MACID … #define RTW89_H2C_JOININFO_W1_MLO_MODE … #define RTW89_H2C_JOININFO_W1_EMLSR_CAB … #define RTW89_H2C_JOININFO_W1_NSTR_EN … #define RTW89_H2C_JOININFO_W1_INIT_PWR_STATE … #define RTW89_H2C_JOININFO_W1_EMLSR_PADDING … #define RTW89_H2C_JOININFO_W1_EMLSR_TRANS_DELAY … #define RTW89_H2C_JOININFO_W2_MACID_EXT … #define RTW89_H2C_JOININFO_W2_MAIN_MACID_EXT … struct rtw89_h2c_notify_dbcc { … } __packed; #define RTW89_H2C_NOTIFY_DBCC_EN … static inline void SET_GENERAL_PKT_MACID(void *h2c, u32 val) { … } static inline void SET_GENERAL_PKT_PROBRSP_ID(void *h2c, u32 val) { … } static inline void SET_GENERAL_PKT_PSPOLL_ID(void *h2c, u32 val) { … } static inline void SET_GENERAL_PKT_NULL_ID(void *h2c, u32 val) { … } static inline void SET_GENERAL_PKT_QOS_NULL_ID(void *h2c, u32 val) { … } static inline void SET_GENERAL_PKT_CTS2SELF_ID(void *h2c, u32 val) { … } static inline void SET_LOG_CFG_LEVEL(void *h2c, u32 val) { … } static inline void SET_LOG_CFG_PATH(void *h2c, u32 val) { … } static inline void SET_LOG_CFG_COMP(void *h2c, u32 val) { … } static inline void SET_LOG_CFG_COMP_EXT(void *h2c, u32 val) { … } struct rtw89_h2c_ba_cam { … } __packed; #define RTW89_H2C_BA_CAM_W0_VALID … #define RTW89_H2C_BA_CAM_W0_INIT_REQ … #define RTW89_H2C_BA_CAM_W0_ENTRY_IDX … #define RTW89_H2C_BA_CAM_W0_TID … #define RTW89_H2C_BA_CAM_W0_MACID … #define RTW89_H2C_BA_CAM_W0_BMAP_SIZE … #define RTW89_H2C_BA_CAM_W0_SSN … #define RTW89_H2C_BA_CAM_W1_UID … #define RTW89_H2C_BA_CAM_W1_STD_EN … #define RTW89_H2C_BA_CAM_W1_BAND … #define RTW89_H2C_BA_CAM_W1_ENTRY_IDX_V1 … struct rtw89_h2c_ba_cam_v1 { … } __packed; #define RTW89_H2C_BA_CAM_V1_W0_VALID … #define RTW89_H2C_BA_CAM_V1_W0_INIT_REQ … #define RTW89_H2C_BA_CAM_V1_W0_TID_MASK … #define RTW89_H2C_BA_CAM_V1_W0_MACID_MASK … #define RTW89_H2C_BA_CAM_V1_W0_BMAP_SIZE_MASK … #define RTW89_H2C_BA_CAM_V1_W0_SSN_MASK … #define RTW89_H2C_BA_CAM_V1_W1_UID_VALUE_MASK … #define RTW89_H2C_BA_CAM_V1_W1_STD_ENTRY_EN … #define RTW89_H2C_BA_CAM_V1_W1_BAND_SEL … #define RTW89_H2C_BA_CAM_V1_W1_MLD_EN … #define RTW89_H2C_BA_CAM_V1_W1_ENTRY_IDX_MASK … struct rtw89_h2c_ba_cam_init { … } __packed; #define RTW89_H2C_BA_CAM_INIT_USERS_MASK … #define RTW89_H2C_BA_CAM_INIT_OFFSET_MASK … #define RTW89_H2C_BA_CAM_INIT_BAND_SEL … static inline void SET_LPS_PARM_MACID(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_PSMODE(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_RLBM(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_SMARTPS(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_AWAKEINTERVAL(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_VOUAPSD(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_VIUAPSD(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_BEUAPSD(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_BKUAPSD(void *h2c, u32 val) { … } static inline void SET_LPS_PARM_LASTRPWM(void *h2c, u32 val) { … } struct rtw89_h2c_lps_ch_info { … } __packed; static inline void RTW89_SET_FWCMD_CPU_EXCEPTION_TYPE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_SEL(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_BAND(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_PORT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MBSSID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_ROLE_A_INFO_TF_TRS(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_0(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_1(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_2(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PKT_DROP_MACID_BAND_SEL_3(void *cmd, u32 val) { … } static inline void RTW89_SET_KEEP_ALIVE_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_KEEP_ALIVE_PKT_NULL_ID(void *h2c, u32 val) { … } static inline void RTW89_SET_KEEP_ALIVE_PERIOD(void *h2c, u32 val) { … } static inline void RTW89_SET_KEEP_ALIVE_MACID(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_EN(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_DISCONNECT(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_MAC_ID(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_CHECK_PERIOD(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_TRY_PKT_COUNT(void *h2c, u32 val) { … } static inline void RTW89_SET_DISCONNECT_DETECT_TRYOK_BCNFAIL_COUNT_LIMIT(void *h2c, u32 val) { … } struct rtw89_h2c_wow_global { … } __packed; #define RTW89_H2C_WOW_GLOBAL_W0_ENABLE … #define RTW89_H2C_WOW_GLOBAL_W0_DROP_ALL_PKT … #define RTW89_H2C_WOW_GLOBAL_W0_RX_PARSE_AFTER_WAKE … #define RTW89_H2C_WOW_GLOBAL_W0_WAKE_BAR_PULLED … #define RTW89_H2C_WOW_GLOBAL_W0_MAC_ID … #define RTW89_H2C_WOW_GLOBAL_W0_PAIRWISE_SEC_ALGO … #define RTW89_H2C_WOW_GLOBAL_W0_GROUP_SEC_ALGO … #define RTW89_MAX_SUPPORT_NL_NUM … struct rtw89_h2c_cfg_nlo { … } __packed; #define RTW89_H2C_NLO_W0_ENABLE … #define RTW89_H2C_NLO_W0_IGNORE_CIPHER … #define RTW89_H2C_NLO_W0_MACID … static inline void RTW89_SET_WOW_WAKEUP_CTRL_PATTERN_MATCH_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAGIC_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_HW_UNICAST_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_FW_UNICAST_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_DEAUTH_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_REKEYP_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_EAP_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_ALL_DATA_ENABLE(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_WAKEUP_CTRL_MAC_ID(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_R_W(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_IDX(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_WKFM1(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_WKFM2(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_WKFM3(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_WKFM4(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_CRC(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_NEGATIVE_PATTERN_MATCH(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_SKIP_MAC_HDR(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_UC(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_MC(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_BC(void *h2c, u32 val) { … } static inline void RTW89_SET_WOW_CAM_UPD_VALID(void *h2c, u32 val) { … } struct rtw89_h2c_wow_gtk_ofld { … } __packed; #define RTW89_H2C_WOW_GTK_OFLD_W0_EN … #define RTW89_H2C_WOW_GTK_OFLD_W0_TKIP_EN … #define RTW89_H2C_WOW_GTK_OFLD_W0_IEEE80211W_EN … #define RTW89_H2C_WOW_GTK_OFLD_W0_PAIRWISE_WAKEUP … #define RTW89_H2C_WOW_GTK_OFLD_W0_NOREKEY_WAKEUP … #define RTW89_H2C_WOW_GTK_OFLD_W0_MAC_ID … #define RTW89_H2C_WOW_GTK_OFLD_W0_GTK_RSP_ID … #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_SA_QUERY_ID … #define RTW89_H2C_WOW_GTK_OFLD_W1_PMF_BIP_SEC_ALGO … #define RTW89_H2C_WOW_GTK_OFLD_W1_ALGO_AKM_SUIT … struct rtw89_h2c_arp_offload { … } __packed; #define RTW89_H2C_ARP_OFFLOAD_W0_ENABLE … #define RTW89_H2C_ARP_OFFLOAD_W0_ACTION … #define RTW89_H2C_ARP_OFFLOAD_W0_MACID … #define RTW89_H2C_ARP_OFFLOAD_W0_PKT_ID … #define RTW89_H2C_ARP_OFFLOAD_W1_CONTENT … enum rtw89_btc_btf_h2c_class { … }; enum rtw89_btc_btf_set { … }; enum rtw89_btc_cxdrvinfo { … }; enum rtw89_scan_mode { … }; enum rtw89_scan_type { … }; static inline void RTW89_SET_FWCMD_CXHDR_TYPE(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXHDR_LEN(void *cmd, u8 val) { … } struct rtw89_h2c_cxhdr { … } __packed; struct rtw89_h2c_cxhdr_v7 { … } __packed; struct rtw89_h2c_cxctrl_v7 { … } __packed; #define H2C_LEN_CXDRVHDR … #define H2C_LEN_CXDRVHDR_V7 … struct rtw89_btc_wl_role_info_v7_u8 { … } __packed; struct rtw89_btc_wl_role_info_v7_u32 { … } __packed; struct rtw89_h2c_cxrole_v7 { … } __packed; struct rtw89_btc_wl_role_info_v8_u8 { … } __packed; struct rtw89_btc_wl_role_info_v8_u32 { … } __packed; struct rtw89_h2c_cxrole_v8 { … } __packed; struct rtw89_h2c_cxinit { … } __packed; #define RTW89_H2C_CXINIT_ANT_INFO_POS … #define RTW89_H2C_CXINIT_ANT_INFO_DIVERSITY … #define RTW89_H2C_CXINIT_ANT_INFO_BTG_POS … #define RTW89_H2C_CXINIT_ANT_INFO_STREAM_CNT … #define RTW89_H2C_CXINIT_MOD_INFO_BT_SOLO … #define RTW89_H2C_CXINIT_MOD_INFO_BT_POS … #define RTW89_H2C_CXINIT_MOD_INFO_SW_TYPE … #define RTW89_H2C_CXINIT_MOD_INFO_WA_TYPE … #define RTW89_H2C_CXINIT_INFO_WL_ONLY … #define RTW89_H2C_CXINIT_INFO_WL_INITOK … #define RTW89_H2C_CXINIT_INFO_DBCC_EN … #define RTW89_H2C_CXINIT_INFO_CX_OTHER … #define RTW89_H2C_CXINIT_INFO_BT_ONLY … struct rtw89_h2c_cxinit_v7 { … } __packed; static inline void RTW89_SET_FWCMD_CXROLE_CONNECT_CNT(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NONE(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_STA(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_AP(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_VAP(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_ADHOC_MASTER(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MESH(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_MONITOR(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_DEV(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GC(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_P2P_GO(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ROLE_NAN(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_LVL(void *cmd, u16 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_LVL(void *cmd, u16 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_TX_RATE(void *cmd, u16 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_RX_RATE(void *cmd, u16 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR(void *cmd, u32 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CONNECTED_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_PID_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_PHY_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_BAND_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CLIENT_PS_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_BW_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_ROLE_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_CH_V2(void *cmd, u8 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_ACT_NOA_DUR_V2(void *cmd, u32 val, int n, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_MROLE_TYPE(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_MROLE_NOA(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_DBCC_EN(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_DBCC_CHG(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_DBCC_2G_PHY(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXROLE_LINK_MODE_CHG(void *cmd, u32 val, u8 offset) { … } static inline void RTW89_SET_FWCMD_CXCTRL_MANUAL(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXCTRL_IGNORE_BT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXCTRL_ALWAYS_FREERUN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXCTRL_TRACE_STEP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_TXLV(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RXLV(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_WLRSSI(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_BTRSSI(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_TXPWR(void *cmd, s8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RXGAIN(void *cmd, s8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_BTTXPWR(void *cmd, s8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_BTRXGAIN(void *cmd, s8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_CN(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_NHM(void *cmd, s8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_BTPROFILE(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RSVD2(void *cmd, u8 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_TXRATE(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RXRATE(void *cmd, u16 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_TXTP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RXTP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXTRX_RXERRRA(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXRFK_STATE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXRFK_PATH_MAP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXRFK_PHY_MAP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXRFK_BAND(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_CXRFK_TYPE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_IDX(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_OP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_PACKET_OFLD_PKT_LENGTH(void *cmd, u32 val) { … } struct rtw89_h2c_chinfo_elem { … } __packed; #define RTW89_H2C_CHINFO_W0_PERIOD … #define RTW89_H2C_CHINFO_W0_DWELL … #define RTW89_H2C_CHINFO_W0_CENTER_CH … #define RTW89_H2C_CHINFO_W0_PRI_CH … #define RTW89_H2C_CHINFO_W1_BW … #define RTW89_H2C_CHINFO_W1_ACTION … #define RTW89_H2C_CHINFO_W1_NUM_PKT … #define RTW89_H2C_CHINFO_W1_TX … #define RTW89_H2C_CHINFO_W1_PAUSE_DATA … #define RTW89_H2C_CHINFO_W1_BAND … #define RTW89_H2C_CHINFO_W1_PKT_ID … #define RTW89_H2C_CHINFO_W1_DFS … #define RTW89_H2C_CHINFO_W1_TX_NULL … #define RTW89_H2C_CHINFO_W1_RANDOM … #define RTW89_H2C_CHINFO_W1_CFG_TX … #define RTW89_H2C_CHINFO_W2_PKT0 … #define RTW89_H2C_CHINFO_W2_PKT1 … #define RTW89_H2C_CHINFO_W2_PKT2 … #define RTW89_H2C_CHINFO_W2_PKT3 … #define RTW89_H2C_CHINFO_W3_PKT4 … #define RTW89_H2C_CHINFO_W3_PKT5 … #define RTW89_H2C_CHINFO_W3_PKT6 … #define RTW89_H2C_CHINFO_W3_PKT7 … #define RTW89_H2C_CHINFO_W4_POWER_IDX … struct rtw89_h2c_chinfo_elem_be { … } __packed; #define RTW89_H2C_CHINFO_BE_W0_PERIOD … #define RTW89_H2C_CHINFO_BE_W0_DWELL … #define RTW89_H2C_CHINFO_BE_W0_CENTER_CH … #define RTW89_H2C_CHINFO_BE_W0_PRI_CH … #define RTW89_H2C_CHINFO_BE_W1_BW … #define RTW89_H2C_CHINFO_BE_W1_CH_BAND … #define RTW89_H2C_CHINFO_BE_W1_DFS … #define RTW89_H2C_CHINFO_BE_W1_PAUSE_DATA … #define RTW89_H2C_CHINFO_BE_W1_TX_NULL … #define RTW89_H2C_CHINFO_BE_W1_RANDOM … #define RTW89_H2C_CHINFO_BE_W1_NOTIFY … #define RTW89_H2C_CHINFO_BE_W1_PROBE … #define RTW89_H2C_CHINFO_BE_W1_EARLY_LEAVE_CRIT … #define RTW89_H2C_CHINFO_BE_W1_CHKPT_TIMER … #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TIME … #define RTW89_H2C_CHINFO_BE_W2_EARLY_LEAVE_TH … #define RTW89_H2C_CHINFO_BE_W2_TX_PKT_CTRL … #define RTW89_H2C_CHINFO_BE_W3_PKT0 … #define RTW89_H2C_CHINFO_BE_W3_PKT1 … #define RTW89_H2C_CHINFO_BE_W3_PKT2 … #define RTW89_H2C_CHINFO_BE_W3_PKT3 … #define RTW89_H2C_CHINFO_BE_W4_PKT4 … #define RTW89_H2C_CHINFO_BE_W4_PKT5 … #define RTW89_H2C_CHINFO_BE_W4_PKT6 … #define RTW89_H2C_CHINFO_BE_W4_PKT7 … #define RTW89_H2C_CHINFO_BE_W5_SW_DEF … #define RTW89_H2C_CHINFO_BE_W5_FW_PROBE0_SSIDS … #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_SHORTSSIDS … #define RTW89_H2C_CHINFO_BE_W6_FW_PROBE0_BSSIDS … struct rtw89_h2c_chinfo { … } __packed; #define RTW89_H2C_CHINFO_ARG_MAC_IDX_MASK … #define RTW89_H2C_CHINFO_ARG_APPEND_MASK … struct rtw89_h2c_scanofld { … } __packed; #define RTW89_H2C_SCANOFLD_W0_MACID … #define RTW89_H2C_SCANOFLD_W0_NORM_CY … #define RTW89_H2C_SCANOFLD_W0_PORT_ID … #define RTW89_H2C_SCANOFLD_W0_BAND … #define RTW89_H2C_SCANOFLD_W0_OPERATION … #define RTW89_H2C_SCANOFLD_W0_TARGET_CH_BAND … #define RTW89_H2C_SCANOFLD_W1_NOTIFY_END … #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_MODE … #define RTW89_H2C_SCANOFLD_W1_START_MODE … #define RTW89_H2C_SCANOFLD_W1_SCAN_TYPE … #define RTW89_H2C_SCANOFLD_W1_TARGET_CH_BW … #define RTW89_H2C_SCANOFLD_W1_TARGET_PRI_CH … #define RTW89_H2C_SCANOFLD_W1_TARGET_CENTRAL_CH … #define RTW89_H2C_SCANOFLD_W1_PROBE_REQ_PKT_ID … #define RTW89_H2C_SCANOFLD_W2_NORM_PD … #define RTW89_H2C_SCANOFLD_W2_SLOW_PD … #define RTW89_H2C_SCANOFLD_W3_TSF_HIGH … #define RTW89_H2C_SCANOFLD_W4_TSF_LOW … struct rtw89_h2c_scanofld_be_macc_role { … } __packed; #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_BAND … #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_PORT … #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_MACID … #define RTW89_H2C_SCANOFLD_BE_MACC_ROLE_W0_OPCH_END … struct rtw89_h2c_scanofld_be_opch { … } __packed; #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_MACID … #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_BAND … #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_PORT … #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY … #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_TXNULL … #define RTW89_H2C_SCANOFLD_BE_OPCH_W0_POLICY_VAL … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_DURATION … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CH_BAND … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_BW … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_NOTIFY … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_PRI_CH … #define RTW89_H2C_SCANOFLD_BE_OPCH_W1_CENTRAL_CH … #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_PKTS_CTRL … #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SW_DEF … #define RTW89_H2C_SCANOFLD_BE_OPCH_W2_SS … #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT0 … #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT1 … #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT2 … #define RTW89_H2C_SCANOFLD_BE_OPCH_W3_PKT3 … struct rtw89_h2c_scanofld_be { … } __packed; #define RTW89_H2C_SCANOFLD_BE_W0_OP … #define RTW89_H2C_SCANOFLD_BE_W0_SCAN_MODE … #define RTW89_H2C_SCANOFLD_BE_W0_REPEAT … #define RTW89_H2C_SCANOFLD_BE_W0_NOTIFY_END … #define RTW89_H2C_SCANOFLD_BE_W0_LEARN_CH … #define RTW89_H2C_SCANOFLD_BE_W0_MACID … #define RTW89_H2C_SCANOFLD_BE_W0_PORT … #define RTW89_H2C_SCANOFLD_BE_W0_BAND … #define RTW89_H2C_SCANOFLD_BE_W0_PROBE_WITH_RATE … #define RTW89_H2C_SCANOFLD_BE_W1_NUM_MACC_ROLE … #define RTW89_H2C_SCANOFLD_BE_W1_NUM_OP … #define RTW89_H2C_SCANOFLD_BE_W1_NORM_PD … #define RTW89_H2C_SCANOFLD_BE_W2_SLOW_PD … #define RTW89_H2C_SCANOFLD_BE_W2_NORM_CY … #define RTW89_H2C_SCANOFLD_BE_W2_OPCH_END … #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SSID … #define RTW89_H2C_SCANOFLD_BE_W3_NUM_SHORT_SSID … #define RTW89_H2C_SCANOFLD_BE_W3_NUM_BSSID … #define RTW89_H2C_SCANOFLD_BE_W3_PROBEID … #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_5G … #define RTW89_H2C_SCANOFLD_BE_W4_PROBE_6G … #define RTW89_H2C_SCANOFLD_BE_W4_DELAY_START … #define RTW89_H2C_SCANOFLD_BE_W5_MLO_MODE … #define RTW89_H2C_SCANOFLD_BE_W6_CHAN_PROHIB_LOW … #define RTW89_H2C_SCANOFLD_BE_W7_CHAN_PROHIB_HIGH … #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_2GHZ … #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_5GHZ … #define RTW89_H2C_SCANOFLD_BE_W8_PROBE_RATE_6GHZ … #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_CFG … #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_MACC … #define RTW89_H2C_SCANOFLD_BE_W9_SIZE_OP … struct rtw89_h2c_fwips { … } __packed; #define RTW89_H2C_FW_IPS_W0_MACID … #define RTW89_H2C_FW_IPS_W0_ENABLE … static inline void RTW89_SET_FWCMD_P2P_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_P2P_P2PID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_P2P_NOAID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_P2P_ACT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_P2P_TYPE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_P2P_ALL_SLEP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_NOA_START_TIME(void *cmd, __le32 val) { … } static inline void RTW89_SET_FWCMD_NOA_INTERVAL(void *cmd, __le32 val) { … } static inline void RTW89_SET_FWCMD_NOA_DURATION(void *cmd, __le32 val) { … } static inline void RTW89_SET_FWCMD_NOA_COUNT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_NOA_CTWINDOW(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_TSF32_TOGL_BAND(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_TSF32_TOGL_EN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_TSF32_TOGL_PORT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_TSF32_TOGL_EARLY(void *cmd, u32 val) { … } enum rtw89_fw_mcc_c2h_rpt_cfg { … }; struct rtw89_fw_mcc_add_req { … }; static inline void RTW89_SET_FWCMD_ADD_MCC_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG0(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_CENTRAL_CH_SEG1(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_PRIMARY_CH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_BANDWIDTH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_C2H_RPT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_TX_NULL(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_DIS_SW_RETRY(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_IN_CURR_CH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_SW_RETRY_COUNT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_TX_NULL_EARLY(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_BTC_IN_2G(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_PTA_EN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_RFK_BY_PASS(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_CH_BAND_TYPE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_DURATION(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_EN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_NUM(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_ADD_MCC_COURTESY_TARGET(void *cmd, u32 val) { … } enum rtw89_fw_mcc_old_group_actions { … }; struct rtw89_fw_mcc_start_req { … }; static inline void RTW89_SET_FWCMD_START_MCC_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_BTC_IN_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP_ACTION(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_OLD_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_CNT(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_NOTIFY_RXDBG_EN(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_TSF_LOW(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_START_MCC_TSF_HIGH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_STOP_MCC_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_STOP_MCC_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_STOP_MCC_PREV_GROUPS(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_DEL_MCC_GROUP_PREV_GROUPS(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_RESET_MCC_GROUP_GROUP(void *cmd, u32 val) { … } struct rtw89_fw_mcc_tsf_req { … }; static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_X(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_REQ_TSF_MACID_Y(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP_LENGTH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_MACID_BITMAP_BITMAP(void *cmd, u8 *bitmap, u8 len) { … } static inline void RTW89_SET_FWCMD_MCC_SYNC_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_SOURCE(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SYNC_MACID_TARGET(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SYNC_SYNC_OFFSET(void *cmd, u32 val) { … } struct rtw89_fw_mcc_duration { … }; static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_BTC_IN_GROUP(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_MACID(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_X(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_MACID_Y(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_LOW(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_START_TSF_HIGH(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_X(void *cmd, u32 val) { … } static inline void RTW89_SET_FWCMD_MCC_SET_DURATION_DURATION_Y(void *cmd, u32 val) { … } enum rtw89_h2c_mrc_sch_types { … }; enum rtw89_h2c_mrc_role_types { … }; #define RTW89_MAC_MRC_MAX_ADD_SLOT_NUM … #define RTW89_MAC_MRC_MAX_ADD_ROLE_NUM_PER_SLOT … struct rtw89_fw_mrc_add_slot_arg { … }; struct rtw89_fw_mrc_add_arg { … }; struct rtw89_h2c_mrc_add_role { … } __packed; #define RTW89_H2C_MRC_ADD_ROLE_W0_MACID … #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_TYPE … #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_MASTER … #define RTW89_H2C_MRC_ADD_ROLE_W0_IS_ALT_ROLE … #define RTW89_H2C_MRC_ADD_ROLE_W0_TX_NULL_EN … #define RTW89_H2C_MRC_ADD_ROLE_W0_ROLE_ALT_EN … #define RTW89_H2C_MRC_ADD_ROLE_W1_CENTRAL_CH_SEG … #define RTW89_H2C_MRC_ADD_ROLE_W1_PRI_CH … #define RTW89_H2C_MRC_ADD_ROLE_W1_BW … #define RTW89_H2C_MRC_ADD_ROLE_W1_CH_BAND_TYPE … #define RTW89_H2C_MRC_ADD_ROLE_W1_RFK_BY_PASS … #define RTW89_H2C_MRC_ADD_ROLE_W1_CAN_BTC … #define RTW89_H2C_MRC_ADD_ROLE_W1_NULL_EARLY … #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_PERIOD … #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_TYPE … #define RTW89_H2C_MRC_ADD_ROLE_W2_ALT_ROLE_MACID … struct rtw89_h2c_mrc_add_slot { … } __packed; #define RTW89_H2C_MRC_ADD_SLOT_W0_DURATION … #define RTW89_H2C_MRC_ADD_SLOT_W0_COURTESY_EN … #define RTW89_H2C_MRC_ADD_SLOT_W0_ROLE_NUM … #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_PERIOD … #define RTW89_H2C_MRC_ADD_SLOT_W1_COURTESY_TARGET … struct rtw89_h2c_mrc_add { … } __packed; #define RTW89_H2C_MRC_ADD_W0_SCH_IDX … #define RTW89_H2C_MRC_ADD_W0_SCH_TYPE … #define RTW89_H2C_MRC_ADD_W0_SLOT_NUM … #define RTW89_H2C_MRC_ADD_W0_BTC_IN_SCH … enum rtw89_h2c_mrc_start_actions { … }; struct rtw89_fw_mrc_start_arg { … }; struct rtw89_h2c_mrc_start { … } __packed; #define RTW89_H2C_MRC_START_W0_SCH_IDX … #define RTW89_H2C_MRC_START_W0_OLD_SCH_IDX … #define RTW89_H2C_MRC_START_W0_ACTION … struct rtw89_h2c_mrc_del { … } __packed; #define RTW89_H2C_MRC_DEL_W0_SCH_IDX … #define RTW89_H2C_MRC_DEL_W0_DEL_ALL … #define RTW89_H2C_MRC_DEL_W0_STOP_ONLY … #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_EN … #define RTW89_H2C_MRC_DEL_W0_STOP_SLOT_IDX … #define RTW89_H2C_MRC_DEL_W0_SPECIFIC_ROLE_MACID … #define RTW89_MAC_MRC_MAX_REQ_TSF_NUM … struct rtw89_fw_mrc_req_tsf_arg { … }; struct rtw89_h2c_mrc_req_tsf { … } __packed; #define RTW89_H2C_MRC_REQ_TSF_INFO_BAND … #define RTW89_H2C_MRC_REQ_TSF_INFO_PORT … enum rtw89_h2c_mrc_upd_bitmap_actions { … }; struct rtw89_fw_mrc_upd_bitmap_arg { … }; struct rtw89_h2c_mrc_upd_bitmap { … } __packed; #define RTW89_H2C_MRC_UPD_BITMAP_W0_SCH_IDX … #define RTW89_H2C_MRC_UPD_BITMAP_W0_ACTION … #define RTW89_H2C_MRC_UPD_BITMAP_W0_MACID … #define RTW89_H2C_MRC_UPD_BITMAP_W1_CLIENT_MACID … struct rtw89_fw_mrc_sync_arg { … }; struct rtw89_h2c_mrc_sync { … } __packed; #define RTW89_H2C_MRC_SYNC_W0_SYNC_EN … #define RTW89_H2C_MRC_SYNC_W0_SRC_PORT … #define RTW89_H2C_MRC_SYNC_W0_SRC_BAND … #define RTW89_H2C_MRC_SYNC_W0_DEST_PORT … #define RTW89_H2C_MRC_SYNC_W0_DEST_BAND … #define RTW89_H2C_MRC_SYNC_W1_OFFSET … struct rtw89_fw_mrc_upd_duration_arg { … }; struct rtw89_h2c_mrc_upd_duration { … } __packed; #define RTW89_H2C_MRC_UPD_DURATION_W0_SCH_IDX … #define RTW89_H2C_MRC_UPD_DURATION_W0_SLOT_NUM … #define RTW89_H2C_MRC_UPD_DURATION_W0_BTC_IN_SCH … #define RTW89_H2C_MRC_UPD_DURATION_SLOT_SLOT_IDX … #define RTW89_H2C_MRC_UPD_DURATION_SLOT_DURATION … struct rtw89_h2c_wow_aoac { … } __packed; #define RTW89_C2H_HEADER_LEN … struct rtw89_c2h_hdr { … } __packed; #define RTW89_C2H_HDR_W0_CATEGORY … #define RTW89_C2H_HDR_W0_CLASS … #define RTW89_C2H_HDR_W0_FUNC … #define RTW89_C2H_HDR_W1_LEN … struct rtw89_fw_c2h_attr { … }; static inline struct rtw89_fw_c2h_attr *RTW89_SKB_C2H_CB(struct sk_buff *skb) { … } struct rtw89_c2h_done_ack { … } __packed; #define RTW89_C2H_DONE_ACK_W2_CAT … #define RTW89_C2H_DONE_ACK_W2_CLASS … #define RTW89_C2H_DONE_ACK_W2_FUNC … #define RTW89_C2H_DONE_ACK_W2_H2C_RETURN … #define RTW89_C2H_DONE_ACK_W2_H2C_SEQ … #define RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h) … #define RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h) … #define RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h) … #define RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h) … struct rtw89_fw_c2h_log_fmt { … } __packed; #define RTW89_C2H_FW_FORMATTED_LOG_MIN_LEN … #define RTW89_C2H_FW_LOG_FEATURE_PARA_INT … #define RTW89_C2H_FW_LOG_MAX_PARA_NUM … #define RTW89_C2H_FW_LOG_SIGNATURE … #define RTW89_C2H_FW_LOG_STR_BUF_SIZE … struct rtw89_c2h_mac_bcnfltr_rpt { … } __packed; #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID … #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE … #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT … #define RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA … struct rtw89_c2h_ra_rpt { … } __packed; #define RTW89_C2H_RA_RPT_W2_MACID … #define RTW89_C2H_RA_RPT_W2_RETRY_RATIO … #define RTW89_C2H_RA_RPT_W2_MCSNSS_B7 … #define RTW89_C2H_RA_RPT_W3_MCSNSS … #define RTW89_C2H_RA_RPT_W3_MD_SEL … #define RTW89_C2H_RA_RPT_W3_GILTF … #define RTW89_C2H_RA_RPT_W3_BW … #define RTW89_C2H_RA_RPT_W3_MD_SEL_B2 … #define RTW89_C2H_RA_RPT_W3_BW_B2 … /* For WiFi 6 chips: * VHT, HE, HT-old: [6:4]: NSS, [3:0]: MCS * HT-new: [6:5]: NA, [4:0]: MCS * For WiFi 7 chips (V1): * HT, VHT, HE, EHT: [7:5]: NSS, [4:0]: MCS */ #define RTW89_RA_RATE_MASK_NSS … #define RTW89_RA_RATE_MASK_MCS … #define RTW89_RA_RATE_MASK_NSS_V1 … #define RTW89_RA_RATE_MASK_MCS_V1 … #define RTW89_RA_RATE_MASK_HT_MCS … #define RTW89_MK_HT_RATE(nss, mcs) … #define RTW89_GET_MAC_C2H_PKTOFLD_ID(c2h) … #define RTW89_GET_MAC_C2H_PKTOFLD_OP(c2h) … #define RTW89_GET_MAC_C2H_PKTOFLD_LEN(c2h) … struct rtw89_c2h_scanofld { … } __packed; #define RTW89_C2H_SCANOFLD_W2_PRI_CH … #define RTW89_C2H_SCANOFLD_W2_RSN … #define RTW89_C2H_SCANOFLD_W2_STATUS … #define RTW89_C2H_SCANOFLD_W2_PERIOD … #define RTW89_C2H_SCANOFLD_W5_TX_FAIL … #define RTW89_C2H_SCANOFLD_W5_AIR_DENSITY … #define RTW89_C2H_SCANOFLD_W5_BAND … #define RTW89_C2H_SCANOFLD_W5_MAC_IDX … #define RTW89_C2H_SCANOFLD_W6_SW_DEF … #define RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD … #define RTW89_C2H_SCANOFLD_W6_FW_DEF … #define RTW89_C2H_SCANOFLD_W7_REPORT_TSF … #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h) … #define RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h) … #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h) … #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h) … #define RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h) … struct rtw89_mac_mcc_tsf_rpt { … }; static_assert(…); #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h) … #define RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h) … #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h) … #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h) … #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h) … #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h) … #define RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h) … struct rtw89_mac_mrc_tsf_rpt { … }; static_assert(…); struct rtw89_c2h_mrc_tsf_rpt_info { … } __packed; struct rtw89_c2h_mrc_tsf_rpt { … } __packed; #define RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM … struct rtw89_c2h_mrc_status_rpt { … } __packed; #define RTW89_C2H_MRC_STATUS_RPT_W2_STATUS … #define RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX … struct rtw89_c2h_pkt_ofld_rsp { … } __packed; #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID … #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP … #define RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN … struct rtw89_c2h_wow_aoac_report { … } __packed; #define RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX … struct rtw89_h2c_bcnfltr { … } __packed; #define RTW89_H2C_BCNFLTR_W0_MON_RSSI … #define RTW89_H2C_BCNFLTR_W0_MON_BCN … #define RTW89_H2C_BCNFLTR_W0_MON_EN … #define RTW89_H2C_BCNFLTR_W0_MODE … #define RTW89_H2C_BCNFLTR_W0_BCN_LOSS_CNT … #define RTW89_H2C_BCNFLTR_W0_RSSI_HYST … #define RTW89_H2C_BCNFLTR_W0_RSSI_THRESHOLD … #define RTW89_H2C_BCNFLTR_W0_MAC_ID … struct rtw89_h2c_ofld_rssi { … } __packed; #define RTW89_H2C_OFLD_RSSI_W0_MACID … #define RTW89_H2C_OFLD_RSSI_W0_NUM … #define RTW89_H2C_OFLD_RSSI_W1_VAL … struct rtw89_h2c_ofld { … } __packed; #define RTW89_H2C_OFLD_W0_MAC_ID … #define RTW89_H2C_OFLD_W0_TX_TP … #define RTW89_H2C_OFLD_W0_RX_TP … #define RTW89_MFW_SIG … struct rtw89_mfw_info { … } __packed; struct rtw89_mfw_hdr { … } __packed; struct rtw89_fw_logsuit_hdr { … } __packed; #define RTW89_FW_ELEMENT_ALIGN … enum rtw89_fw_element_id { … }; #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS_NO_6GHZ … #define BITS_OF_RTW89_TXPWR_FW_ELEMENTS … #define RTW89_AX_GEN_DEF_NEEDED_FW_ELEMENTS_NO_6GHZ … #define RTW89_BE_GEN_DEF_NEEDED_FW_ELEMENTS … struct __rtw89_fw_txpwr_element { … } __packed; enum rtw89_fw_txpwr_trk_type { … }; struct rtw89_fw_txpwr_track_cfg { … }; #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_6GHZ … #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_5GHZ … #define RTW89_DEFAULT_NEEDED_FW_TXPWR_TRK_2GHZ … struct rtw89_fw_element_hdr { … } __packed; struct fwcmd_hdr { … }; rtw89_compat_fw_hdr; static inline u32 rtw89_compat_fw_hdr_ver_code(const void *fw_buf) { … } static inline void rtw89_fw_get_filename(char *buf, size_t size, const char *fw_basename, int fw_format) { … } #define RTW89_H2C_RF_PAGE_SIZE … #define RTW89_H2C_RF_PAGE_NUM … struct rtw89_fw_h2c_rf_reg_info { … }; #define H2C_SEC_CAM_LEN … #define H2C_HEADER_LEN … #define H2C_HDR_CAT … #define H2C_HDR_CLASS … #define H2C_HDR_FUNC … #define H2C_HDR_DEL_TYPE … #define H2C_HDR_H2C_SEQ … #define H2C_HDR_TOTAL_LEN … #define H2C_HDR_REC_ACK … #define H2C_HDR_DONE_ACK … #define FWCMD_TYPE_H2C … #define H2C_CAT_TEST … /* CLASS 5 - FW STATUS TEST */ #define H2C_CL_FW_STATUS_TEST … #define H2C_FUNC_CPU_EXCEPTION … #define H2C_CAT_MAC … /* CLASS 0 - FW INFO */ #define H2C_CL_FW_INFO … #define H2C_FUNC_LOG_CFG … #define H2C_FUNC_MAC_GENERAL_PKT … /* CLASS 1 - WOW */ #define H2C_CL_MAC_WOW … enum rtw89_wow_h2c_func { … }; #define RTW89_WOW_WAIT_COND(tag, func) … #define RTW89_WOW_WAIT_COND_AOAC … /* CLASS 2 - PS */ #define H2C_CL_MAC_PS … enum rtw89_ps_h2c_func { … }; #define RTW89_PS_WAIT_COND(tag, func) … #define RTW89_PS_WAIT_COND_IPS_CFG … /* CLASS 3 - FW download */ #define H2C_CL_MAC_FWDL … #define H2C_FUNC_MAC_FWHDR_DL … /* CLASS 5 - Frame Exchange */ #define H2C_CL_MAC_FR_EXCHG … #define H2C_FUNC_MAC_CCTLINFO_UD … #define H2C_FUNC_MAC_BCN_UPD … #define H2C_FUNC_MAC_DCTLINFO_UD_V1 … #define H2C_FUNC_MAC_CCTLINFO_UD_V1 … #define H2C_FUNC_MAC_DCTLINFO_UD_V2 … #define H2C_FUNC_MAC_BCN_UPD_BE … #define H2C_FUNC_MAC_CCTLINFO_UD_G7 … /* CLASS 6 - Address CAM */ #define H2C_CL_MAC_ADDR_CAM_UPDATE … #define H2C_FUNC_MAC_ADDR_CAM_UPD … /* CLASS 8 - Media Status Report */ #define H2C_CL_MAC_MEDIA_RPT … #define H2C_FUNC_MAC_JOININFO … #define H2C_FUNC_MAC_FWROLE_MAINTAIN … #define H2C_FUNC_NOTIFY_DBCC … /* CLASS 9 - FW offload */ #define H2C_CL_MAC_FW_OFLD … enum rtw89_fw_ofld_h2c_func { … }; #define RTW89_FW_OFLD_WAIT_COND(tag, func) … #define RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op) … #define RTW89_SCANOFLD_WAIT_COND_ADD_CH … #define RTW89_SCANOFLD_WAIT_COND_START … #define RTW89_SCANOFLD_WAIT_COND_STOP … #define RTW89_SCANOFLD_BE_WAIT_COND_START … #define RTW89_SCANOFLD_BE_WAIT_COND_STOP … /* CLASS 10 - Security CAM */ #define H2C_CL_MAC_SEC_CAM … #define H2C_FUNC_MAC_SEC_UPD … /* CLASS 12 - BA CAM */ #define H2C_CL_BA_CAM … #define H2C_FUNC_MAC_BA_CAM … #define H2C_FUNC_MAC_BA_CAM_V1 … #define H2C_FUNC_MAC_BA_CAM_INIT … /* CLASS 14 - MCC */ #define H2C_CL_MCC … enum rtw89_mcc_h2c_func { … }; #define RTW89_MCC_WAIT_COND(group, func) … /* CLASS 24 - MRC */ #define H2C_CL_MRC … enum rtw89_mrc_h2c_func { … }; /* can consider MRC's sch_idx as MCC's group */ #define RTW89_MRC_WAIT_COND(sch_idx, func) … #define RTW89_MRC_WAIT_COND_REQ_TSF … #define H2C_CAT_OUTSRC … #define H2C_CL_OUTSRC_RA … #define H2C_FUNC_OUTSRC_RA_MACIDCFG … #define H2C_CL_OUTSRC_DM … #define H2C_FUNC_FW_LPS_CH_INFO … #define H2C_CL_OUTSRC_RF_REG_A … #define H2C_CL_OUTSRC_RF_REG_B … #define H2C_CL_OUTSRC_RF_FW_NOTIFY … #define H2C_FUNC_OUTSRC_RF_GET_MCCCH … #define H2C_CL_OUTSRC_RF_FW_RFK … enum rtw89_rfk_offload_h2c_func { … }; struct rtw89_fw_h2c_rf_get_mccch { … } __packed; #define NUM_OF_RTW89_FW_RFK_PATH … #define NUM_OF_RTW89_FW_RFK_TBL … struct rtw89_fw_h2c_rfk_pre_info_common { … } __packed; struct rtw89_fw_h2c_rfk_pre_info_v0 { … } __packed; struct rtw89_fw_h2c_rfk_pre_info { … } __packed; struct rtw89_h2c_rf_tssi { … } __packed; struct rtw89_h2c_rf_iqk { … } __packed; struct rtw89_h2c_rf_dpk { … } __packed; struct rtw89_h2c_rf_txgapk { … } __packed; struct rtw89_h2c_rf_dack { … } __packed; struct rtw89_h2c_rf_rxdck { … } __packed; enum rtw89_rf_log_type { … }; struct rtw89_c2h_rf_log_hdr { … } __packed; struct rtw89_c2h_rf_run_log { … } __packed; struct rtw89_c2h_rf_dpk_rpt_log { … } __packed; struct rtw89_c2h_rf_dack_rpt_log { … } __packed; struct rtw89_c2h_rf_rxdck_rpt_log { … } __packed; struct rtw89_c2h_rf_txgapk_rpt_log { … } __packed; struct rtw89_c2h_rfk_report { … } __packed; #define RTW89_FW_RSVD_PLE_SIZE … #define RTW89_FW_BACKTRACE_INFO_SIZE … #define RTW89_VALID_FW_BACKTRACE_SIZE(_size) … #define RTW89_FW_BACKTRACE_MAX_SIZE … #define RTW89_FW_BACKTRACE_KEY … #define FWDL_WAIT_CNT … int rtw89_fw_check_rdy(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type); int rtw89_fw_recognize(struct rtw89_dev *rtwdev); int rtw89_fw_recognize_elements(struct rtw89_dev *rtwdev); const struct firmware * rtw89_early_fw_feature_recognize(struct device *device, const struct rtw89_chip_info *chip, struct rtw89_fw_info *early_fw, int *used_fw_format); int rtw89_fw_download(struct rtw89_dev *rtwdev, enum rtw89_fw_type type, bool include_bb); void rtw89_load_firmware_work(struct work_struct *work); void rtw89_unload_firmware(struct rtw89_dev *rtwdev); int rtw89_wait_firmware_completion(struct rtw89_dev *rtwdev); int rtw89_fw_log_prepare(struct rtw89_dev *rtwdev); void rtw89_fw_log_dump(struct rtw89_dev *rtwdev, u8 *buf, u32 len); void rtw89_h2c_pkt_set_hdr(struct rtw89_dev *rtwdev, struct sk_buff *skb, u8 type, u8 cat, u8 class, u8 func, bool rack, bool dack, u32 len); int rtw89_fw_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_default_cmac_tbl_g7(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_default_dmac_tbl_v2(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_fw_h2c_assoc_cmac_tbl_g7(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_fw_h2c_ampdu_cmac_tbl_g7(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); int rtw89_fw_h2c_txtime_cmac_tbl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_txpath_cmac_tbl(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_update_beacon(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_update_beacon_be(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_cam(struct rtw89_dev *rtwdev, struct rtw89_vif *vif, struct rtw89_sta *rtwsta, const u8 *scan_mac_addr); int rtw89_fw_h2c_dctl_sec_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta); int rtw89_fw_h2c_dctl_sec_cam_v2(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta); void rtw89_fw_c2h_irqsafe(struct rtw89_dev *rtwdev, struct sk_buff *c2h); void rtw89_fw_c2h_work(struct work_struct *work); int rtw89_fw_h2c_role_maintain(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta, enum rtw89_upd_mode upd_mode); int rtw89_fw_h2c_join_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta, bool dis_conn); int rtw89_fw_h2c_notify_dbcc(struct rtw89_dev *rtwdev, bool en); int rtw89_fw_h2c_macid_pause(struct rtw89_dev *rtwdev, u8 sh, u8 grp, bool pause); int rtw89_fw_h2c_set_edca(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u8 ac, u32 val); int rtw89_fw_h2c_set_ofld_cfg(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_set_bcn_fltr_cfg(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, bool connect); int rtw89_fw_h2c_rssi_offload(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu); int rtw89_fw_h2c_tp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_ra(struct rtw89_dev *rtwdev, struct rtw89_ra_info *ra, bool csi); int rtw89_fw_h2c_cxdrv_init(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_init_v7(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_role(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_role_v1(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_role_v2(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_role_v7(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_role_v8(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_ctrl(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_ctrl_v7(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_trx(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_cxdrv_rfk(struct rtw89_dev *rtwdev, u8 type); int rtw89_fw_h2c_del_pkt_offload(struct rtw89_dev *rtwdev, u8 id); int rtw89_fw_h2c_add_pkt_offload(struct rtw89_dev *rtwdev, u8 *id, struct sk_buff *skb_ofld); int rtw89_fw_h2c_scan_list_offload(struct rtw89_dev *rtwdev, int ch_num, struct list_head *chan_list); int rtw89_fw_h2c_scan_list_offload_be(struct rtw89_dev *rtwdev, int ch_num, struct list_head *chan_list); int rtw89_fw_h2c_scan_offload_ax(struct rtw89_dev *rtwdev, struct rtw89_scan_option *opt, struct rtw89_vif *vif, bool wowlan); int rtw89_fw_h2c_scan_offload_be(struct rtw89_dev *rtwdev, struct rtw89_scan_option *opt, struct rtw89_vif *vif, bool wowlan); int rtw89_fw_h2c_rf_reg(struct rtw89_dev *rtwdev, struct rtw89_fw_h2c_rf_reg_info *info, u16 len, u8 page); int rtw89_fw_h2c_rf_ntfy_mcc(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_rf_pre_ntfy(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); int rtw89_fw_h2c_rf_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode); int rtw89_fw_h2c_rf_iqk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); int rtw89_fw_h2c_rf_dpk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); int rtw89_fw_h2c_rf_txgapk(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); int rtw89_fw_h2c_rf_dack(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); int rtw89_fw_h2c_rf_rxdck(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan); int rtw89_fw_h2c_raw_with_hdr(struct rtw89_dev *rtwdev, u8 h2c_class, u8 h2c_func, u8 *buf, u16 len, bool rack, bool dack); int rtw89_fw_h2c_raw(struct rtw89_dev *rtwdev, const u8 *buf, u16 len); void rtw89_fw_send_all_early_h2c(struct rtw89_dev *rtwdev); void rtw89_fw_free_all_early_h2c(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_general_pkt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u8 macid); void rtw89_fw_release_general_pkt_list_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool notify_fw); void rtw89_fw_release_general_pkt_list(struct rtw89_dev *rtwdev, bool notify_fw); int rtw89_fw_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, bool valid, struct ieee80211_ampdu_params *params); int rtw89_fw_h2c_ba_cam_v1(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, bool valid, struct ieee80211_ampdu_params *params); void rtw89_fw_h2c_init_dynamic_ba_cam_v0_ext(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_init_ba_cam_users(struct rtw89_dev *rtwdev, u8 users, u8 offset, u8 mac_idx); int rtw89_fw_h2c_lps_parm(struct rtw89_dev *rtwdev, struct rtw89_lps_parm *lps_param); int rtw89_fw_h2c_lps_ch_info(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_fwips(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); struct sk_buff *rtw89_fw_h2c_alloc_skb_with_hdr(struct rtw89_dev *rtwdev, u32 len); struct sk_buff *rtw89_fw_h2c_alloc_skb_no_hdr(struct rtw89_dev *rtwdev, u32 len); int rtw89_fw_msg_reg(struct rtw89_dev *rtwdev, struct rtw89_mac_h2c_info *h2c_info, struct rtw89_mac_c2h_info *c2h_info); int rtw89_fw_h2c_fw_log(struct rtw89_dev *rtwdev, bool enable); void rtw89_fw_st_dbg_dump(struct rtw89_dev *rtwdev); void rtw89_hw_scan_start(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_scan_request *req); void rtw89_hw_scan_complete(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, bool aborted); int rtw89_hw_scan_offload(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, bool enable); void rtw89_hw_scan_abort(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); int rtw89_hw_scan_add_chan_list_ax(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool connected); int rtw89_pno_scan_add_chan_list_ax(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_hw_scan_add_chan_list_be(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool connected); int rtw89_pno_scan_add_chan_list_be(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_fw_h2c_trigger_cpu_exception(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_pkt_drop(struct rtw89_dev *rtwdev, const struct rtw89_pkt_drop_params *params); int rtw89_fw_h2c_p2p_act(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_p2p_noa_desc *desc, u8 act, u8 noa_id); int rtw89_fw_h2c_tsf32_toggle(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool en); int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_cfg_pno(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_keep_alive(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_arp_offload(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_disconnect_detect(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_wow_global(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_wow_wakeup_ctrl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_wow_cam_update(struct rtw89_dev *rtwdev, struct rtw89_wow_cam_info *cam_info); int rtw89_fw_h2c_wow_gtk_ofld(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool enable); int rtw89_fw_h2c_wow_request_aoac(struct rtw89_dev *rtwdev); int rtw89_fw_h2c_add_mcc(struct rtw89_dev *rtwdev, const struct rtw89_fw_mcc_add_req *p); int rtw89_fw_h2c_start_mcc(struct rtw89_dev *rtwdev, const struct rtw89_fw_mcc_start_req *p); int rtw89_fw_h2c_stop_mcc(struct rtw89_dev *rtwdev, u8 group, u8 macid, bool prev_groups); int rtw89_fw_h2c_del_mcc_group(struct rtw89_dev *rtwdev, u8 group, bool prev_groups); int rtw89_fw_h2c_reset_mcc_group(struct rtw89_dev *rtwdev, u8 group); int rtw89_fw_h2c_mcc_req_tsf(struct rtw89_dev *rtwdev, const struct rtw89_fw_mcc_tsf_req *req, struct rtw89_mac_mcc_tsf_rpt *rpt); int rtw89_fw_h2c_mcc_macid_bitmap(struct rtw89_dev *rtwdev, u8 group, u8 macid, u8 *bitmap); int rtw89_fw_h2c_mcc_sync(struct rtw89_dev *rtwdev, u8 group, u8 source, u8 target, u8 offset); int rtw89_fw_h2c_mcc_set_duration(struct rtw89_dev *rtwdev, const struct rtw89_fw_mcc_duration *p); int rtw89_fw_h2c_mrc_add(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_add_arg *arg); int rtw89_fw_h2c_mrc_start(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_start_arg *arg); int rtw89_fw_h2c_mrc_del(struct rtw89_dev *rtwdev, u8 sch_idx, u8 slot_idx); int rtw89_fw_h2c_mrc_req_tsf(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_req_tsf_arg *arg, struct rtw89_mac_mrc_tsf_rpt *rpt); int rtw89_fw_h2c_mrc_upd_bitmap(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_upd_bitmap_arg *arg); int rtw89_fw_h2c_mrc_sync(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_sync_arg *arg); int rtw89_fw_h2c_mrc_upd_duration(struct rtw89_dev *rtwdev, const struct rtw89_fw_mrc_upd_duration_arg *arg); static inline void rtw89_fw_h2c_init_ba_cam(struct rtw89_dev *rtwdev) { … } static inline int rtw89_chip_h2c_default_cmac_tbl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta) { … } static inline int rtw89_chip_h2c_default_dmac_tbl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_sta *rtwsta) { … } static inline int rtw89_chip_h2c_update_beacon(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) { … } static inline int rtw89_chip_h2c_assoc_cmac_tbl(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { … } static inline int rtw89_chip_h2c_ampdu_cmac_tbl(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { … } static inline int rtw89_chip_h2c_ba_cam(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, bool valid, struct ieee80211_ampdu_params *params) { … } /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_byrate_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_2ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_5ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_6ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_ru_2ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_ru_5ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_txpwr_lmt_ru_6ghz_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_tx_shape_lmt_entry { … } __packed; /* must consider compatibility; don't insert new in the mid */ struct rtw89_fw_tx_shape_lmt_ru_entry { … } __packed; const struct rtw89_rfe_parms * rtw89_load_rfe_data_from_fw(struct rtw89_dev *rtwdev, const struct rtw89_rfe_parms *init); enum rtw89_wow_wakeup_ver { … }; #endif
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