/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright(c) 2019-2020 Realtek Corporation */ #ifndef __RTW89_PHY_H__ #define __RTW89_PHY_H__ #include "core.h" #define RTW89_BBMCU_ADDR_OFFSET … #define RTW89_RF_ADDR_ADSEL_MASK … #define get_phy_headline(addr) … #define PHY_HEADLINE_VALID … #define get_phy_target(addr) … #define get_phy_compare(rfe, cv) … #define get_phy_cond(addr) … #define get_phy_cond_rfe(addr) … #define get_phy_cond_pkg(addr) … #define get_phy_cond_cv(addr) … #define phy_div(a, b) … #define PHY_COND_BRANCH_IF … #define PHY_COND_BRANCH_ELIF … #define PHY_COND_BRANCH_ELSE … #define PHY_COND_BRANCH_END … #define PHY_COND_CHECK … #define PHY_COND_DONT_CARE … #define RA_MASK_CCK_RATES … #define RA_MASK_OFDM_RATES … #define RA_MASK_SUBCCK_RATES … #define RA_MASK_SUBOFDM_RATES … #define RA_MASK_HT_1SS_RATES … #define RA_MASK_HT_2SS_RATES … #define RA_MASK_HT_3SS_RATES … #define RA_MASK_HT_4SS_RATES … #define RA_MASK_HT_RATES … #define RA_MASK_VHT_1SS_RATES … #define RA_MASK_VHT_2SS_RATES … #define RA_MASK_VHT_3SS_RATES … #define RA_MASK_VHT_4SS_RATES … #define RA_MASK_VHT_RATES … #define RA_MASK_HE_1SS_RATES … #define RA_MASK_HE_2SS_RATES … #define RA_MASK_HE_3SS_RATES … #define RA_MASK_HE_4SS_RATES … #define RA_MASK_HE_RATES … #define RA_MASK_EHT_1SS_RATES … #define RA_MASK_EHT_2SS_RATES … #define RA_MASK_EHT_3SS_RATES … #define RA_MASK_EHT_4SS_RATES … #define RA_MASK_EHT_RATES … #define CFO_TRK_ENABLE_TH … #define CFO_TRK_STOP_TH_4 … #define CFO_TRK_STOP_TH_3 … #define CFO_TRK_STOP_TH_2 … #define CFO_TRK_STOP_TH_1 … #define CFO_TRK_STOP_TH … #define CFO_SW_COMP_FINE_TUNE … #define CFO_PERIOD_CNT … #define CFO_BOUND … #define CFO_TP_UPPER … #define CFO_TP_LOWER … #define CFO_COMP_PERIOD … #define CFO_COMP_WEIGHT … #define MAX_CFO_TOLERANCE … #define CFO_TF_CNT_TH … #define UL_TB_TF_CNT_L2H_TH … #define UL_TB_TF_CNT_H2L_TH … #define ANTDIV_TRAINNING_CNT … #define ANTDIV_TRAINNING_INTVL … #define ANTDIV_DELAY … #define ANTDIV_TP_DIFF_TH_HIGH … #define ANTDIV_TP_DIFF_TH_LOW … #define ANTDIV_EVM_DIFF_TH … #define ANTDIV_RSSI_DIFF_TH … #define CCX_MAX_PERIOD … #define CCX_MAX_PERIOD_UNIT … #define MS_TO_4US_RATIO … #define ENV_MNTR_FAIL_DWORD … #define ENV_MNTR_IFSCLM_HIS_MAX … #define PERMIL … #define PERCENT … #define IFS_CLM_TH0_UPPER … #define IFS_CLM_TH_MUL … #define IFS_CLM_TH_START_IDX … #define TIA0_GAIN_A … #define TIA0_GAIN_G … #define LNA0_GAIN … #define U4_MAX_BIT … #define U8_MAX_BIT … #define DIG_GAIN_SHIFT … #define DIG_GAIN … #define LNA_IDX_MAX … #define LNA_IDX_MIN … #define TIA_IDX_MAX … #define TIA_IDX_MIN … #define RXB_IDX_MAX … #define RXB_IDX_MIN … #define IGI_RSSI_MAX … #define PD_TH_MAX_RSSI … #define PD_TH_MIN_RSSI … #define CCKPD_TH_MIN_RSSI … #define PD_TH_BW160_CMP_VAL … #define PD_TH_BW80_CMP_VAL … #define PD_TH_BW40_CMP_VAL … #define PD_TH_BW20_CMP_VAL … #define PD_TH_CMP_VAL … #define PD_TH_SB_FLTR_CMP_VAL … #define PHYSTS_MGNT … #define PHYSTS_CTRL … #define PHYSTS_DATA … #define PHYSTS_RSVD … #define PPDU_FILTER_BITMAP … #define EDCCA_MAX … #define EDCCA_TH_L2H_LB … #define EDCCA_TH_REF … #define EDCCA_HL_DIFF_NORMAL … #define RSSI_UNIT_CONVER … #define EDCCA_UNIT_CONVER … #define EDCCA_PWROFST_DEFAULT … enum rtw89_phy_c2h_ra_func { … }; enum rtw89_phy_c2h_rfk_log_func { … }; enum rtw89_phy_c2h_rfk_report_func { … }; enum rtw89_phy_c2h_dm_func { … }; enum rtw89_phy_c2h_class { … }; enum rtw89_env_monitor_result_level { … }; #define CCX_US_BASE_RATIO … enum rtw89_ccx_unit { … }; enum rtw89_phy_status_ie_type { … }; enum rtw89_phy_status_bitmap { … }; enum rtw89_dig_gain_type { … }; enum rtw89_dig_gain_lna_idx { … }; enum rtw89_dig_gain_tia_idx { … }; enum rtw89_tssi_bandedge_cfg { … }; enum rtw89_tssi_sbw_idx { … }; struct rtw89_txpwr_byrate_cfg { … }; struct rtw89_txpwr_track_cfg { … }; struct rtw89_phy_dig_gain_cfg { … }; struct rtw89_phy_dig_gain_table { … }; struct rtw89_phy_tssi_dbw_table { … }; struct rtw89_phy_reg3_tbl { … }; #define DECLARE_PHY_REG3_TBL(_name) … struct rtw89_nbi_reg_def { … }; struct rtw89_ccx_regs { … }; struct rtw89_physts_regs { … }; struct rtw89_cfo_regs { … }; enum rtw89_bandwidth_section_num_ax { … }; enum rtw89_bandwidth_section_num_be { … }; #define RTW89_TXPWR_LMT_PAGE_SIZE_AX … struct rtw89_txpwr_limit_ax { … }; #define RTW89_TXPWR_LMT_PAGE_SIZE_BE … struct rtw89_txpwr_limit_be { … }; #define RTW89_RU_SEC_NUM_AX … #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_AX … struct rtw89_txpwr_limit_ru_ax { … }; #define RTW89_RU_SEC_NUM_BE … #define RTW89_TXPWR_LMT_RU_PAGE_SIZE_BE … struct rtw89_txpwr_limit_ru_be { … }; struct rtw89_phy_rfk_log_fmt { … }; struct rtw89_phy_gen_def { … }; extern const struct rtw89_phy_gen_def rtw89_phy_gen_ax; extern const struct rtw89_phy_gen_def rtw89_phy_gen_be; static inline void rtw89_phy_write8(struct rtw89_dev *rtwdev, u32 addr, u8 data) { … } static inline void rtw89_phy_write16(struct rtw89_dev *rtwdev, u32 addr, u16 data) { … } static inline void rtw89_phy_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data) { … } static inline void rtw89_phy_write32_set(struct rtw89_dev *rtwdev, u32 addr, u32 bits) { … } static inline void rtw89_phy_write32_clr(struct rtw89_dev *rtwdev, u32 addr, u32 bits) { … } static inline void rtw89_phy_write32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data) { … } static inline u8 rtw89_phy_read8(struct rtw89_dev *rtwdev, u32 addr) { … } static inline u16 rtw89_phy_read16(struct rtw89_dev *rtwdev, u32 addr) { … } static inline u32 rtw89_phy_read32(struct rtw89_dev *rtwdev, u32 addr) { … } static inline u32 rtw89_phy_read32_mask(struct rtw89_dev *rtwdev, u32 addr, u32 mask) { … } static inline void rtw89_bbmcu_write32(struct rtw89_dev *rtwdev, u32 addr, u32 data, enum rtw89_phy_idx phy_idx) { … } static inline enum rtw89_gain_offset rtw89_subband_to_gain_offset_band_of_ofdm(enum rtw89_subband subband) { … } static inline enum rtw89_phy_bb_gain_band rtw89_subband_to_bb_gain_band(enum rtw89_subband subband) { … } static inline enum rtw89_phy_gain_band_be rtw89_subband_to_gain_band_be(enum rtw89_subband subband) { … } struct rtw89_rfk_chan_desc { … }; enum rtw89_rfk_flag { … }; struct rtw89_rfk_tbl { … }; #define RTW89_DECLARE_RFK_TBL(_name) … #define RTW89_DECL_RFK_WRF(_path, _addr, _mask, _data) … #define RTW89_DECL_RFK_WM(_addr, _mask, _data) … #define RTW89_DECL_RFK_WS(_addr, _mask) … #define RTW89_DECL_RFK_WC(_addr, _mask) … #define RTW89_DECL_RFK_DELAY(_data) … void rtw89_rfk_parser(struct rtw89_dev *rtwdev, const struct rtw89_rfk_tbl *tbl); #define rtw89_rfk_parser_by_cond(dev, cond, tbl_t, tbl_f) … void rtw89_phy_write_reg3_tbl(struct rtw89_dev *rtwdev, const struct rtw89_phy_reg3_tbl *tbl); u8 rtw89_phy_get_txsc(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_bandwidth dbw); u8 rtw89_phy_get_txsb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_bandwidth dbw); u32 rtw89_phy_read_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask); u32 rtw89_phy_read_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask); u32 rtw89_phy_read_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask); bool rtw89_phy_write_rf(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); bool rtw89_phy_write_rf_v1(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); bool rtw89_phy_write_rf_v2(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path, u32 addr, u32 mask, u32 data); void rtw89_phy_init_bb_reg(struct rtw89_dev *rtwdev); void rtw89_phy_init_rf_reg(struct rtw89_dev *rtwdev, bool noio); void rtw89_phy_config_rf_reg_v1(struct rtw89_dev *rtwdev, const struct rtw89_reg2_def *reg, enum rtw89_rf_path rf_path, void *extra_data); void rtw89_phy_dm_init(struct rtw89_dev *rtwdev); void rtw89_phy_write32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 data, enum rtw89_phy_idx phy_idx); u32 rtw89_phy_read32_idx(struct rtw89_dev *rtwdev, u32 addr, u32 mask, enum rtw89_phy_idx phy_idx); s8 *rtw89_phy_raw_byr_seek(struct rtw89_dev *rtwdev, struct rtw89_txpwr_byrate *head, const struct rtw89_rate_desc *desc); s8 rtw89_phy_read_txpwr_byrate(struct rtw89_dev *rtwdev, u8 band, u8 bw, const struct rtw89_rate_desc *rate_desc); void rtw89_phy_load_txpwr_byrate(struct rtw89_dev *rtwdev, const struct rtw89_txpwr_table *tbl); s8 rtw89_phy_read_txpwr_limit(struct rtw89_dev *rtwdev, u8 band, u8 bw, u8 ntx, u8 rs, u8 bf, u8 ch); s8 rtw89_phy_read_txpwr_limit_ru(struct rtw89_dev *rtwdev, u8 band, u8 ru, u8 ntx, u8 ch); static inline void rtw89_phy_preinit_rf_nctl(struct rtw89_dev *rtwdev) { … } static inline void rtw89_phy_bb_wrap_init(struct rtw89_dev *rtwdev) { … } static inline void rtw89_phy_ch_info_init(struct rtw89_dev *rtwdev) { … } static inline void rtw89_phy_set_txpwr_byrate(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_phy_set_txpwr_offset(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_phy_set_txpwr_limit(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_phy_idx phy_idx) { … } static inline void rtw89_phy_set_txpwr_limit_ru(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, enum rtw89_phy_idx phy_idx) { … } void rtw89_phy_ra_assoc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta); void rtw89_phy_ra_update(struct rtw89_dev *rtwdev); void rtw89_phy_ra_update_sta(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, u32 changed); void rtw89_phy_rate_pattern_vif(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, const struct cfg80211_bitrate_mask *mask); bool rtw89_phy_c2h_chk_atomic(struct rtw89_dev *rtwdev, u8 class, u8 func); void rtw89_phy_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len, u8 class, u8 func); int rtw89_phy_rfk_pre_ntfy_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, unsigned int ms); int rtw89_phy_rfk_tssi_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, enum rtw89_tssi_mode tssi_mode, unsigned int ms); int rtw89_phy_rfk_iqk_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); int rtw89_phy_rfk_dpk_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); int rtw89_phy_rfk_txgapk_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); int rtw89_phy_rfk_dack_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); int rtw89_phy_rfk_rxdck_and_wait(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, const struct rtw89_chan *chan, unsigned int ms); void rtw89_phy_rfk_tssi_fill_fwcmd_efuse_to_de(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, const struct rtw89_chan *chan, struct rtw89_h2c_rf_tssi *h2c); void rtw89_phy_rfk_tssi_fill_fwcmd_tmeter_tbl(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy, const struct rtw89_chan *chan, struct rtw89_h2c_rf_tssi *h2c); void rtw89_phy_cfo_track(struct rtw89_dev *rtwdev); void rtw89_phy_cfo_track_work(struct work_struct *work); void rtw89_phy_cfo_parse(struct rtw89_dev *rtwdev, s16 cfo_val, struct rtw89_rx_phy_ppdu *phy_ppdu); void rtw89_phy_stat_track(struct rtw89_dev *rtwdev); void rtw89_phy_env_monitor_track(struct rtw89_dev *rtwdev); void rtw89_phy_set_phy_regs(struct rtw89_dev *rtwdev, u32 addr, u32 mask, u32 val); void rtw89_phy_dig_reset(struct rtw89_dev *rtwdev); void rtw89_phy_dig(struct rtw89_dev *rtwdev); void rtw89_phy_tx_path_div_track(struct rtw89_dev *rtwdev); void rtw89_phy_antdiv_parse(struct rtw89_dev *rtwdev, struct rtw89_rx_phy_ppdu *phy_ppdu); void rtw89_phy_antdiv_track(struct rtw89_dev *rtwdev); void rtw89_phy_antdiv_work(struct work_struct *work); void rtw89_phy_set_bss_color(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); void rtw89_phy_tssi_ctrl_set_bandedge_cfg(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, enum rtw89_tssi_bandedge_cfg bandedge_cfg); void rtw89_phy_ul_tb_assoc(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_phy_ul_tb_ctrl_track(struct rtw89_dev *rtwdev); u8 rtw89_encode_chan_idx(struct rtw89_dev *rtwdev, u8 central_ch, u8 band); void rtw89_decode_chan_idx(struct rtw89_dev *rtwdev, u8 chan_idx, u8 *ch, enum nl80211_band *band); void rtw89_phy_config_edcca(struct rtw89_dev *rtwdev, bool scan); void rtw89_phy_edcca_track(struct rtw89_dev *rtwdev); void rtw89_phy_edcca_thre_calc(struct rtw89_dev *rtwdev); enum rtw89_rf_path_bit rtw89_phy_get_kpath(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); enum rtw89_rf_path rtw89_phy_get_syn_sel(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); u8 rtw89_rfk_chan_lookup(struct rtw89_dev *rtwdev, const struct rtw89_rfk_chan_desc *desc, u8 desc_nr, const struct rtw89_chan *target_chan); #endif
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