/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ /* Copyright(c) 2019-2020 Realtek Corporation */ #ifndef __RTW89_MAC_H__ #define __RTW89_MAC_H__ #include "core.h" #include "reg.h" #define MAC_MEM_DUMP_PAGE_SIZE … #define ADDR_CAM_ENT_SIZE … #define ADDR_CAM_ENT_SHORT_SIZE … #define BSSID_CAM_ENT_SIZE … #define HFC_PAGE_UNIT … #define RPWM_TRY_CNT … enum rtw89_mac_hwmod_sel { … }; enum rtw89_mac_fwd_target { … }; enum rtw89_mac_wd_dma_intvl { … }; enum rtw89_mac_multi_tag_num { … }; enum rtw89_mac_lbc_tmr { … }; enum rtw89_mac_cpuio_op_cmd_type { … }; enum rtw89_mac_wde_dle_port_id { … }; enum rtw89_mac_wde_dle_queid_wdrls { … }; enum rtw89_mac_ple_dle_port_id { … }; enum rtw89_mac_ple_dle_queid_plrls { … }; enum rtw89_machdr_frame_type { … }; enum rtw89_mac_dle_dfi_type { … }; enum rtw89_mac_dle_wde_quota_id { … }; enum rtw89_mac_dle_ple_quota_id { … }; enum rtw89_mac_dle_ctrl_type { … }; enum rtw89_mac_ax_l0_to_l1_event { … }; enum rtw89_mac_wow_fw_status { … }; #define RTW89_PORT_OFFSET_TU_TO_32US(shift_tu) … enum rtw89_mac_dbg_port_sel { … }; /* SRAM mem dump */ #define R_AX_INDIR_ACCESS_ENTRY … #define R_BE_INDIR_ACCESS_ENTRY … #define AXIDMA_BASE_ADDR … #define STA_SCHED_BASE_ADDR … #define RXPLD_FLTR_CAM_BASE_ADDR … #define SECURITY_CAM_BASE_ADDR … #define WOW_CAM_BASE_ADDR … #define CMAC_TBL_BASE_ADDR … #define ADDR_CAM_BASE_ADDR … #define BSSID_CAM_BASE_ADDR … #define BA_CAM_BASE_ADDR … #define BCN_IE_CAM0_BASE_ADDR … #define SHARED_BUF_BASE_ADDR … #define DMAC_TBL_BASE_ADDR … #define SHCUT_MACHDR_BASE_ADDR … #define BCN_IE_CAM1_BASE_ADDR … #define TXD_FIFO_0_BASE_ADDR … #define TXD_FIFO_1_BASE_ADDR … #define TXD_FIFO_0_BASE_ADDR_V1 … #define TXD_FIFO_1_BASE_ADDR_V1 … #define TXDATA_FIFO_0_BASE_ADDR … #define TXDATA_FIFO_1_BASE_ADDR … #define CPU_LOCAL_BASE_ADDR … #define WD_PAGE_BASE_ADDR_BE … #define CPU_LOCAL_BASE_ADDR_BE … #define AXIDMA_BASE_ADDR_BE … #define SHARED_BUF_BASE_ADDR_BE … #define DMAC_TBL_BASE_ADDR_BE … #define SHCUT_MACHDR_BASE_ADDR_BE … #define STA_SCHED_BASE_ADDR_BE … #define NAT25_CAM_BASE_ADDR_BE … #define RXPLD_FLTR_CAM_BASE_ADDR_BE … #define SEC_CAM_BASE_ADDR_BE … #define WOW_CAM_BASE_ADDR_BE … #define MLD_TBL_BASE_ADDR_BE … #define RX_CLSF_CAM_BASE_ADDR_BE … #define CMAC_TBL_BASE_ADDR_BE … #define ADDR_CAM_BASE_ADDR_BE … #define BSSID_CAM_BASE_ADDR_BE … #define BA_CAM_BASE_ADDR_BE … #define BCN_IE_CAM0_BASE_ADDR_BE … #define TXDATA_FIFO_0_BASE_ADDR_BE … #define TXD_FIFO_0_BASE_ADDR_BE … #define BCN_IE_CAM1_BASE_ADDR_BE … #define TXDATA_FIFO_1_BASE_ADDR_BE … #define TXD_FIFO_1_BASE_ADDR_BE … #define DCPU_LOCAL_BASE_ADDR_BE … #define CCTL_INFO_SIZE … enum rtw89_mac_mem_sel { … }; enum rtw89_rpwm_req_pwr_state { … }; struct rtw89_pwr_cfg { … }; enum rtw89_mac_c2h_ofld_func { … }; enum rtw89_mac_c2h_info_func { … }; enum rtw89_mac_c2h_mcc_func { … }; enum rtw89_mac_c2h_mrc_func { … }; enum rtw89_mac_c2h_wow_func { … }; enum rtw89_mac_c2h_class { … }; enum rtw89_mac_mcc_status { … }; enum rtw89_mac_mrc_status { … }; struct rtw89_mac_ax_coex { … }; struct rtw89_mac_ax_plt { … }; enum rtw89_mac_bf_rrsc_rate { … }; #define RTW89_R32_EA … #define RTW89_R32_DEAD … #define MAC_REG_POOL_COUNT … #define ACCESS_CMAC(_addr) … #define RTW89_MAC_AX_BAND_REG_OFFSET … #define RTW89_MAC_BE_BAND_REG_OFFSET … #define PTCL_IDLE_POLL_CNT … #define SW_CVR_DUR_US … #define SW_CVR_CNT … #define DLE_BOUND_UNIT … #define DLE_WAIT_CNT … #define TRXCFG_WAIT_CNT … #define RTW89_WDE_PG_64 … #define RTW89_WDE_PG_128 … #define RTW89_WDE_PG_256 … #define S_AX_WDE_PAGE_SEL_64 … #define S_AX_WDE_PAGE_SEL_128 … #define S_AX_WDE_PAGE_SEL_256 … #define RTW89_PLE_PG_64 … #define RTW89_PLE_PG_128 … #define RTW89_PLE_PG_256 … #define S_AX_PLE_PAGE_SEL_64 … #define S_AX_PLE_PAGE_SEL_128 … #define S_AX_PLE_PAGE_SEL_256 … #define B_CMAC0_MGQ_NORMAL … #define B_CMAC0_MGQ_NO_PWRSAV … #define B_CMAC0_CPUMGQ … #define B_CMAC1_MGQ_NORMAL … #define B_CMAC1_MGQ_NO_PWRSAV … #define B_CMAC1_CPUMGQ … #define B_CMAC0_MGQ_NORMAL_BE … #define B_CMAC1_MGQ_NORMAL_BE … #define QEMP_ACQ_GRP_MACID_NUM … #define QEMP_ACQ_GRP_QSEL_SH … #define QEMP_ACQ_GRP_QSEL_MASK … #define SDIO_LOCAL_BASE_ADDR … #define PWR_CMD_WRITE … #define PWR_CMD_POLL … #define PWR_CMD_DELAY … #define PWR_CMD_END … #define PWR_INTF_MSK_SDIO … #define PWR_INTF_MSK_USB … #define PWR_INTF_MSK_PCIE … #define PWR_INTF_MSK_ALL … #define PWR_BASE_MAC … #define PWR_BASE_USB … #define PWR_BASE_PCIE … #define PWR_BASE_SDIO … #define PWR_CV_MSK_A … #define PWR_CV_MSK_B … #define PWR_CV_MSK_C … #define PWR_CV_MSK_D … #define PWR_CV_MSK_E … #define PWR_CV_MSK_F … #define PWR_CV_MSK_G … #define PWR_CV_MSK_TEST … #define PWR_CV_MSK_ALL … #define PWR_DELAY_US … #define PWR_DELAY_MS … /* STA scheduler */ #define SS_MACID_SH … #define SS_TX_LEN_MSK … #define SS_CTRL1_R_TX_LEN … #define SS_CTRL1_R_NEXT_LINK … #define SS_LINK_SIZE … /* MAC debug port */ #define TMAC_DBG_SEL_C0 … #define RMAC_DBG_SEL_C0 … #define TRXPTCL_DBG_SEL_C0 … #define TMAC_DBG_SEL_C1 … #define RMAC_DBG_SEL_C1 … #define TRXPTCL_DBG_SEL_C1 … #define FW_PROG_CNTR_DBG_SEL … #define PCIE_TXDMA_DBG_SEL … #define PCIE_RXDMA_DBG_SEL … #define PCIE_CVT_DBG_SEL … #define PCIE_CXPL_DBG_SEL … #define PCIE_IO_DBG_SEL … #define PCIE_MISC_DBG_SEL … #define PCIE_MISC2_DBG_SEL … #define MAC_DBG_SEL … #define RMAC_CMAC_DBG_SEL … /* TRXPTCL dbg port sel */ #define TRXPTRL_DBG_SEL_TMAC … #define TRXPTRL_DBG_SEL_RMAC … struct rtw89_cpuio_ctrl { … }; struct rtw89_mac_dbg_port_info { … }; #define QLNKTBL_ADDR_INFO_SEL … #define QLNKTBL_ADDR_INFO_SEL_0 … #define QLNKTBL_ADDR_INFO_SEL_1 … #define QLNKTBL_ADDR_TBL_IDX_MASK … #define QLNKTBL_DATA_SEL1_PKT_CNT_MASK … struct rtw89_mac_dle_dfi_ctrl { … }; struct rtw89_mac_dle_dfi_quota { … }; struct rtw89_mac_dle_dfi_qempty { … }; enum rtw89_mac_dle_rsvd_qt_type { … }; struct rtw89_mac_dle_rsvd_qt_cfg { … }; enum rtw89_mac_error_scenario { … }; #define RTW89_ERROR_SCENARIO(__err) … /* Define DBG and recovery enum */ enum mac_ax_err_info { … }; struct rtw89_mac_size_set { … }; extern const struct rtw89_mac_size_set rtw89_mac_size; struct rtw89_mac_gen_def { … }; extern const struct rtw89_mac_gen_def rtw89_mac_gen_ax; extern const struct rtw89_mac_gen_def rtw89_mac_gen_be; static inline u32 rtw89_mac_reg_by_idx(struct rtw89_dev *rtwdev, u32 reg_base, u8 band) { … } static inline u32 rtw89_mac_reg_by_port(struct rtw89_dev *rtwdev, u32 base, u8 port, u8 mac_idx) { … } static inline u32 rtw89_read32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base) { … } static inline u32 rtw89_read32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 mask) { … } static inline void rtw89_write32_port(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 data) { … } static inline void rtw89_write32_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 mask, u32 data) { … } static inline void rtw89_write16_port_mask(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 mask, u16 data) { … } static inline void rtw89_write32_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 bit) { … } static inline void rtw89_write16_port_clr(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u16 bit) { … } static inline void rtw89_write32_port_set(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u32 base, u32 bit) { … } void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev); int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb); int rtw89_mac_init(struct rtw89_dev *rtwdev); int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, enum rtw89_qta_mode ext_mode); int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en); int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, enum rtw89_qta_mode mode); bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode); static inline int rtw89_mac_check_mac_en(struct rtw89_dev *rtwdev, u8 band, enum rtw89_mac_hwmod_sel sel) { … } int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val); int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val); int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl); int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_quota *quota); void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev); int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_qempty *qempty); void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, enum mac_ax_err_info err); int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, struct rtw89_vif *rtwvif_src, u16 offset_tu); int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, u64 *tsf); void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool en); void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif); void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en); int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *vif); int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev); int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev); static inline int rtw89_chip_enable_bb_rf(struct rtw89_dev *rtwdev) { … } static inline int rtw89_chip_disable_bb_rf(struct rtw89_dev *rtwdev) { … } static inline int rtw89_chip_reset_bb_rf(struct rtw89_dev *rtwdev) { … } u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev); int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err); bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u8 class, u8 func); void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len, u8 class, u8 func); int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev); int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel); int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel); int rtw89_mac_stop_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 *tx_en, enum rtw89_sch_tx_sel sel); int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); int rtw89_mac_resume_sch_tx_v2(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en); static inline int rtw89_mac_cfg_ppdu_status(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) { … } void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx); void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop); int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex); int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); int rtw89_mac_cfg_gnt_v2(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex_gnt *gnt_cfg); static inline int rtw89_mac_cfg_plt(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) { … } static inline u16 rtw89_mac_get_plt_cnt(struct rtw89_dev *rtwdev, u8 band) { … } void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val); u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev); bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev); int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl); int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl); int rtw89_mac_cfg_ctrl_path_v2(struct rtw89_dev *rtwdev, bool wl); void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter); void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev); static inline void rtw89_mac_bf_assoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta) { … } void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_sta *sta); void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, struct ieee80211_bss_conf *conf); void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, struct ieee80211_sta *sta, bool disconnect); void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev); void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en); int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, bool en); int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause); static inline void rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) { … } static inline int rtw89_mac_txpwr_read32(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 *val) { … } static inline int rtw89_mac_txpwr_write32(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 val) { … } static inline int rtw89_mac_txpwr_write32_mask(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx, u32 reg_base, u32 mask, u32 val) { … } static inline void rtw89_mac_ctrl_hci_dma_tx(struct rtw89_dev *rtwdev, bool enable) { … } static inline void rtw89_mac_ctrl_hci_dma_rx(struct rtw89_dev *rtwdev, bool enable) { … } static inline void rtw89_mac_ctrl_hci_dma_trx(struct rtw89_dev *rtwdev, bool enable) { … } static inline bool rtw89_mac_get_power_state(struct rtw89_dev *rtwdev) { … } int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, bool resume, u32 tx_time); int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, u32 *tx_time); int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, bool resume, u8 tx_retry); int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, u8 *tx_retry); enum rtw89_mac_xtal_si_offset { … }; static inline int rtw89_mac_write_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) { … } static inline int rtw89_mac_read_xtal_si(struct rtw89_dev *rtwdev, u8 offset, u8 *val) { … } void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif); int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow); int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, enum rtw89_mac_idx band); void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool wow); int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, bool band1_en); int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, enum rtw89_mac_dle_rsvd_qt_type type, struct rtw89_mac_dle_rsvd_qt_cfg *cfg); int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable); #endif
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