#ifndef __RSI_HAL_H__
#define __RSI_HAL_H__
#define DEV_OPMODE_WIFI_ALONE …
#define DEV_OPMODE_BT_ALONE …
#define DEV_OPMODE_BT_LE_ALONE …
#define DEV_OPMODE_BT_DUAL …
#define DEV_OPMODE_STA_BT …
#define DEV_OPMODE_STA_BT_LE …
#define DEV_OPMODE_STA_BT_DUAL …
#define DEV_OPMODE_AP_BT …
#define DEV_OPMODE_AP_BT_DUAL …
#define DEV_OPMODE_PARAM_DESC …
#define FLASH_WRITE_CHUNK_SIZE …
#define FLASH_SECTOR_SIZE …
#define FLASH_SIZE_ADDR …
#define PING_BUFFER_ADDRESS …
#define PONG_BUFFER_ADDRESS …
#define SWBL_REGIN …
#define SWBL_REGOUT …
#define PING_WRITE …
#define PONG_WRITE …
#define BL_CMD_TIMEOUT …
#define BL_BURN_TIMEOUT …
#define REGIN_VALID …
#define REGIN_INPUT …
#define REGOUT_VALID …
#define REGOUT_INVALID …
#define CMD_PASS …
#define CMD_FAIL …
#define LOAD_HOSTED_FW …
#define BURN_HOSTED_FW …
#define PING_VALID …
#define PONG_VALID …
#define PING_AVAIL …
#define PONG_AVAIL …
#define EOF_REACHED …
#define CHECK_CRC …
#define POLLING_MODE …
#define AUTO_READ_MODE …
#define JUMP_TO_ZERO_PC …
#define FW_LOADING_SUCCESSFUL …
#define LOADING_INITIATED …
#define RSI_ULP_RESET_REG …
#define RSI_WATCH_DOG_TIMER_1 …
#define RSI_WATCH_DOG_TIMER_2 …
#define RSI_WATCH_DOG_DELAY_TIMER_1 …
#define RSI_WATCH_DOG_DELAY_TIMER_2 …
#define RSI_WATCH_DOG_TIMER_ENABLE …
#define NWP_AHB_BASE_ADDR …
#define NWP_WWD_INTERRUPT_TIMER …
#define NWP_WWD_SYSTEM_RESET_TIMER …
#define NWP_WWD_WINDOW_TIMER …
#define NWP_WWD_TIMER_SETTINGS …
#define NWP_WWD_MODE_AND_RSTART …
#define NWP_WWD_RESET_BYPASS …
#define NWP_FSM_INTR_MASK_REG …
#define NWP_WWD_INT_TIMER_CLKS …
#define NWP_WWD_SYS_RESET_TIMER_CLKS …
#define NWP_WWD_TIMER_DISABLE …
#define RSI_ULP_WRITE_0 …
#define RSI_ULP_WRITE_2 …
#define RSI_ULP_WRITE_50 …
#define RSI_RESTART_WDT …
#define RSI_BYPASS_ULP_ON_WDT …
#define RSI_ULP_TIMER_ENABLE …
#define RSI_RF_SPI_PROG_REG_BASE_ADDR …
#define RSI_GSPI_CTRL_REG0 …
#define RSI_GSPI_CTRL_REG1 …
#define RSI_GSPI_DATA_REG0 …
#define RSI_GSPI_DATA_REG1 …
#define RSI_GSPI_DATA_REG2 …
#define RSI_GSPI_CTRL_REG0_VALUE …
#define RSI_GSPI_DMA_MODE …
#define RSI_GSPI_2_ULP …
#define RSI_GSPI_TRIG …
#define RSI_GSPI_READ …
#define RSI_GSPI_RF_SPI_ACTIVE …
#define SEND_RPS_FILE …
#define FW_IMAGE_MIN_ADDRESS …
#define MAX_FLASH_FILE_SIZE …
#define FLASH_START_ADDRESS …
#define COMMON_HAL_CARD_READY_IND …
#define COMMAN_HAL_WAIT_FOR_CARD_READY …
#define RSI_DEV_OPMODE_WIFI_ALONE …
#define RSI_DEV_COEX_MODE_WIFI_ALONE …
#define BBP_INFO_40MHZ …
#define FW_FLASH_OFFSET …
#define LMAC_VER_OFFSET_9113 …
#define LMAC_VER_OFFSET_9116 …
#define MAX_DWORD_ALIGN_BYTES …
#define RSI_COMMON_REG_SIZE …
#define RSI_9116_REG_SIZE …
#define FW_ALIGN_SIZE …
#define RSI_9116_FW_MAGIC_WORD …
#define MEM_ACCESS_CTRL_FROM_HOST …
#define RAM_384K_ACCESS_FROM_TA …
struct bl_header { … } __packed;
struct ta_metadata { … };
#define RSI_BL_CTRL_LEN_MASK …
#define RSI_BL_CTRL_SPI_32BIT_MODE …
#define RSI_BL_CTRL_REL_TA_SOFTRESET …
#define RSI_BL_CTRL_START_FROM_ROM_PC …
#define RSI_BL_CTRL_SPI_8BIT_MODE …
#define RSI_BL_CTRL_LAST_ENTRY …
struct bootload_entry { … } __packed;
struct bootload_ds { … } __packed;
struct rsi_mgmt_desc { … } __packed;
struct rsi_data_desc { … } __packed;
struct rsi_bt_desc { … } __packed;
int rsi_hal_device_init(struct rsi_hw *adapter);
int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
int rsi_prepare_beacon(struct rsi_common *common, struct sk_buff *skb);
int rsi_send_pkt_to_bus(struct rsi_common *common, struct sk_buff *skb);
int rsi_send_bt_pkt(struct rsi_common *common, struct sk_buff *skb);
#endif