/* SPDX-License-Identifier: GPL-2.0-only */ /* * Low-level I/O functions. * * Copyright (c) 2017-2020, Silicon Laboratories, Inc. * Copyright (c) 2010, ST-Ericsson */ #ifndef WFX_HWIO_H #define WFX_HWIO_H #include <linux/types.h> struct wfx_dev; /* Caution: in the functions below, 'buf' will used with a DMA. So, it must be kmalloc'd (do not use * stack allocated buffers). In doubt, enable CONFIG_DEBUG_SG to detect badly located buffer. */ int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len); int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len); int wfx_sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len); int wfx_sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len); int wfx_ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len); int wfx_ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len); int wfx_sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val); int wfx_sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val); int wfx_ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val); int wfx_ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val); #define CFG_ERR_SPI_FRAME … #define CFG_ERR_SDIO_BUF_MISMATCH … #define CFG_ERR_BUF_UNDERRUN … #define CFG_ERR_DATA_IN_TOO_LARGE … #define CFG_ERR_HOST_NO_OUT_QUEUE … #define CFG_ERR_BUF_OVERRUN … #define CFG_ERR_DATA_OUT_TOO_LARGE … #define CFG_ERR_HOST_NO_IN_QUEUE … #define CFG_ERR_HOST_CRC_MISS … #define CFG_SPI_IGNORE_CS … #define CFG_BYTE_ORDER_MASK … #define CFG_BYTE_ORDER_BADC … #define CFG_BYTE_ORDER_DCBA … #define CFG_BYTE_ORDER_ABCD … #define CFG_DIRECT_ACCESS_MODE … #define CFG_PREFETCH_AHB … #define CFG_DISABLE_CPU_CLK … #define CFG_PREFETCH_SRAM … #define CFG_CPU_RESET … #define CFG_SDIO_DISABLE_IRQ … #define CFG_IRQ_ENABLE_DATA … #define CFG_IRQ_ENABLE_WRDY … #define CFG_CLK_RISE_EDGE … #define CFG_SDIO_DISABLE_CRC_CHK … #define CFG_RESERVED … #define CFG_DEVICE_ID_MAJOR … #define CFG_DEVICE_ID_RESERVED … #define CFG_DEVICE_ID_TYPE … int wfx_config_reg_read(struct wfx_dev *wdev, u32 *val); int wfx_config_reg_write(struct wfx_dev *wdev, u32 val); int wfx_config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val); #define CTRL_NEXT_LEN_MASK … #define CTRL_WLAN_WAKEUP … #define CTRL_WLAN_READY … int wfx_control_reg_read(struct wfx_dev *wdev, u32 *val); int wfx_control_reg_write(struct wfx_dev *wdev, u32 val); int wfx_control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val); #define IGPR_RW … #define IGPR_INDEX … #define IGPR_VALUE … int wfx_igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val); int wfx_igpr_reg_write(struct wfx_dev *wdev, int index, u32 val); #endif
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