/* SPDX-License-Identifier: GPL-2.0-only */ /* * Low-level API for mac80211 ST-Ericsson CW1200 drivers * * Copyright (c) 2010, ST-Ericsson * Author: Dmitry Tarnyagin <[email protected]> * * Based on: * ST-Ericsson UMAC CW1200 driver which is * Copyright (c) 2010, ST-Ericsson * Author: Ajitpal Singh <[email protected]> */ #ifndef CW1200_HWIO_H_INCLUDED #define CW1200_HWIO_H_INCLUDED /* extern */ struct cw1200_common; #define CW1200_CUT_11_ID_STR … #define CW1200_CUT_22_ID_STR1 … #define CW1200_CUT_22_ID_STR2 … #define CW1200_CUT_22_ID_STR3 … #define CW1200_CUT_ID_ADDR … #define CW1200_CUT2_ID_ADDR … /* Download control area */ /* boot loader start address in SRAM */ #define DOWNLOAD_BOOT_LOADER_OFFSET … /* 32K, 0x4000 to 0xDFFF */ #define DOWNLOAD_FIFO_OFFSET … /* 32K */ #define DOWNLOAD_FIFO_SIZE … /* 128 bytes, 0xFF80 to 0xFFFF */ #define DOWNLOAD_CTRL_OFFSET … #define DOWNLOAD_CTRL_DATA_DWORDS … struct download_cntl_t { … }; #define DOWNLOAD_IMAGE_SIZE_REG … #define DOWNLOAD_FLAGS_REG … #define DOWNLOAD_PUT_REG … #define DOWNLOAD_TRACE_PC_REG … #define DOWNLOAD_GET_REG … #define DOWNLOAD_STATUS_REG … #define DOWNLOAD_DEBUG_DATA_REG … #define DOWNLOAD_DEBUG_DATA_LEN … #define DOWNLOAD_BLOCK_SIZE … /* For boot loader detection */ #define DOWNLOAD_ARE_YOU_HERE … #define DOWNLOAD_I_AM_HERE … /* Download error code */ #define DOWNLOAD_PENDING … #define DOWNLOAD_SUCCESS … #define DOWNLOAD_EXCEPTION … #define DOWNLOAD_ERR_MEM_1 … #define DOWNLOAD_ERR_MEM_2 … #define DOWNLOAD_ERR_SOFTWARE … #define DOWNLOAD_ERR_FILE_SIZE … #define DOWNLOAD_ERR_CHECKSUM … #define DOWNLOAD_ERR_OVERFLOW … #define DOWNLOAD_ERR_IMAGE … #define DOWNLOAD_ERR_HOST … #define DOWNLOAD_ERR_ABORT … #define SYS_BASE_ADDR_SILICON … #define PAC_BASE_ADDRESS_SILICON … #define PAC_SHARED_MEMORY_SILICON … #define CW1200_APB(addr) … /* Device register definitions */ /* WBF - SPI Register Addresses */ #define ST90TDS_ADDR_ID_BASE … /* 16/32 bits */ #define ST90TDS_CONFIG_REG_ID … /* 16/32 bits */ #define ST90TDS_CONTROL_REG_ID … /* 16 bits, Q mode W/R */ #define ST90TDS_IN_OUT_QUEUE_REG_ID … /* 32 bits, AHB bus R/W */ #define ST90TDS_AHB_DPORT_REG_ID … /* 16/32 bits */ #define ST90TDS_SRAM_BASE_ADDR_REG_ID … /* 32 bits, APB bus R/W */ #define ST90TDS_SRAM_DPORT_REG_ID … /* 32 bits, t_settle/general */ #define ST90TDS_TSET_GEN_R_W_REG_ID … /* 16 bits, Q mode read, no length */ #define ST90TDS_FRAME_OUT_REG_ID … #define ST90TDS_ADDR_ID_MAX … /* WBF - Control register bit set */ /* next o/p length, bit 11 to 0 */ #define ST90TDS_CONT_NEXT_LEN_MASK … #define ST90TDS_CONT_WUP_BIT … #define ST90TDS_CONT_RDY_BIT … #define ST90TDS_CONT_IRQ_ENABLE … #define ST90TDS_CONT_RDY_ENABLE … #define ST90TDS_CONT_IRQ_RDY_ENABLE … /* SPI Config register bit set */ #define ST90TDS_CONFIG_FRAME_BIT … #define ST90TDS_CONFIG_WORD_MODE_BITS … #define ST90TDS_CONFIG_WORD_MODE_1 … #define ST90TDS_CONFIG_WORD_MODE_2 … #define ST90TDS_CONFIG_ERROR_0_BIT … #define ST90TDS_CONFIG_ERROR_1_BIT … #define ST90TDS_CONFIG_ERROR_2_BIT … /* TBD: Sure??? */ #define ST90TDS_CONFIG_CSN_FRAME_BIT … #define ST90TDS_CONFIG_ERROR_3_BIT … #define ST90TDS_CONFIG_ERROR_4_BIT … /* QueueM */ #define ST90TDS_CONFIG_ACCESS_MODE_BIT … /* AHB bus */ #define ST90TDS_CONFIG_AHB_PRFETCH_BIT … #define ST90TDS_CONFIG_CPU_CLK_DIS_BIT … /* APB bus */ #define ST90TDS_CONFIG_PRFETCH_BIT … /* cpu reset */ #define ST90TDS_CONFIG_CPU_RESET_BIT … #define ST90TDS_CONFIG_CLEAR_INT_BIT … /* For CW1200 the IRQ Enable and Ready Bits are in CONFIG register */ #define ST90TDS_CONF_IRQ_ENABLE … #define ST90TDS_CONF_RDY_ENABLE … #define ST90TDS_CONF_IRQ_RDY_ENABLE … int cw1200_data_read(struct cw1200_common *priv, void *buf, size_t buf_len); int cw1200_data_write(struct cw1200_common *priv, const void *buf, size_t buf_len); int cw1200_reg_read(struct cw1200_common *priv, u16 addr, void *buf, size_t buf_len); int cw1200_reg_write(struct cw1200_common *priv, u16 addr, const void *buf, size_t buf_len); static inline int cw1200_reg_read_16(struct cw1200_common *priv, u16 addr, u16 *val) { … } static inline int cw1200_reg_write_16(struct cw1200_common *priv, u16 addr, u16 val) { … } static inline int cw1200_reg_read_32(struct cw1200_common *priv, u16 addr, u32 *val) { … } static inline int cw1200_reg_write_32(struct cw1200_common *priv, u16 addr, u32 val) { … } int cw1200_indirect_read(struct cw1200_common *priv, u32 addr, void *buf, size_t buf_len, u32 prefetch, u16 port_addr); int cw1200_apb_write(struct cw1200_common *priv, u32 addr, const void *buf, size_t buf_len); static inline int cw1200_apb_read(struct cw1200_common *priv, u32 addr, void *buf, size_t buf_len) { … } static inline int cw1200_ahb_read(struct cw1200_common *priv, u32 addr, void *buf, size_t buf_len) { … } static inline int cw1200_apb_read_32(struct cw1200_common *priv, u32 addr, u32 *val) { … } static inline int cw1200_apb_write_32(struct cw1200_common *priv, u32 addr, u32 val) { … } static inline int cw1200_ahb_read_32(struct cw1200_common *priv, u32 addr, u32 *val) { … } #endif /* CW1200_HWIO_H_INCLUDED */
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