/* SPDX-License-Identifier: GPL-2.0-only * * Copyright (c) 2021, MediaTek Inc. * Copyright (c) 2021-2022, Intel Corporation. * * Authors: * Haijun Liu <[email protected]> * Moises Veleta <[email protected]> * Ricardo Martinez <[email protected]> * * Contributors: * Amir Hanania <[email protected]> * Andy Shevchenko <[email protected]> * Sreehari Kancharla <[email protected]> */ #ifndef __T7XX_CLDMA_H__ #define __T7XX_CLDMA_H__ #include <linux/bits.h> #include <linux/types.h> #define CLDMA_TXQ_NUM … #define CLDMA_RXQ_NUM … #define CLDMA_ALL_Q … /* Interrupt status bits */ #define EMPTY_STATUS_BITMASK … #define TXRX_STATUS_BITMASK … #define EQ_STA_BIT_OFFSET … #define L2_INT_BIT_COUNT … #define EQ_STA_BIT(index) … #define TQ_ERR_INT_BITMASK … #define TQ_ACTIVE_START_ERR_INT_BITMASK … #define RQ_ERR_INT_BITMASK … #define RQ_ACTIVE_START_ERR_INT_BITMASK … #define CLDMA0_AO_BASE … #define CLDMA0_PD_BASE … #define CLDMA1_AO_BASE … #define CLDMA1_PD_BASE … #define CLDMA_R_AO_BASE … #define CLDMA_R_PD_BASE … /* CLDMA TX */ #define REG_CLDMA_UL_START_ADDRL_0 … #define REG_CLDMA_UL_START_ADDRH_0 … #define REG_CLDMA_UL_CURRENT_ADDRL_0 … #define REG_CLDMA_UL_CURRENT_ADDRH_0 … #define REG_CLDMA_UL_STATUS … #define REG_CLDMA_UL_START_CMD … #define REG_CLDMA_UL_RESUME_CMD … #define REG_CLDMA_UL_STOP_CMD … #define REG_CLDMA_UL_ERROR … #define REG_CLDMA_UL_CFG … #define UL_CFG_BIT_MODE_36 … #define UL_CFG_BIT_MODE_40 … #define UL_CFG_BIT_MODE_64 … #define UL_CFG_BIT_MODE_MASK … #define REG_CLDMA_UL_MEM … #define UL_MEM_CHECK_DIS … /* CLDMA RX */ #define REG_CLDMA_DL_START_CMD … #define REG_CLDMA_DL_RESUME_CMD … #define REG_CLDMA_DL_STOP_CMD … #define REG_CLDMA_DL_MEM … #define DL_MEM_CHECK_DIS … #define REG_CLDMA_DL_CFG … #define DL_CFG_UP_HW_LAST … #define DL_CFG_BIT_MODE_36 … #define DL_CFG_BIT_MODE_40 … #define DL_CFG_BIT_MODE_64 … #define DL_CFG_BIT_MODE_MASK … #define REG_CLDMA_DL_START_ADDRL_0 … #define REG_CLDMA_DL_START_ADDRH_0 … #define REG_CLDMA_DL_CURRENT_ADDRL_0 … #define REG_CLDMA_DL_CURRENT_ADDRH_0 … #define REG_CLDMA_DL_STATUS … /* CLDMA MISC */ #define REG_CLDMA_L2TISAR0 … #define REG_CLDMA_L2TISAR1 … #define REG_CLDMA_L2TIMR0 … #define REG_CLDMA_L2TIMR1 … #define REG_CLDMA_L2TIMCR0 … #define REG_CLDMA_L2TIMCR1 … #define REG_CLDMA_L2TIMSR0 … #define REG_CLDMA_L2TIMSR1 … #define REG_CLDMA_L3TISAR0 … #define REG_CLDMA_L3TISAR1 … #define REG_CLDMA_L2RISAR0 … #define REG_CLDMA_L2RISAR1 … #define REG_CLDMA_L3RISAR0 … #define REG_CLDMA_L3RISAR1 … #define REG_CLDMA_IP_BUSY … #define IP_BUSY_WAKEUP … #define CLDMA_L2TISAR0_ALL_INT_MASK … #define CLDMA_L2RISAR0_ALL_INT_MASK … /* CLDMA MISC */ #define REG_CLDMA_L2RIMR0 … #define REG_CLDMA_L2RIMR1 … #define REG_CLDMA_L2RIMCR0 … #define REG_CLDMA_L2RIMCR1 … #define REG_CLDMA_L2RIMSR0 … #define REG_CLDMA_L2RIMSR1 … #define REG_CLDMA_BUSY_MASK … #define BUSY_MASK_PCIE … #define BUSY_MASK_AP … #define BUSY_MASK_MD … #define REG_CLDMA_INT_MASK … /* CLDMA RESET */ #define REG_INFRA_RST4_SET … #define RST4_CLDMA1_SW_RST_SET … #define REG_INFRA_RST4_CLR … #define RST4_CLDMA1_SW_RST_CLR … #define REG_INFRA_RST2_SET … #define RST2_PMIC_SW_RST_SET … #define REG_INFRA_RST2_CLR … #define RST2_PMIC_SW_RST_CLR … enum mtk_txrx { … }; enum t7xx_hw_mode { … }; struct t7xx_cldma_hw { … }; void t7xx_cldma_hw_irq_dis_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_irq_dis_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_irq_en_txrx(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_irq_en_eq(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); unsigned int t7xx_cldma_hw_queue_status(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_init(struct t7xx_cldma_hw *hw_info); void t7xx_cldma_hw_resume_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_start(struct t7xx_cldma_hw *hw_info); void t7xx_cldma_hw_start_queue(struct t7xx_cldma_hw *hw_info, unsigned int qno, enum mtk_txrx tx_rx); void t7xx_cldma_hw_tx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); void t7xx_cldma_hw_rx_done(struct t7xx_cldma_hw *hw_info, unsigned int bitmask); void t7xx_cldma_hw_stop_all_qs(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); void t7xx_cldma_hw_set_start_addr(struct t7xx_cldma_hw *hw_info, unsigned int qno, u64 address, enum mtk_txrx tx_rx); void t7xx_cldma_hw_reset(void __iomem *ao_base); void t7xx_cldma_hw_stop(struct t7xx_cldma_hw *hw_info, enum mtk_txrx tx_rx); unsigned int t7xx_cldma_hw_int_status(struct t7xx_cldma_hw *hw_info, unsigned int bitmask, enum mtk_txrx tx_rx); void t7xx_cldma_hw_restore(struct t7xx_cldma_hw *hw_info); void t7xx_cldma_clear_ip_busy(struct t7xx_cldma_hw *hw_info); bool t7xx_cldma_tx_addr_is_set(struct t7xx_cldma_hw *hw_info, unsigned int qno); #endif
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