// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2021, MediaTek Inc. * Copyright (c) 2021-2022, Intel Corporation. * * Authors: * Amir Hanania <[email protected]> * Haijun Liu <[email protected]> * Moises Veleta <[email protected]> * Ricardo Martinez <[email protected]> * * Contributors: * Andy Shevchenko <[email protected]> * Chiranjeevi Rapolu <[email protected]> * Eliot Lee <[email protected]> * Sreehari Kancharla <[email protected]> */ #include <linux/bits.h> #include <linux/bitfield.h> #include <linux/bitops.h> #include <linux/delay.h> #include <linux/dev_printk.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/types.h> #include "t7xx_dpmaif.h" #include "t7xx_reg.h" #define ioread32_poll_timeout_atomic(addr, val, cond, delay_us, timeout_us) … static int t7xx_dpmaif_init_intr(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_mask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } void t7xx_dpmaif_unmask_ulq_intr(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } void t7xx_dpmaif_dl_unmask_batcnt_len_err_intr(struct dpmaif_hw_info *hw_info) { … } void t7xx_dpmaif_dl_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info) { … } static u32 t7xx_update_dlq_intr(struct dpmaif_hw_info *hw_info, u32 q_done) { … } static int t7xx_mask_dlq_intr(struct dpmaif_hw_info *hw_info, unsigned int qno) { … } void t7xx_dpmaif_dlq_unmask_rx_done(struct dpmaif_hw_info *hw_info, unsigned int qno) { … } void t7xx_dpmaif_clr_ip_busy_sts(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dlq_mask_rx_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info, unsigned int qno) { … } void t7xx_dpmaif_dlq_unmask_pitcnt_len_err_intr(struct dpmaif_hw_info *hw_info, unsigned int qno) { … } void t7xx_dpmaif_ul_clr_all_intr(struct dpmaif_hw_info *hw_info) { … } void t7xx_dpmaif_dl_clr_all_intr(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_set_intr_para(struct dpmaif_hw_intr_st_para *para, enum dpmaif_hw_intr_type intr_type, unsigned int intr_queue) { … } /* The para->intr_cnt counter is set to zero before this function is called. * It does not check for overflow as there is no risk of overflowing intr_types or intr_queues. */ static void t7xx_dpmaif_hw_check_tx_intr(struct dpmaif_hw_info *hw_info, unsigned int intr_status, struct dpmaif_hw_intr_st_para *para) { … } /* The para->intr_cnt counter is set to zero before this function is called. * It does not check for overflow as there is no risk of overflowing intr_types or intr_queues. */ static void t7xx_dpmaif_hw_check_rx_intr(struct dpmaif_hw_info *hw_info, unsigned int intr_status, struct dpmaif_hw_intr_st_para *para, int qno) { … } /** * t7xx_dpmaif_hw_get_intr_cnt() - Reads interrupt status and count from HW. * @hw_info: Pointer to struct hw_info. * @para: Pointer to struct dpmaif_hw_intr_st_para. * @qno: Queue number. * * Reads RX/TX interrupt status from HW and clears UL/DL status as needed. * * Return: Interrupt count. */ int t7xx_dpmaif_hw_get_intr_cnt(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_intr_st_para *para, int qno) { … } static int t7xx_dpmaif_sram_init(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_reset(struct dpmaif_hw_info *hw_info) { … } static int t7xx_dpmaif_hw_config(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_pcie_dpmaif_sign(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_performance(struct dpmaif_hw_info *hw_info) { … } /* DPMAIF DL DLQ part HW setting */ static void t7xx_dpmaif_hw_hpc_cntl_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_agg_cfg_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_hash_bit_choose_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_mid_pit_timeout_thres_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_dlq_timeout_thres_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_hw_dlq_start_prs_thres_set(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_dlq_hpc_hw_init(struct dpmaif_hw_info *hw_info) { … } static int t7xx_dpmaif_dl_bat_init_done(struct dpmaif_hw_info *hw_info, bool frg_en) { … } static void t7xx_dpmaif_dl_set_bat_base_addr(struct dpmaif_hw_info *hw_info, dma_addr_t addr) { … } static void t7xx_dpmaif_dl_set_bat_size(struct dpmaif_hw_info *hw_info, unsigned int size) { … } static void t7xx_dpmaif_dl_bat_en(struct dpmaif_hw_info *hw_info, bool enable) { … } static void t7xx_dpmaif_dl_set_ao_bid_maxcnt(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_mtu(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_pit_chknum(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_remain_minsz(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_bat_bufsz(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_bat_rsv_length(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_pkt_alignment(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_pkt_checksum(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_frg_check_thres(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_ao_frg_bufsz(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_frg_ao_en(struct dpmaif_hw_info *hw_info, bool enable) { … } static void t7xx_dpmaif_dl_set_ao_bat_check_thres(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_pit_seqnum(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_set_dlq_pit_base_addr(struct dpmaif_hw_info *hw_info, dma_addr_t addr) { … } static void t7xx_dpmaif_dl_set_dlq_pit_size(struct dpmaif_hw_info *hw_info, unsigned int size) { … } static void t7xx_dpmaif_dl_dlq_pit_en(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_dlq_pit_init_done(struct dpmaif_hw_info *hw_info, unsigned int pit_idx) { … } static void t7xx_dpmaif_config_dlq_pit_hw(struct dpmaif_hw_info *hw_info, unsigned int q_num, struct dpmaif_dl *dl_que) { … } static void t7xx_dpmaif_config_all_dlq_hw(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_dl_all_q_en(struct dpmaif_hw_info *hw_info, bool enable) { … } static int t7xx_dpmaif_config_dlq_hw(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_ul_update_drb_size(struct dpmaif_hw_info *hw_info, unsigned int q_num, unsigned int size) { … } static void t7xx_dpmaif_ul_update_drb_base_addr(struct dpmaif_hw_info *hw_info, unsigned int q_num, dma_addr_t addr) { … } static void t7xx_dpmaif_ul_rdy_en(struct dpmaif_hw_info *hw_info, unsigned int q_num, bool ready) { … } static void t7xx_dpmaif_ul_arb_en(struct dpmaif_hw_info *hw_info, unsigned int q_num, bool enable) { … } static void t7xx_dpmaif_config_ulq_hw(struct dpmaif_hw_info *hw_info) { … } static int t7xx_dpmaif_hw_init_done(struct dpmaif_hw_info *hw_info) { … } static bool t7xx_dpmaif_dl_idle_check(struct dpmaif_hw_info *hw_info) { … } static void t7xx_dpmaif_ul_all_q_en(struct dpmaif_hw_info *hw_info, bool enable) { … } static bool t7xx_dpmaif_ul_idle_check(struct dpmaif_hw_info *hw_info) { … } void t7xx_dpmaif_ul_update_hw_drb_cnt(struct dpmaif_hw_info *hw_info, unsigned int q_num, unsigned int drb_entry_cnt) { … } unsigned int t7xx_dpmaif_ul_get_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } int t7xx_dpmaif_dlq_add_pit_remain_cnt(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx, unsigned int pit_remain_cnt) { … } unsigned int t7xx_dpmaif_dl_dlq_pit_get_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int dlq_pit_idx) { … } static int t7xx_dl_add_timedout(struct dpmaif_hw_info *hw_info) { … } int t7xx_dpmaif_dl_snd_hw_bat_cnt(struct dpmaif_hw_info *hw_info, unsigned int bat_entry_cnt) { … } unsigned int t7xx_dpmaif_dl_get_bat_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } unsigned int t7xx_dpmaif_dl_get_bat_wr_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } int t7xx_dpmaif_dl_snd_hw_frg_cnt(struct dpmaif_hw_info *hw_info, unsigned int frg_entry_cnt) { … } unsigned int t7xx_dpmaif_dl_get_frg_rd_idx(struct dpmaif_hw_info *hw_info, unsigned int q_num) { … } static void t7xx_dpmaif_set_queue_property(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_para) { … } /** * t7xx_dpmaif_hw_stop_all_txq() - Stop all TX queues. * @hw_info: Pointer to struct hw_info. * * Disable HW UL queues. Checks busy UL queues to go to idle * with an attempt count of 1000000. * * Return: * * 0 - Success * * -ETIMEDOUT - Timed out checking busy queues */ int t7xx_dpmaif_hw_stop_all_txq(struct dpmaif_hw_info *hw_info) { … } /** * t7xx_dpmaif_hw_stop_all_rxq() - Stop all RX queues. * @hw_info: Pointer to struct hw_info. * * Disable HW DL queue. Checks busy UL queues to go to idle * with an attempt count of 1000000. * Check that HW PIT write index equals read index with the same * attempt count. * * Return: * * 0 - Success. * * -ETIMEDOUT - Timed out checking busy queues. */ int t7xx_dpmaif_hw_stop_all_rxq(struct dpmaif_hw_info *hw_info) { … } void t7xx_dpmaif_start_hw(struct dpmaif_hw_info *hw_info) { … } /** * t7xx_dpmaif_hw_init() - Initialize HW data path API. * @hw_info: Pointer to struct hw_info. * @init_param: Pointer to struct dpmaif_hw_params. * * Configures port mode, clock config, HW interrupt initialization, and HW queue. * * Return: * * 0 - Success. * * -ERROR - Error code from failure sub-initializations. */ int t7xx_dpmaif_hw_init(struct dpmaif_hw_info *hw_info, struct dpmaif_hw_params *init_param) { … } bool t7xx_dpmaif_ul_clr_done(struct dpmaif_hw_info *hw_info, unsigned int qno) { … }
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