// SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. */ #include <linux/signal.h> #include <linux/slab.h> #include <linux/module.h> #include <linux/netdevice.h> #include <linux/etherdevice.h> #include <linux/mii.h> #include <linux/ethtool.h> #include <linux/phy.h> #include <linux/usb.h> #include <linux/crc32.h> #include <linux/if_vlan.h> #include <linux/uaccess.h> #include <linux/list.h> #include <linux/ip.h> #include <linux/ipv6.h> #include <net/ip6_checksum.h> #include <uapi/linux/mdio.h> #include <linux/mdio.h> #include <linux/usb/cdc.h> #include <linux/suspend.h> #include <linux/atomic.h> #include <linux/acpi.h> #include <linux/firmware.h> #include <crypto/hash.h> #include <linux/usb/r8152.h> #include <net/gso.h> /* Information for net-next */ #define NETNEXT_VERSION … /* Information for net */ #define NET_VERSION … #define DRIVER_VERSION … #define DRIVER_AUTHOR … #define DRIVER_DESC … #define MODULENAME … #define R8152_PHY_ID … #define PLA_IDR … #define PLA_RCR … #define PLA_RCR1 … #define PLA_RMS … #define PLA_RXFIFO_CTRL0 … #define PLA_RXFIFO_FULL … #define PLA_RXFIFO_CTRL1 … #define PLA_RX_FIFO_FULL … #define PLA_RXFIFO_CTRL2 … #define PLA_RX_FIFO_EMPTY … #define PLA_DMY_REG0 … #define PLA_FMC … #define PLA_CFG_WOL … #define PLA_TEREDO_CFG … #define PLA_TEREDO_WAKE_BASE … #define PLA_MAR … #define PLA_BACKUP … #define PLA_BDC_CR … #define PLA_TEREDO_TIMER … #define PLA_REALWOW_TIMER … #define PLA_UPHY_TIMER … #define PLA_SUSPEND_FLAG … #define PLA_INDICATE_FALG … #define PLA_MACDBG_PRE … #define PLA_MACDBG_POST … #define PLA_EXTRA_STATUS … #define PLA_GPHY_CTRL … #define PLA_POL_GPIO_CTRL … #define PLA_EFUSE_DATA … #define PLA_EFUSE_CMD … #define PLA_LEDSEL … #define PLA_LED_FEATURE … #define PLA_PHYAR … #define PLA_BOOT_CTRL … #define PLA_LWAKE_CTRL_REG … #define PLA_GPHY_INTR_IMR … #define PLA_EEE_CR … #define PLA_EEE_TXTWSYS … #define PLA_EEE_TXTWSYS_2P5G … #define PLA_EEEP_CR … #define PLA_MAC_PWR_CTRL … #define PLA_MAC_PWR_CTRL2 … #define PLA_MAC_PWR_CTRL3 … #define PLA_MAC_PWR_CTRL4 … #define PLA_WDT6_CTRL … #define PLA_TCR0 … #define PLA_TCR1 … #define PLA_MTPS … #define PLA_TXFIFO_CTRL … #define PLA_TXFIFO_FULL … #define PLA_RSTTALLY … #define PLA_CR … #define PLA_CRWECR … #define PLA_CONFIG12 … #define PLA_CONFIG34 … #define PLA_CONFIG5 … #define PLA_PHY_PWR … #define PLA_OOB_CTRL … #define PLA_CPCR … #define PLA_MISC_0 … #define PLA_MISC_1 … #define PLA_OCP_GPHY_BASE … #define PLA_TALLYCNT … #define PLA_SFF_STS_7 … #define PLA_PHYSTATUS … #define PLA_CONFIG6 … #define PLA_USB_CFG … #define PLA_BP_BA … #define PLA_BP_0 … #define PLA_BP_1 … #define PLA_BP_2 … #define PLA_BP_3 … #define PLA_BP_4 … #define PLA_BP_5 … #define PLA_BP_6 … #define PLA_BP_7 … #define PLA_BP_EN … #define USB_USB2PHY … #define USB_SSPHYLINK1 … #define USB_SSPHYLINK2 … #define USB_L1_CTRL … #define USB_U2P3_CTRL … #define USB_CSR_DUMMY1 … #define USB_CSR_DUMMY2 … #define USB_DEV_STAT … #define USB_CONNECT_TIMER … #define USB_MSC_TIMER … #define USB_BURST_SIZE … #define USB_FW_FIX_EN0 … #define USB_FW_FIX_EN1 … #define USB_LPM_CONFIG … #define USB_ECM_OPTION … #define USB_CSTMR … #define USB_MISC_2 … #define USB_ECM_OP … #define USB_GPHY_CTRL … #define USB_SPEED_OPTION … #define USB_FW_CTRL … #define USB_FC_TIMER … #define USB_USB_CTRL … #define USB_PHY_CTRL … #define USB_TX_AGG … #define USB_RX_BUF_TH … #define USB_USB_TIMER … #define USB_RX_EARLY_TIMEOUT … #define USB_RX_EARLY_SIZE … #define USB_PM_CTRL_STATUS … #define USB_RX_EXTRA_AGGR_TMR … #define USB_TX_DMA … #define USB_UPT_RXDMA_OWN … #define USB_UPHY3_MDCMDIO … #define USB_TOLERANCE … #define USB_LPM_CTRL … #define USB_BMU_RESET … #define USB_BMU_CONFIG … #define USB_U1U2_TIMER … #define USB_FW_TASK … #define USB_RX_AGGR_NUM … #define USB_UPS_CTRL … #define USB_POWER_CUT … #define USB_MISC_0 … #define USB_MISC_1 … #define USB_AFE_CTRL2 … #define USB_UPHY_XTAL … #define USB_UPS_CFG … #define USB_UPS_FLAGS … #define USB_WDT1_CTRL … #define USB_WDT11_CTRL … #define USB_BP_BA … #define USB_BP_0 … #define USB_BP_1 … #define USB_BP_2 … #define USB_BP_3 … #define USB_BP_4 … #define USB_BP_5 … #define USB_BP_6 … #define USB_BP_7 … #define USB_BP_EN … #define USB_BP_8 … #define USB_BP_9 … #define USB_BP_10 … #define USB_BP_11 … #define USB_BP_12 … #define USB_BP_13 … #define USB_BP_14 … #define USB_BP_15 … #define USB_BP2_EN … /* OCP Registers */ #define OCP_ALDPS_CONFIG … #define OCP_EEE_CONFIG1 … #define OCP_EEE_CONFIG2 … #define OCP_EEE_CONFIG3 … #define OCP_BASE_MII … #define OCP_EEE_AR … #define OCP_EEE_DATA … #define OCP_PHY_STATUS … #define OCP_INTR_EN … #define OCP_NCTL_CFG … #define OCP_POWER_CFG … #define OCP_EEE_CFG … #define OCP_SRAM_ADDR … #define OCP_SRAM_DATA … #define OCP_DOWN_SPEED … #define OCP_EEE_ABLE … #define OCP_EEE_ADV … #define OCP_EEE_LPABLE … #define OCP_10GBT_CTRL … #define OCP_10GBT_STAT … #define OCP_EEE_ADV2 … #define OCP_PHY_STATE … #define OCP_PHY_PATCH_STAT … #define OCP_PHY_PATCH_CMD … #define OCP_PHY_LOCK … #define OCP_ADC_IOFFSET … #define OCP_ADC_CFG … #define OCP_SYSCLK_CFG … /* SRAM Register */ #define SRAM_GREEN_CFG … #define SRAM_LPF_CFG … #define SRAM_GPHY_FW_VER … #define SRAM_10M_AMP1 … #define SRAM_10M_AMP2 … #define SRAM_IMPEDANCE … #define SRAM_PHY_LOCK … /* PLA_RCR */ #define RCR_AAP … #define RCR_APM … #define RCR_AM … #define RCR_AB … #define RCR_ACPT_ALL … #define SLOT_EN … /* PLA_RCR1 */ #define OUTER_VLAN … #define INNER_VLAN … /* PLA_RXFIFO_CTRL0 */ #define RXFIFO_THR1_NORMAL … #define RXFIFO_THR1_OOB … /* PLA_RXFIFO_FULL */ #define RXFIFO_FULL_MASK … /* PLA_RXFIFO_CTRL1 */ #define RXFIFO_THR2_FULL … #define RXFIFO_THR2_HIGH … #define RXFIFO_THR2_OOB … #define RXFIFO_THR2_NORMAL … /* PLA_RXFIFO_CTRL2 */ #define RXFIFO_THR3_FULL … #define RXFIFO_THR3_HIGH … #define RXFIFO_THR3_OOB … #define RXFIFO_THR3_NORMAL … /* PLA_TXFIFO_CTRL */ #define TXFIFO_THR_NORMAL … #define TXFIFO_THR_NORMAL2 … /* PLA_DMY_REG0 */ #define ECM_ALDPS … /* PLA_FMC */ #define FMC_FCR_MCU_EN … /* PLA_EEEP_CR */ #define EEEP_CR_EEEP_TX … /* PLA_WDT6_CTRL */ #define WDT6_SET_MODE … /* PLA_TCR0 */ #define TCR0_TX_EMPTY … #define TCR0_AUTO_FIFO … /* PLA_TCR1 */ #define VERSION_MASK … #define IFG_MASK … #define IFG_144NS … #define IFG_96NS … /* PLA_MTPS */ #define MTPS_JUMBO … #define MTPS_DEFAULT … /* PLA_RSTTALLY */ #define TALLY_RESET … /* PLA_CR */ #define CR_RST … #define CR_RE … #define CR_TE … /* PLA_CRWECR */ #define CRWECR_NORAML … #define CRWECR_CONFIG … /* PLA_OOB_CTRL */ #define NOW_IS_OOB … #define TXFIFO_EMPTY … #define RXFIFO_EMPTY … #define LINK_LIST_READY … #define DIS_MCU_CLROOB … #define FIFO_EMPTY … /* PLA_MISC_1 */ #define RXDY_GATED_EN … /* PLA_SFF_STS_7 */ #define RE_INIT_LL … #define MCU_BORW_EN … /* PLA_CPCR */ #define FLOW_CTRL_EN … #define CPCR_RX_VLAN … /* PLA_CFG_WOL */ #define MAGIC_EN … /* PLA_TEREDO_CFG */ #define TEREDO_SEL … #define TEREDO_WAKE_MASK … #define TEREDO_RS_EVENT_MASK … #define OOB_TEREDO_EN … /* PLA_BDC_CR */ #define ALDPS_PROXY_MODE … /* PLA_EFUSE_CMD */ #define EFUSE_READ_CMD … #define EFUSE_DATA_BIT16 … /* PLA_CONFIG34 */ #define LINK_ON_WAKE_EN … #define LINK_OFF_WAKE_EN … /* PLA_CONFIG6 */ #define LANWAKE_CLR_EN … /* PLA_USB_CFG */ #define EN_XG_LIP … #define EN_G_LIP … /* PLA_CONFIG5 */ #define BWF_EN … #define MWF_EN … #define UWF_EN … #define LAN_WAKE_EN … /* PLA_LED_FEATURE */ #define LED_MODE_MASK … /* PLA_PHY_PWR */ #define TX_10M_IDLE_EN … #define PFM_PWM_SWITCH … #define TEST_IO_OFF … /* PLA_MAC_PWR_CTRL */ #define D3_CLK_GATED_EN … #define MCU_CLK_RATIO … #define MCU_CLK_RATIO_MASK … #define ALDPS_SPDWN_RATIO … /* PLA_MAC_PWR_CTRL2 */ #define EEE_SPDWN_RATIO … #define MAC_CLK_SPDWN_EN … #define EEE_SPDWN_RATIO_MASK … /* PLA_MAC_PWR_CTRL3 */ #define PLA_MCU_SPDWN_EN … #define PKT_AVAIL_SPDWN_EN … #define SUSPEND_SPDWN_EN … #define U1U2_SPDWN_EN … #define L1_SPDWN_EN … /* PLA_MAC_PWR_CTRL4 */ #define PWRSAVE_SPDWN_EN … #define RXDV_SPDWN_EN … #define TX10MIDLE_EN … #define IDLE_SPDWN_EN … #define TP100_SPDWN_EN … #define TP500_SPDWN_EN … #define TP1000_SPDWN_EN … #define EEE_SPDWN_EN … /* PLA_GPHY_INTR_IMR */ #define GPHY_STS_MSK … #define SPEED_DOWN_MSK … #define SPDWN_RXDV_MSK … #define SPDWN_LINKCHG_MSK … /* PLA_PHYAR */ #define PHYAR_FLAG … /* PLA_EEE_CR */ #define EEE_RX_EN … #define EEE_TX_EN … /* PLA_BOOT_CTRL */ #define AUTOLOAD_DONE … /* PLA_LWAKE_CTRL_REG */ #define LANWAKE_PIN … /* PLA_SUSPEND_FLAG */ #define LINK_CHG_EVENT … /* PLA_INDICATE_FALG */ #define UPCOMING_RUNTIME_D3 … /* PLA_MACDBG_PRE and PLA_MACDBG_POST */ #define DEBUG_OE … #define DEBUG_LTSSM … /* PLA_EXTRA_STATUS */ #define CUR_LINK_OK … #define U3P3_CHECK_EN … #define LINK_CHANGE_FLAG … #define POLL_LINK_CHG … /* PLA_GPHY_CTRL */ #define GPHY_FLASH … /* PLA_POL_GPIO_CTRL */ #define DACK_DET_EN … #define POL_GPHY_PATCH … /* USB_USB2PHY */ #define USB2PHY_SUSPEND … #define USB2PHY_L1 … /* USB_SSPHYLINK1 */ #define DELAY_PHY_PWR_CHG … /* USB_SSPHYLINK2 */ #define pwd_dn_scale_mask … #define pwd_dn_scale(x) … /* USB_CSR_DUMMY1 */ #define DYNAMIC_BURST … /* USB_CSR_DUMMY2 */ #define EP4_FULL_FC … /* USB_DEV_STAT */ #define STAT_SPEED_MASK … #define STAT_SPEED_HIGH … #define STAT_SPEED_FULL … /* USB_FW_FIX_EN0 */ #define FW_FIX_SUSPEND … /* USB_FW_FIX_EN1 */ #define FW_IP_RESET_EN … /* USB_LPM_CONFIG */ #define LPM_U1U2_EN … /* USB_TX_AGG */ #define TX_AGG_MAX_THRESHOLD … /* USB_RX_BUF_TH */ #define RX_THR_SUPPER … #define RX_THR_HIGH … #define RX_THR_SLOW … #define RX_THR_B … /* USB_TX_DMA */ #define TEST_MODE_DISABLE … #define TX_SIZE_ADJUST1 … /* USB_BMU_RESET */ #define BMU_RESET_EP_IN … #define BMU_RESET_EP_OUT … /* USB_BMU_CONFIG */ #define ACT_ODMA … /* USB_UPT_RXDMA_OWN */ #define OWN_UPDATE … #define OWN_CLEAR … /* USB_FW_TASK */ #define FC_PATCH_TASK … /* USB_RX_AGGR_NUM */ #define RX_AGGR_NUM_MASK … /* USB_UPS_CTRL */ #define POWER_CUT … /* USB_PM_CTRL_STATUS */ #define RESUME_INDICATE … /* USB_ECM_OPTION */ #define BYPASS_MAC_RESET … /* USB_CSTMR */ #define FORCE_SUPER … /* USB_MISC_2 */ #define UPS_FORCE_PWR_DOWN … /* USB_ECM_OP */ #define EN_ALL_SPEED … /* USB_GPHY_CTRL */ #define GPHY_PATCH_DONE … #define BYPASS_FLASH … #define BACKUP_RESTRORE … /* USB_SPEED_OPTION */ #define RG_PWRDN_EN … #define ALL_SPEED_OFF … /* USB_FW_CTRL */ #define FLOW_CTRL_PATCH_OPT … #define AUTO_SPEEDUP … #define FLOW_CTRL_PATCH_2 … /* USB_FC_TIMER */ #define CTRL_TIMER_EN … /* USB_USB_CTRL */ #define CDC_ECM_EN … #define RX_AGG_DISABLE … #define RX_ZERO_EN … /* USB_U2P3_CTRL */ #define U2P3_ENABLE … #define RX_DETECT8 … /* USB_POWER_CUT */ #define PWR_EN … #define PHASE2_EN … #define UPS_EN … #define USP_PREWAKE … /* USB_MISC_0 */ #define PCUT_STATUS … /* USB_RX_EARLY_TIMEOUT */ #define COALESCE_SUPER … #define COALESCE_HIGH … #define COALESCE_SLOW … /* USB_WDT1_CTRL */ #define WTD1_EN … /* USB_WDT11_CTRL */ #define TIMER11_EN … /* USB_LPM_CTRL */ /* bit 4 ~ 5: fifo empty boundary */ #define FIFO_EMPTY_1FB … /* bit 2 ~ 3: LMP timer */ #define LPM_TIMER_MASK … #define LPM_TIMER_500MS … #define LPM_TIMER_500US … #define ROK_EXIT_LPM … /* USB_AFE_CTRL2 */ #define SEN_VAL_MASK … #define SEN_VAL_NORMAL … #define SEL_RXIDLE … /* USB_UPHY_XTAL */ #define OOBS_POLLING … /* USB_UPS_CFG */ #define SAW_CNT_1MS_MASK … #define MID_REVERSE … /* USB_UPS_FLAGS */ #define UPS_FLAGS_R_TUNE … #define UPS_FLAGS_EN_10M_CKDIV … #define UPS_FLAGS_250M_CKDIV … #define UPS_FLAGS_EN_ALDPS … #define UPS_FLAGS_CTAP_SHORT_DIS … #define UPS_FLAGS_SPEED_MASK … #define ups_flags_speed(x) … #define UPS_FLAGS_EN_EEE … #define UPS_FLAGS_EN_500M_EEE … #define UPS_FLAGS_EN_EEE_CKDIV … #define UPS_FLAGS_EEE_PLLOFF_100 … #define UPS_FLAGS_EEE_PLLOFF_GIGA … #define UPS_FLAGS_EEE_CMOD_LV_EN … #define UPS_FLAGS_EN_GREEN … #define UPS_FLAGS_EN_FLOW_CTR … enum spd_duplex { … }; /* OCP_ALDPS_CONFIG */ #define ENPWRSAVE … #define ENPDNPS … #define LINKENA … #define DIS_SDSAVE … /* OCP_PHY_STATUS */ #define PHY_STAT_MASK … #define PHY_STAT_EXT_INIT … #define PHY_STAT_LAN_ON … #define PHY_STAT_PWRDN … /* OCP_INTR_EN */ #define INTR_SPEED_FORCE … /* OCP_NCTL_CFG */ #define PGA_RETURN_EN … /* OCP_POWER_CFG */ #define EEE_CLKDIV_EN … #define EN_ALDPS … #define EN_10M_PLLOFF … /* OCP_EEE_CONFIG1 */ #define RG_TXLPI_MSK_HFDUP … #define RG_MATCLR_EN … #define EEE_10_CAP … #define EEE_NWAY_EN … #define TX_QUIET_EN … #define RX_QUIET_EN … #define sd_rise_time_mask … #define sd_rise_time(x) … #define RG_RXLPI_MSK_HFDUP … #define SDFALLTIME … /* OCP_EEE_CONFIG2 */ #define RG_LPIHYS_NUM … #define RG_DACQUIET_EN … #define RG_LDVQUIET_EN … #define RG_CKRSEL … #define RG_EEEPRG_EN … /* OCP_EEE_CONFIG3 */ #define fast_snr_mask … #define fast_snr(x) … #define RG_LFS_SEL … #define MSK_PH … /* OCP_EEE_AR */ /* bit[15:14] function */ #define FUN_ADDR … #define FUN_DATA … /* bit[4:0] device addr */ /* OCP_EEE_CFG */ #define CTAP_SHORT_EN … #define EEE10_EN … /* OCP_DOWN_SPEED */ #define EN_EEE_CMODE … #define EN_EEE_1000 … #define EN_EEE_100 … #define EN_10M_CLKDIV … #define EN_10M_BGOFF … /* OCP_10GBT_CTRL */ #define RTL_ADV2_5G_F_R … /* OCP_PHY_STATE */ #define TXDIS_STATE … #define ABD_STATE … /* OCP_PHY_PATCH_STAT */ #define PATCH_READY … /* OCP_PHY_PATCH_CMD */ #define PATCH_REQUEST … /* OCP_PHY_LOCK */ #define PATCH_LOCK … /* OCP_ADC_CFG */ #define CKADSEL_L … #define ADC_EN … #define EN_EMI_L … /* OCP_SYSCLK_CFG */ #define sysclk_div_expo(x) … #define clk_div_expo(x) … /* SRAM_GREEN_CFG */ #define GREEN_ETH_EN … #define R_TUNE_EN … /* SRAM_LPF_CFG */ #define LPF_AUTO_TUNE … /* SRAM_10M_AMP1 */ #define GDAC_IB_UPALL … /* SRAM_10M_AMP2 */ #define AMP_DN … /* SRAM_IMPEDANCE */ #define RX_DRIVING_MASK … /* SRAM_PHY_LOCK */ #define PHY_PATCH_LOCK … /* MAC PASSTHRU */ #define AD_MASK … #define BND_MASK … #define BD_MASK … #define EFUSE … #define PASS_THRU_MASK … #define BP4_SUPER_ONLY … enum rtl_register_content { … }; #define is_speed_2500(_speed) … #define is_flow_control(_speed) … #define RTL8152_MAX_TX … #define RTL8152_MAX_RX … #define INTBUFSIZE … #define TX_ALIGN … #define RX_ALIGN … #define RTL8152_RX_MAX_PENDING … #define RTL8152_RXFG_HEADSZ … #define INTR_LINK … #define RTL8152_RMS … #define RTL8153_RMS … #define RTL8152_TX_TIMEOUT … #define mtu_to_size(m) … #define size_to_mtu(s) … #define rx_reserved_size(x) … /* rtl8152 flags */ enum rtl8152_flags { … }; #define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB … #define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK … #define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 … #define DEVICE_ID_THINKPAD_USB_C_DONGLE … #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 … #define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 … struct tally_counter { … }; struct rx_desc { … }; struct tx_desc { … }; struct r8152; struct rx_agg { … }; struct tx_agg { … }; struct r8152 { … }; /** * struct fw_block - block type and total length * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA, * RTL_FW_USB and so on. * @length: total length of the current block. */ struct fw_block { … } __packed; /** * struct fw_header - header of the firmware file * @checksum: checksum of sha256 which is calculated from the whole file * except the checksum field of the file. That is, calculate sha256 * from the version field to the end of the file. * @version: version of this firmware. * @blocks: the first firmware block of the file */ struct fw_header { … } __packed; enum rtl8152_fw_flags { … }; enum rtl8152_fw_fixup_cmd { … }; struct fw_phy_set { … } __packed; struct fw_phy_speed_up { … } __packed; struct fw_phy_ver { … } __packed; struct fw_phy_fixup { … } __packed; struct fw_phy_union { … } __packed; /** * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. * The layout of the firmware block is: * <struct fw_mac> + <info> + <firmware data>. * @blk_hdr: firmware descriptor (type, length) * @fw_offset: offset of the firmware binary data. The start address of * the data would be the address of struct fw_mac + @fw_offset. * @fw_reg: the register to load the firmware. Depends on chip. * @bp_ba_addr: the register to write break point base address. Depends on * chip. * @bp_ba_value: break point base address. Depends on chip. * @bp_en_addr: the register to write break point enabled mask. Depends * on chip. * @bp_en_value: break point enabled mask. Depends on the firmware. * @bp_start: the start register of break points. Depends on chip. * @bp_num: the break point number which needs to be set for this firmware. * Depends on the firmware. * @bp: break points. Depends on firmware. * @reserved: reserved space (unused) * @fw_ver_reg: the register to store the fw version. * @fw_ver_data: the firmware version of the current type. * @info: additional information for debugging, and is followed by the * binary data of firmware. */ struct fw_mac { … } __packed; /** * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. * This is used to set patch key when loading the firmware of PHY. * @blk_hdr: firmware descriptor (type, length) * @key_reg: the register to write the patch key. * @key_data: patch key. * @reserved: reserved space (unused) */ struct fw_phy_patch_key { … } __packed; /** * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. * The layout of the firmware block is: * <struct fw_phy_nc> + <info> + <firmware data>. * @blk_hdr: firmware descriptor (type, length) * @fw_offset: offset of the firmware binary data. The start address of * the data would be the address of struct fw_phy_nc + @fw_offset. * @fw_reg: the register to load the firmware. Depends on chip. * @ba_reg: the register to write the base address. Depends on chip. * @ba_data: base address. Depends on chip. * @patch_en_addr: the register of enabling patch mode. Depends on chip. * @patch_en_value: patch mode enabled mask. Depends on the firmware. * @mode_reg: the regitster of switching the mode. * @mode_pre: the mode needing to be set before loading the firmware. * @mode_post: the mode to be set when finishing to load the firmware. * @reserved: reserved space (unused) * @bp_start: the start register of break points. Depends on chip. * @bp_num: the break point number which needs to be set for this firmware. * Depends on the firmware. * @bp: break points. Depends on firmware. * @info: additional information for debugging, and is followed by the * binary data of firmware. */ struct fw_phy_nc { … } __packed; enum rtl_fw_type { … }; enum rtl_version { … }; enum tx_csum_stat { … }; #define RTL_ADVERTISED_10_HALF … #define RTL_ADVERTISED_10_FULL … #define RTL_ADVERTISED_100_HALF … #define RTL_ADVERTISED_100_FULL … #define RTL_ADVERTISED_1000_HALF … #define RTL_ADVERTISED_1000_FULL … #define RTL_ADVERTISED_2500_FULL … /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). * The RTL chips use a 64 element hash table based on the Ethernet CRC. */ static const int multicast_filter_limit = …; static unsigned int agg_buf_sz = …; #define RTL_LIMITED_TSO_SIZE … /* If register access fails then we block access and issue a reset. If this * happens too many times in a row without a successful access then we stop * trying to reset and just leave access blocked. */ #define REGISTER_ACCESS_MAX_RESETS … static void rtl_set_inaccessible(struct r8152 *tp) { … } static void rtl_set_accessible(struct r8152 *tp) { … } static int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request, __u8 requesttype, __u16 value, __u16 index, void *data, __u16 size, const char *msg_tag) { … } static int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) { … } static int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) { … } static void rtl_set_unplug(struct r8152 *tp) { … } static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data, u16 type) { … } static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data, u16 type) { … } static inline int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) { … } static inline int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) { … } static inline int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) { … } static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) { … } static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) { … } static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) { … } static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) { … } static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) { … } static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) { … } static u16 ocp_reg_read(struct r8152 *tp, u16 addr) { … } static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) { … } static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) { … } static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) { … } static void sram_write(struct r8152 *tp, u16 addr, u16 data) { … } static u16 sram_read(struct r8152 *tp, u16 addr) { … } static int read_mii_word(struct net_device *netdev, int phy_id, int reg) { … } static void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) { … } static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, u32 advertising); static int __rtl8152_set_mac_address(struct net_device *netdev, void *p, bool in_resume) { … } static int rtl8152_set_mac_address(struct net_device *netdev, void *p) { … } /* Devices containing proper chips can support a persistent * host system provided MAC address. * Examples of this are Dell TB15 and Dell WD15 docks */ static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa) { … } static int determine_ethernet_addr(struct r8152 *tp, struct sockaddr *sa) { … } static int set_ethernet_addr(struct r8152 *tp, bool in_resume) { … } static void read_bulk_callback(struct urb *urb) { … } static void write_bulk_callback(struct urb *urb) { … } static void intr_callback(struct urb *urb) { … } static inline void *rx_agg_align(void *data) { … } static inline void *tx_agg_align(void *data) { … } static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) { … } static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) { … } static void free_all_mem(struct r8152 *tp) { … } static int alloc_all_mem(struct r8152 *tp) { … } static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) { … } /* r8152_csum_workaround() * The hw limits the value of the transport offset. When the offset is out of * range, calculate the checksum by sw. */ static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, struct sk_buff_head *list) { … } static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) { … } static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) { … } static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, struct sk_buff *skb, u32 len) { … } static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) { … } static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) { … } static inline bool rx_count_exceed(struct r8152 *tp) { … } static inline int agg_offset(struct rx_agg *agg, void *addr) { … } static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) { … } static int rx_bottom(struct r8152 *tp, int budget) { … } static void tx_bottom(struct r8152 *tp) { … } static void bottom_half(struct tasklet_struct *t) { … } static int r8152_poll(struct napi_struct *napi, int budget) { … } static int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) { … } static void rtl_drop_queued_tx(struct r8152 *tp) { … } static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue) { … } static void rtl8152_set_rx_mode(struct net_device *netdev) { … } static void _rtl8152_set_rx_mode(struct net_device *netdev) { … } static netdev_features_t rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, netdev_features_t features) { … } static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, struct net_device *netdev) { … } static void r8152b_reset_packet_filter(struct r8152 *tp) { … } static void rtl8152_nic_reset(struct r8152 *tp) { … } static void set_tx_qlen(struct r8152 *tp) { … } static inline u16 rtl8152_get_speed(struct r8152 *tp) { … } static void rtl_eee_plus_en(struct r8152 *tp, bool enable) { … } static void rtl_set_eee_plus(struct r8152 *tp) { … } static void rxdy_gated_en(struct r8152 *tp, bool enable) { … } static int rtl_start_rx(struct r8152 *tp) { … } static int rtl_stop_rx(struct r8152 *tp) { … } static void rtl_set_ifg(struct r8152 *tp, u16 speed) { … } static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) { … } static int rtl_enable(struct r8152 *tp) { … } static int rtl8152_enable(struct r8152 *tp) { … } static void r8153_set_rx_early_timeout(struct r8152 *tp) { … } static void r8153_set_rx_early_size(struct r8152 *tp) { … } static int rtl8153_enable(struct r8152 *tp) { … } static void rtl_disable(struct r8152 *tp) { … } static void r8152_power_cut_en(struct r8152 *tp, bool enable) { … } static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) { … } static int rtl8152_set_features(struct net_device *dev, netdev_features_t features) { … } #define WAKE_ANY … static u32 __rtl_get_wol(struct r8152 *tp) { … } static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) { … } static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) { … } static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) { … } static void r8153_u1u2en(struct r8152 *tp, bool enable) { … } static void r8153b_u1u2en(struct r8152 *tp, bool enable) { … } static void r8153_u2p3en(struct r8152 *tp, bool enable) { … } static void r8153b_ups_flags(struct r8152 *tp) { … } static void r8156_ups_flags(struct r8152 *tp) { … } static void rtl_green_en(struct r8152 *tp, bool enable) { … } static void r8153b_green_en(struct r8152 *tp, bool enable) { … } static u16 r8153_phy_status(struct r8152 *tp, u16 desired) { … } static void r8153b_ups_en(struct r8152 *tp, bool enable) { … } static void r8153c_ups_en(struct r8152 *tp, bool enable) { … } static void r8156_ups_en(struct r8152 *tp, bool enable) { … } static void r8153_power_cut_en(struct r8152 *tp, bool enable) { … } static void r8153b_power_cut_en(struct r8152 *tp, bool enable) { … } static void r8153_queue_wake(struct r8152 *tp, bool enable) { … } static bool rtl_can_wakeup(struct r8152 *tp) { … } static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) { … } static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) { … } static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) { … } static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) { … } static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) { … } static void r8153_teredo_off(struct r8152 *tp) { … } static void rtl_reset_bmu(struct r8152 *tp) { … } /* Clear the bp to stop the firmware before loading a new one */ static void rtl_clear_bp(struct r8152 *tp, u16 type) { … } static inline void rtl_reset_ocp_base(struct r8152 *tp) { … } static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) { … } static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) { … } static int rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) { … } static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) { … } static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) { … } static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) { … } static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) { … } static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) { … } static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) { … } static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac) { … } /* Verify the checksum for the firmware file. It is calculated from the version * field to the end of the file. Compare the result with the checksum field to * make sure the file is correct. */ static long rtl8152_fw_verify_checksum(struct r8152 *tp, struct fw_header *fw_hdr, size_t size) { … } static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw) { … } static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) { … } static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) { … } static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) { … } static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) { … } static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) { … } static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) { … } static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) { … } static void rtl8152_release_firmware(struct r8152 *tp) { … } static int rtl8152_request_firmware(struct r8152 *tp) { … } static void r8152_aldps_en(struct r8152 *tp, bool enable) { … } static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) { … } static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) { … } static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) { … } static void r8152_eee_en(struct r8152 *tp, bool enable) { … } static void r8153_eee_en(struct r8152 *tp, bool enable) { … } static void r8156_eee_en(struct r8152 *tp, bool enable) { … } static void rtl_eee_enable(struct r8152 *tp, bool enable) { … } static void r8152b_enable_fc(struct r8152 *tp) { … } static void rtl8152_disable(struct r8152 *tp) { … } static void r8152b_hw_phy_cfg(struct r8152 *tp) { … } static void wait_oob_link_list_ready(struct r8152 *tp) { … } static void r8156b_wait_loading_flash(struct r8152 *tp) { … } static void r8152b_exit_oob(struct r8152 *tp) { … } static void r8152b_enter_oob(struct r8152 *tp) { … } static int r8153_pre_firmware_1(struct r8152 *tp) { … } static int r8153_post_firmware_1(struct r8152 *tp) { … } static int r8153_pre_firmware_2(struct r8152 *tp) { … } static int r8153_post_firmware_2(struct r8152 *tp) { … } static int r8153_post_firmware_3(struct r8152 *tp) { … } static int r8153b_pre_firmware_1(struct r8152 *tp) { … } static int r8153b_post_firmware_1(struct r8152 *tp) { … } static int r8153c_post_firmware_1(struct r8152 *tp) { … } static int r8156a_post_firmware_1(struct r8152 *tp) { … } static void r8153_aldps_en(struct r8152 *tp, bool enable) { … } static void r8153_hw_phy_cfg(struct r8152 *tp) { … } static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) { … } static void r8153b_hw_phy_cfg(struct r8152 *tp) { … } static void r8153c_hw_phy_cfg(struct r8152 *tp) { … } static void rtl8153_change_mtu(struct r8152 *tp) { … } static void r8153_first_init(struct r8152 *tp) { … } static void r8153_enter_oob(struct r8152 *tp) { … } static void rtl8153_disable(struct r8152 *tp) { … } static u32 fc_pause_on_auto(struct r8152 *tp) { … } static u32 fc_pause_off_auto(struct r8152 *tp) { … } static void r8156_fc_parameter(struct r8152 *tp) { … } static int rtl8156_enable(struct r8152 *tp) { … } static void rtl8156_disable(struct r8152 *tp) { … } static int rtl8156b_enable(struct r8152 *tp) { … } static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, u32 advertising) { … } static void rtl8152_up(struct r8152 *tp) { … } static void rtl8152_down(struct r8152 *tp) { … } static void rtl8153_up(struct r8152 *tp) { … } static void rtl8153_down(struct r8152 *tp) { … } static void rtl8153b_up(struct r8152 *tp) { … } static void rtl8153b_down(struct r8152 *tp) { … } static void rtl8153c_change_mtu(struct r8152 *tp) { … } static void rtl8153c_up(struct r8152 *tp) { … } static void rtl8156_change_mtu(struct r8152 *tp) { … } static void rtl8156_up(struct r8152 *tp) { … } static void rtl8156_down(struct r8152 *tp) { … } static bool rtl8152_in_nway(struct r8152 *tp) { … } static bool rtl8153_in_nway(struct r8152 *tp) { … } static void r8156_mdio_force_mode(struct r8152 *tp) { … } static void set_carrier(struct r8152 *tp) { … } static void rtl_work_func_t(struct work_struct *work) { … } static void rtl_hw_phy_work_func_t(struct work_struct *work) { … } #ifdef CONFIG_PM_SLEEP static int rtl_notifier(struct notifier_block *nb, unsigned long action, void *data) { … } #endif static int rtl8152_open(struct net_device *netdev) { … } static int rtl8152_close(struct net_device *netdev) { … } static void rtl_tally_reset(struct r8152 *tp) { … } static void r8152b_init(struct r8152 *tp) { … } static void r8153_init(struct r8152 *tp) { … } static void r8153b_init(struct r8152 *tp) { … } static void r8153c_init(struct r8152 *tp) { … } static void r8156_hw_phy_cfg(struct r8152 *tp) { … } static void r8156b_hw_phy_cfg(struct r8152 *tp) { … } static void r8156_init(struct r8152 *tp) { … } static void r8156b_init(struct r8152 *tp) { … } static bool rtl_check_vendor_ok(struct usb_interface *intf) { … } static int rtl8152_pre_reset(struct usb_interface *intf) { … } static int rtl8152_post_reset(struct usb_interface *intf) { … } static bool delay_autosuspend(struct r8152 *tp) { … } static int rtl8152_runtime_resume(struct r8152 *tp) { … } static int rtl8152_system_resume(struct r8152 *tp) { … } static int rtl8152_runtime_suspend(struct r8152 *tp) { … } static int rtl8152_system_suspend(struct r8152 *tp) { … } static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) { … } static int rtl8152_resume(struct usb_interface *intf) { … } static int rtl8152_reset_resume(struct usb_interface *intf) { … } static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) { … } static u32 rtl8152_get_msglevel(struct net_device *dev) { … } static void rtl8152_set_msglevel(struct net_device *dev, u32 value) { … } static void rtl8152_get_drvinfo(struct net_device *netdev, struct ethtool_drvinfo *info) { … } static int rtl8152_get_link_ksettings(struct net_device *netdev, struct ethtool_link_ksettings *cmd) { … } static int rtl8152_set_link_ksettings(struct net_device *dev, const struct ethtool_link_ksettings *cmd) { … } static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = …; static int rtl8152_get_sset_count(struct net_device *dev, int sset) { … } static void rtl8152_get_ethtool_stats(struct net_device *dev, struct ethtool_stats *stats, u64 *data) { … } static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) { … } static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee) { … } static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee) { … } static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee) { … } static int rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata) { … } static int rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata) { … } static int rtl8152_nway_reset(struct net_device *dev) { … } static int rtl8152_get_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { … } static int rtl8152_set_coalesce(struct net_device *netdev, struct ethtool_coalesce *coalesce, struct kernel_ethtool_coalesce *kernel_coal, struct netlink_ext_ack *extack) { … } static int rtl8152_get_tunable(struct net_device *netdev, const struct ethtool_tunable *tunable, void *d) { … } static int rtl8152_set_tunable(struct net_device *netdev, const struct ethtool_tunable *tunable, const void *d) { … } static void rtl8152_get_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring, struct kernel_ethtool_ringparam *kernel_ring, struct netlink_ext_ack *extack) { … } static int rtl8152_set_ringparam(struct net_device *netdev, struct ethtool_ringparam *ring, struct kernel_ethtool_ringparam *kernel_ring, struct netlink_ext_ack *extack) { … } static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { … } static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) { … } static const struct ethtool_ops ops = …; static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) { … } static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) { … } static const struct net_device_ops rtl8152_netdev_ops = …; static void rtl8152_unload(struct r8152 *tp) { … } static void rtl8153_unload(struct r8152 *tp) { … } static void rtl8153b_unload(struct r8152 *tp) { … } static int rtl_ops_init(struct r8152 *tp) { … } #define FIRMWARE_8153A_2 … #define FIRMWARE_8153A_3 … #define FIRMWARE_8153A_4 … #define FIRMWARE_8153B_2 … #define FIRMWARE_8153C_1 … #define FIRMWARE_8156A_2 … #define FIRMWARE_8156B_2 … MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); MODULE_FIRMWARE(…); static int rtl_fw_init(struct r8152 *tp) { … } static u8 __rtl_get_hw_ver(struct usb_device *udev) { … } u8 rtl8152_get_version(struct usb_interface *intf) { … } EXPORT_SYMBOL_GPL(…); static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev) { … } static int rtl8152_probe_once(struct usb_interface *intf, const struct usb_device_id *id, u8 version) { … } #define RTL8152_PROBE_TRIES … static int rtl8152_probe(struct usb_interface *intf, const struct usb_device_id *id) { … } static void rtl8152_disconnect(struct usb_interface *intf) { … } /* table of devices that work with this driver */ static const struct usb_device_id rtl8152_table[] = …; MODULE_DEVICE_TABLE(usb, rtl8152_table); static struct usb_driver rtl8152_driver = …; static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev) { … } static struct usb_device_driver rtl8152_cfgselector_driver = …; static int __init rtl8152_driver_init(void) { … } static void __exit rtl8152_driver_exit(void) { … } module_init(…) …; module_exit(rtl8152_driver_exit); MODULE_AUTHOR(…); MODULE_DESCRIPTION(…); MODULE_LICENSE(…) …; MODULE_VERSION(…);
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