/* SPDX-License-Identifier: GPL-2.0-only */ /* * CoreChip-sz SR9700 one chip USB 1.1 Ethernet Devices * * Author : Liu Junliang <[email protected]> */ #ifndef _SR9700_H #define _SR9700_H /* sr9700 spec. register table on Linux platform */ /* Network Control Reg */ #define SR_NCR … #define NCR_RST … #define NCR_LBK … #define NCR_FDX … #define NCR_WAKEEN … /* Network Status Reg */ #define SR_NSR … #define NSR_RXRDY … #define NSR_RXOV … #define NSR_TX1END … #define NSR_TX2END … #define NSR_TXFULL … #define NSR_WAKEST … #define NSR_LINKST … #define NSR_SPEED … /* Tx Control Reg */ #define SR_TCR … #define TCR_CRC_DIS … #define TCR_PAD_DIS … #define TCR_LC_CARE … #define TCR_CRS_CARE … #define TCR_EXCECM … #define TCR_LF_EN … /* Tx Status Reg for Packet Index 1 */ #define SR_TSR1 … #define TSR1_EC … #define TSR1_COL … #define TSR1_LC … #define TSR1_NC … #define TSR1_LOC … #define TSR1_TLF … /* Tx Status Reg for Packet Index 2 */ #define SR_TSR2 … #define TSR2_EC … #define TSR2_COL … #define TSR2_LC … #define TSR2_NC … #define TSR2_LOC … #define TSR2_TLF … /* Rx Control Reg*/ #define SR_RCR … #define RCR_RXEN … #define RCR_PRMSC … #define RCR_RUNT … #define RCR_ALL … #define RCR_DIS_CRC … #define RCR_DIS_LONG … /* Rx Status Reg */ #define SR_RSR … #define RSR_AE … #define RSR_MF … #define RSR_RF … /* Rx Overflow Counter Reg */ #define SR_ROCR … #define ROCR_ROC … #define ROCR_RXFU … /* Back Pressure Threshold Reg */ #define SR_BPTR … #define BPTR_JPT … #define BPTR_BPHW … /* Flow Control Threshold Reg */ #define SR_FCTR … #define FCTR_LWOT … #define FCTR_HWOT … /* rx/tx Flow Control Reg */ #define SR_FCR … #define FCR_FLCE … #define FCR_BKPA … #define FCR_TXPEN … #define FCR_TXPF … #define FCR_TXP0 … /* Eeprom & Phy Control Reg */ #define SR_EPCR … #define EPCR_ERRE … #define EPCR_ERPRW … #define EPCR_ERPRR … #define EPCR_EPOS … #define EPCR_WEP … /* Eeprom & Phy Address Reg */ #define SR_EPAR … #define EPAR_EROA … #define EPAR_PHY_ADR_MASK … #define EPAR_PHY_ADR … /* Eeprom & Phy Data Reg */ #define SR_EPDR … /* Wakeup Control Reg */ #define SR_WCR … #define WCR_MAGICST … #define WCR_LINKST … #define WCR_MAGICEN … #define WCR_LINKEN … /* Physical Address Reg */ #define SR_PAR … /* Multicast Address Reg */ #define SR_MAR … /* 0x1e unused */ /* Phy Reset Reg */ #define SR_PRR … #define PRR_PHY_RST … /* Tx sdram Write Pointer Address Low */ #define SR_TWPAL … /* Tx sdram Write Pointer Address High */ #define SR_TWPAH … /* Tx sdram Read Pointer Address Low */ #define SR_TRPAL … /* Tx sdram Read Pointer Address High */ #define SR_TRPAH … /* Rx sdram Write Pointer Address Low */ #define SR_RWPAL … /* Rx sdram Write Pointer Address High */ #define SR_RWPAH … /* Rx sdram Read Pointer Address Low */ #define SR_RRPAL … /* Rx sdram Read Pointer Address High */ #define SR_RRPAH … /* Vendor ID register */ #define SR_VID … /* Product ID register */ #define SR_PID … /* CHIP Revision register */ #define SR_CHIPR … /* 0x2D --> 0xEF unused */ /* USB Device Address */ #define SR_USBDA … #define USBDA_USBFA … /* RX packet Counter Reg */ #define SR_RXC … /* Tx packet Counter & USB Status Reg */ #define SR_TXC_USBS … #define TXC_USBS_TXC0 … #define TXC_USBS_TXC1 … #define TXC_USBS_TXC2 … #define TXC_USBS_EP1RDY … #define TXC_USBS_SUSFLAG … #define TXC_USBS_RXFAULT … /* USB Control register */ #define SR_USBC … #define USBC_EP3NAK … #define USBC_EP3ACK … /* Register access commands and flags */ #define SR_RD_REGS … #define SR_WR_REGS … #define SR_WR_REG … #define SR_REQ_RD_REG … #define SR_REQ_WR_REG … /* parameters */ #define SR_SHARE_TIMEOUT … #define SR_EEPROM_LEN … #define SR_MCAST_SIZE … #define SR_MCAST_ADDR_FLAG … #define SR_MCAST_MAX … #define SR_TX_OVERHEAD … #define SR_RX_OVERHEAD … #endif /* _SR9700_H */
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