/* SPDX-License-Identifier: GPL-2.0-only */ /* * FUJITSU Extended Socket Network Device driver * Copyright (c) 2015 FUJITSU LIMITED */ #ifndef FJES_REGS_H_ #define FJES_REGS_H_ #include <linux/bitops.h> #define XSCT_DEVICE_REGISTER_SIZE … /* register offset */ /* Information registers */ #define XSCT_OWNER_EPID … #define XSCT_MAX_EP … /* Device Control registers */ #define XSCT_DCTL … /* Command Control registers */ #define XSCT_CR … #define XSCT_CS … #define XSCT_SHSTSAL … #define XSCT_SHSTSAH … #define XSCT_REQBL … #define XSCT_REQBAL … #define XSCT_REQBAH … #define XSCT_RESPBL … #define XSCT_RESPBAL … #define XSCT_RESPBAH … /* Interrupt Control registers */ #define XSCT_IS … #define XSCT_IMS … #define XSCT_IMC … #define XSCT_IG … #define XSCT_ICTL … /* register structure */ /* Information registers */ REG_OWNER_EPID; REG_MAX_EP; /* Device Control registers */ REG_DCTL; /* Command Control registers */ REG_CR; REG_CS; /* Interrupt Control registers */ REG_ICTL; enum REG_ICTL_MASK { … }; enum REG_IS_MASK { … }; struct fjes_hw; u32 fjes_hw_rd32(struct fjes_hw *hw, u32 reg); #define wr32(reg, val) … #define rd32(reg) … #endif /* FJES_REGS_H_ */
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