// SPDX-License-Identifier: GPL-2.0-only /* * rtc-ds1307.c - RTC driver for some mostly-compatible I2C chips. * * Copyright (C) 2005 James Chapman (ds1337 core) * Copyright (C) 2006 David Brownell * Copyright (C) 2009 Matthias Fuchs (rx8025 support) * Copyright (C) 2012 Bertrand Achard (nvram access fixes) */ #include <linux/bcd.h> #include <linux/i2c.h> #include <linux/init.h> #include <linux/kstrtox.h> #include <linux/mod_devicetable.h> #include <linux/module.h> #include <linux/property.h> #include <linux/rtc/ds1307.h> #include <linux/rtc.h> #include <linux/slab.h> #include <linux/string.h> #include <linux/hwmon.h> #include <linux/hwmon-sysfs.h> #include <linux/clk-provider.h> #include <linux/regmap.h> #include <linux/watchdog.h> /* * We can't determine type by probing, but if we expect pre-Linux code * to have set the chip up as a clock (turning on the oscillator and * setting the date and time), Linux can ignore the non-clock features. * That's a natural job for a factory or repair bench. */ enum ds_type { … }; /* RTC registers don't differ much, except for the century flag */ #define DS1307_REG_SECS … #define DS1307_BIT_CH … #define DS1340_BIT_nEOSC … #define MCP794XX_BIT_ST … #define DS1307_REG_MIN … #define M41T0_BIT_OF … #define DS1307_REG_HOUR … #define DS1307_BIT_12HR … #define DS1307_BIT_PM … #define DS1340_BIT_CENTURY_EN … #define DS1340_BIT_CENTURY … #define DS1307_REG_WDAY … #define MCP794XX_BIT_OSCRUN … #define MCP794XX_BIT_VBATEN … #define DS1307_REG_MDAY … #define DS1307_REG_MONTH … #define DS1337_BIT_CENTURY … #define DS1307_REG_YEAR … /* * Other registers (control, status, alarms, trickle charge, NVRAM, etc) * start at 7, and they differ a LOT. Only control and status matter for * basic RTC date and time functionality; be careful using them. */ #define DS1307_REG_CONTROL … #define DS1307_BIT_OUT … #define DS1338_BIT_OSF … #define DS1307_BIT_SQWE … #define DS1307_BIT_RS1 … #define DS1307_BIT_RS0 … #define DS1337_REG_CONTROL … #define DS1337_BIT_nEOSC … #define DS1339_BIT_BBSQI … #define DS3231_BIT_BBSQW … #define DS1337_BIT_RS2 … #define DS1337_BIT_RS1 … #define DS1337_BIT_INTCN … #define DS1337_BIT_A2IE … #define DS1337_BIT_A1IE … #define DS1340_REG_CONTROL … #define DS1340_BIT_OUT … #define DS1340_BIT_FT … #define DS1340_BIT_CALIB_SIGN … #define DS1340_M_CALIBRATION … #define DS1340_REG_FLAG … #define DS1340_BIT_OSF … #define DS1337_REG_STATUS … #define DS1337_BIT_OSF … #define DS3231_BIT_EN32KHZ … #define DS1337_BIT_A2I … #define DS1337_BIT_A1I … #define DS1339_REG_ALARM1_SECS … #define DS13XX_TRICKLE_CHARGER_MAGIC … #define RX8025_REG_CTRL1 … #define RX8025_BIT_2412 … #define RX8025_REG_CTRL2 … #define RX8025_BIT_PON … #define RX8025_BIT_VDET … #define RX8025_BIT_XST … #define RX8130_REG_ALARM_MIN … #define RX8130_REG_ALARM_HOUR … #define RX8130_REG_ALARM_WEEK_OR_DAY … #define RX8130_REG_EXTENSION … #define RX8130_REG_EXTENSION_WADA … #define RX8130_REG_FLAG … #define RX8130_REG_FLAG_VLF … #define RX8130_REG_FLAG_AF … #define RX8130_REG_CONTROL0 … #define RX8130_REG_CONTROL0_AIE … #define RX8130_REG_CONTROL1 … #define RX8130_REG_CONTROL1_INIEN … #define RX8130_REG_CONTROL1_CHGEN … #define MCP794XX_REG_CONTROL … #define MCP794XX_BIT_ALM0_EN … #define MCP794XX_BIT_ALM1_EN … #define MCP794XX_REG_ALARM0_BASE … #define MCP794XX_REG_ALARM0_CTRL … #define MCP794XX_REG_ALARM1_BASE … #define MCP794XX_REG_ALARM1_CTRL … #define MCP794XX_BIT_ALMX_IF … #define MCP794XX_BIT_ALMX_C0 … #define MCP794XX_BIT_ALMX_C1 … #define MCP794XX_BIT_ALMX_C2 … #define MCP794XX_BIT_ALMX_POL … #define MCP794XX_MSK_ALMX_MATCH … #define M41TXX_REG_CONTROL … #define M41TXX_BIT_OUT … #define M41TXX_BIT_FT … #define M41TXX_BIT_CALIB_SIGN … #define M41TXX_M_CALIBRATION … #define DS1388_REG_WDOG_HUN_SECS … #define DS1388_REG_WDOG_SECS … #define DS1388_REG_FLAG … #define DS1388_BIT_WF … #define DS1388_BIT_OSF … #define DS1388_REG_CONTROL … #define DS1388_BIT_RST … #define DS1388_BIT_WDE … #define DS1388_BIT_nEOSC … /* negative offset step is -2.034ppm */ #define M41TXX_NEG_OFFSET_STEP_PPB … /* positive offset step is +4.068ppm */ #define M41TXX_POS_OFFSET_STEP_PPB … /* Min and max values supported with 'offset' interface by M41TXX */ #define M41TXX_MIN_OFFSET … #define M41TXX_MAX_OFFSET … struct ds1307 { … }; struct chip_desc { … }; static const struct chip_desc chips[last_ds_type]; static int ds1307_get_time(struct device *dev, struct rtc_time *t) { … } static int ds1307_set_time(struct device *dev, struct rtc_time *t) { … } static int ds1337_read_alarm(struct device *dev, struct rtc_wkalrm *t) { … } static int ds1337_set_alarm(struct device *dev, struct rtc_wkalrm *t) { … } static int ds1307_alarm_irq_enable(struct device *dev, unsigned int enabled) { … } static u8 do_trickle_setup_ds1339(struct ds1307 *ds1307, u32 ohms, bool diode) { … } static u8 do_trickle_setup_rx8130(struct ds1307 *ds1307, u32 ohms, bool diode) { … } static irqreturn_t rx8130_irq(int irq, void *dev_id) { … } static int rx8130_read_alarm(struct device *dev, struct rtc_wkalrm *t) { … } static int rx8130_set_alarm(struct device *dev, struct rtc_wkalrm *t) { … } static int rx8130_alarm_irq_enable(struct device *dev, unsigned int enabled) { … } static irqreturn_t mcp794xx_irq(int irq, void *dev_id) { … } static int mcp794xx_read_alarm(struct device *dev, struct rtc_wkalrm *t) { … } /* * We may have a random RTC weekday, therefore calculate alarm weekday based * on current weekday we read from the RTC timekeeping regs */ static int mcp794xx_alm_weekday(struct device *dev, struct rtc_time *tm_alarm) { … } static int mcp794xx_set_alarm(struct device *dev, struct rtc_wkalrm *t) { … } static int mcp794xx_alarm_irq_enable(struct device *dev, unsigned int enabled) { … } static int m41txx_rtc_read_offset(struct device *dev, long *offset) { … } static int m41txx_rtc_set_offset(struct device *dev, long offset) { … } #ifdef CONFIG_WATCHDOG_CORE static int ds1388_wdt_start(struct watchdog_device *wdt_dev) { … } static int ds1388_wdt_stop(struct watchdog_device *wdt_dev) { … } static int ds1388_wdt_ping(struct watchdog_device *wdt_dev) { … } static int ds1388_wdt_set_timeout(struct watchdog_device *wdt_dev, unsigned int val) { … } #endif static const struct rtc_class_ops rx8130_rtc_ops = …; static const struct rtc_class_ops mcp794xx_rtc_ops = …; static const struct rtc_class_ops m41txx_rtc_ops = …; static const struct chip_desc chips[last_ds_type] = …; static const struct i2c_device_id ds1307_id[] = …; MODULE_DEVICE_TABLE(i2c, ds1307_id); static const struct of_device_id ds1307_of_match[] = …; MODULE_DEVICE_TABLE(of, ds1307_of_match); /* * The ds1337 and ds1339 both have two alarms, but we only use the first * one (with a "seconds" field). For ds1337 we expect nINTA is our alarm * signal; ds1339 chips have only one alarm signal. */ static irqreturn_t ds1307_irq(int irq, void *dev_id) { … } /*----------------------------------------------------------------------*/ static const struct rtc_class_ops ds13xx_rtc_ops = …; static ssize_t frequency_test_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t count) { … } static ssize_t frequency_test_show(struct device *dev, struct device_attribute *attr, char *buf) { … } static DEVICE_ATTR_RW(frequency_test); static struct attribute *rtc_freq_test_attrs[] = …; static const struct attribute_group rtc_freq_test_attr_group = …; static int ds1307_add_frequency_test(struct ds1307 *ds1307) { … } /*----------------------------------------------------------------------*/ static int ds1307_nvram_read(void *priv, unsigned int offset, void *val, size_t bytes) { … } static int ds1307_nvram_write(void *priv, unsigned int offset, void *val, size_t bytes) { … } /*----------------------------------------------------------------------*/ static u8 ds1307_trickle_init(struct ds1307 *ds1307, const struct chip_desc *chip) { … } /*----------------------------------------------------------------------*/ #if IS_REACHABLE(CONFIG_HWMON) /* * Temperature sensor support for ds3231 devices. */ #define DS3231_REG_TEMPERATURE … /* * A user-initiated temperature conversion is not started by this function, * so the temperature is updated once every 64 seconds. */ static int ds3231_hwmon_read_temp(struct device *dev, s32 *mC) { … } static ssize_t ds3231_hwmon_show_temp(struct device *dev, struct device_attribute *attr, char *buf) { … } static SENSOR_DEVICE_ATTR(temp1_input, 0444, ds3231_hwmon_show_temp, NULL, 0); static struct attribute *ds3231_hwmon_attrs[] = …; ATTRIBUTE_GROUPS(…); static void ds1307_hwmon_register(struct ds1307 *ds1307) { … } #else static void ds1307_hwmon_register(struct ds1307 *ds1307) { } #endif /* CONFIG_RTC_DRV_DS1307_HWMON */ /*----------------------------------------------------------------------*/ /* * Square-wave output support for DS3231 * Datasheet: https://datasheets.maximintegrated.com/en/ds/DS3231.pdf */ #ifdef CONFIG_COMMON_CLK enum { … }; #define clk_sqw_to_ds1307(clk) … #define clk_32khz_to_ds1307(clk) … static int ds3231_clk_sqw_rates[] = …; static int ds1337_write_control(struct ds1307 *ds1307, u8 mask, u8 value) { … } static unsigned long ds3231_clk_sqw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long ds3231_clk_sqw_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { … } static int ds3231_clk_sqw_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static int ds3231_clk_sqw_prepare(struct clk_hw *hw) { … } static void ds3231_clk_sqw_unprepare(struct clk_hw *hw) { … } static int ds3231_clk_sqw_is_prepared(struct clk_hw *hw) { … } static const struct clk_ops ds3231_clk_sqw_ops = …; static unsigned long ds3231_clk_32khz_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static int ds3231_clk_32khz_control(struct ds1307 *ds1307, bool enable) { … } static int ds3231_clk_32khz_prepare(struct clk_hw *hw) { … } static void ds3231_clk_32khz_unprepare(struct clk_hw *hw) { … } static int ds3231_clk_32khz_is_prepared(struct clk_hw *hw) { … } static const struct clk_ops ds3231_clk_32khz_ops = …; static const char *ds3231_clks_names[] = …; static struct clk_init_data ds3231_clks_init[] = …; static int ds3231_clks_register(struct ds1307 *ds1307) { … } static void ds1307_clks_register(struct ds1307 *ds1307) { … } #else static void ds1307_clks_register(struct ds1307 *ds1307) { } #endif /* CONFIG_COMMON_CLK */ #ifdef CONFIG_WATCHDOG_CORE static const struct watchdog_info ds1388_wdt_info = …; static const struct watchdog_ops ds1388_wdt_ops = …; static void ds1307_wdt_register(struct ds1307 *ds1307) { … } #else static void ds1307_wdt_register(struct ds1307 *ds1307) { } #endif /* CONFIG_WATCHDOG_CORE */ static const struct regmap_config regmap_config = …; static int ds1307_probe(struct i2c_client *client) { … } static struct i2c_driver ds1307_driver = …; module_i2c_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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