// SPDX-License-Identifier: GPL-2.0-or-later /* * An RTC driver for Allwinner A31/A23 * * Copyright (c) 2014, Chen-Yu Tsai <[email protected]> * * based on rtc-sunxi.c * * An RTC driver for Allwinner A10/A20 * * Copyright (c) 2013, Carlo Caione <[email protected]> */ #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/clk/sunxi-ng.h> #include <linux/delay.h> #include <linux/err.h> #include <linux/fs.h> #include <linux/init.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/platform_device.h> #include <linux/rtc.h> #include <linux/slab.h> #include <linux/types.h> /* Control register */ #define SUN6I_LOSC_CTRL … #define SUN6I_LOSC_CTRL_KEY … #define SUN6I_LOSC_CTRL_AUTO_SWT_BYPASS … #define SUN6I_LOSC_CTRL_ALM_DHMS_ACC … #define SUN6I_LOSC_CTRL_RTC_HMS_ACC … #define SUN6I_LOSC_CTRL_RTC_YMD_ACC … #define SUN6I_LOSC_CTRL_EXT_LOSC_EN … #define SUN6I_LOSC_CTRL_EXT_OSC … #define SUN6I_LOSC_CTRL_ACC_MASK … #define SUN6I_LOSC_CLK_PRESCAL … /* RTC */ #define SUN6I_RTC_YMD … #define SUN6I_RTC_HMS … /* Alarm 0 (counter) */ #define SUN6I_ALRM_COUNTER … /* This holds the remaining alarm seconds on older SoCs (current value) */ #define SUN6I_ALRM_COUNTER_HMS … #define SUN6I_ALRM_EN … #define SUN6I_ALRM_EN_CNT_EN … #define SUN6I_ALRM_IRQ_EN … #define SUN6I_ALRM_IRQ_EN_CNT_IRQ_EN … #define SUN6I_ALRM_IRQ_STA … #define SUN6I_ALRM_IRQ_STA_CNT_IRQ_PEND … /* Alarm 1 (wall clock) */ #define SUN6I_ALRM1_EN … #define SUN6I_ALRM1_IRQ_EN … #define SUN6I_ALRM1_IRQ_STA … #define SUN6I_ALRM1_IRQ_STA_WEEK_IRQ_PEND … /* Alarm config */ #define SUN6I_ALARM_CONFIG … #define SUN6I_ALARM_CONFIG_WAKEUP … #define SUN6I_LOSC_OUT_GATING … #define SUN6I_LOSC_OUT_GATING_EN_OFFSET … /* General-purpose data */ #define SUN6I_GP_DATA … #define SUN6I_GP_DATA_SIZE … /* * Get date values */ #define SUN6I_DATE_GET_DAY_VALUE(x) … #define SUN6I_DATE_GET_MON_VALUE(x) … #define SUN6I_DATE_GET_YEAR_VALUE(x) … #define SUN6I_LEAP_GET_VALUE(x) … /* * Get time values */ #define SUN6I_TIME_GET_SEC_VALUE(x) … #define SUN6I_TIME_GET_MIN_VALUE(x) … #define SUN6I_TIME_GET_HOUR_VALUE(x) … /* * Set date values */ #define SUN6I_DATE_SET_DAY_VALUE(x) … #define SUN6I_DATE_SET_MON_VALUE(x) … #define SUN6I_DATE_SET_YEAR_VALUE(x) … #define SUN6I_LEAP_SET_VALUE(x) … /* * Set time values */ #define SUN6I_TIME_SET_SEC_VALUE(x) … #define SUN6I_TIME_SET_MIN_VALUE(x) … #define SUN6I_TIME_SET_HOUR_VALUE(x) … /* * The year parameter passed to the driver is usually an offset relative to * the year 1900. This macro is used to convert this offset to another one * relative to the minimum year allowed by the hardware. * * The year range is 1970 - 2033. This range is selected to match Allwinner's * driver, even though it is somewhat limited. */ #define SUN6I_YEAR_MIN … #define SUN6I_YEAR_OFF … #define SECS_PER_DAY … /* * There are other differences between models, including: * * - number of GPIO pins that can be configured to hold a certain level * - crypto-key related registers (H5, H6) * - boot process related (super standby, secondary processor entry address) * registers (R40, H6) * - SYS power domain controls (R40) * - DCXO controls (H6) * - RC oscillator calibration (H6) * * These functions are not covered by this driver. */ struct sun6i_rtc_clk_data { … }; #define RTC_LINEAR_DAY … struct sun6i_rtc_dev { … }; static struct sun6i_rtc_dev *sun6i_rtc; static unsigned long sun6i_rtc_osc_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static u8 sun6i_rtc_osc_get_parent(struct clk_hw *hw) { … } static int sun6i_rtc_osc_set_parent(struct clk_hw *hw, u8 index) { … } static const struct clk_ops sun6i_rtc_osc_ops = …; static void __init sun6i_rtc_clk_init(struct device_node *node, const struct sun6i_rtc_clk_data *data) { … } static const struct sun6i_rtc_clk_data sun6i_a31_rtc_data = …; static void __init sun6i_a31_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun6i_a31_rtc_clk, "allwinner,sun6i-a31-rtc", sun6i_a31_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_a23_rtc_data = …; static void __init sun8i_a23_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun8i_a23_rtc_clk, "allwinner,sun8i-a23-rtc", sun8i_a23_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_h3_rtc_data = …; static void __init sun8i_h3_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun8i_h3_rtc_clk, "allwinner,sun8i-h3-rtc", sun8i_h3_rtc_clk_init); /* As far as we are concerned, clocks for H5 are the same as H3 */ CLK_OF_DECLARE_DRIVER(sun50i_h5_rtc_clk, "allwinner,sun50i-h5-rtc", sun8i_h3_rtc_clk_init); static const struct sun6i_rtc_clk_data sun50i_h6_rtc_data = …; static void __init sun50i_h6_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun50i_h6_rtc_clk, "allwinner,sun50i-h6-rtc", sun50i_h6_rtc_clk_init); /* * The R40 user manual is self-conflicting on whether the prescaler is * fixed or configurable. The clock diagram shows it as fixed, but there * is also a configurable divider in the RTC block. */ static const struct sun6i_rtc_clk_data sun8i_r40_rtc_data = …; static void __init sun8i_r40_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun8i_r40_rtc_clk, "allwinner,sun8i-r40-rtc", sun8i_r40_rtc_clk_init); static const struct sun6i_rtc_clk_data sun8i_v3_rtc_data = …; static void __init sun8i_v3_rtc_clk_init(struct device_node *node) { … } CLK_OF_DECLARE_DRIVER(sun8i_v3_rtc_clk, "allwinner,sun8i-v3-rtc", sun8i_v3_rtc_clk_init); static irqreturn_t sun6i_rtc_alarmirq(int irq, void *id) { … } static void sun6i_rtc_setaie(int to, struct sun6i_rtc_dev *chip) { … } static int sun6i_rtc_gettime(struct device *dev, struct rtc_time *rtc_tm) { … } static int sun6i_rtc_getalarm(struct device *dev, struct rtc_wkalrm *wkalrm) { … } static int sun6i_rtc_setalarm(struct device *dev, struct rtc_wkalrm *wkalrm) { … } static int sun6i_rtc_wait(struct sun6i_rtc_dev *chip, int offset, unsigned int mask, unsigned int ms_timeout) { … } static int sun6i_rtc_settime(struct device *dev, struct rtc_time *rtc_tm) { … } static int sun6i_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) { … } static const struct rtc_class_ops sun6i_rtc_ops = …; static int sun6i_rtc_nvmem_read(void *priv, unsigned int offset, void *_val, size_t bytes) { … } static int sun6i_rtc_nvmem_write(void *priv, unsigned int offset, void *_val, size_t bytes) { … } static struct nvmem_config sun6i_rtc_nvmem_cfg = …; #ifdef CONFIG_PM_SLEEP /* Enable IRQ wake on suspend, to wake up from RTC. */ static int sun6i_rtc_suspend(struct device *dev) { … } /* Disable IRQ wake on resume. */ static int sun6i_rtc_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(sun6i_rtc_pm_ops, sun6i_rtc_suspend, sun6i_rtc_resume); static void sun6i_rtc_bus_clk_cleanup(void *data) { … } static int sun6i_rtc_probe(struct platform_device *pdev) { … } /* * As far as RTC functionality goes, all models are the same. The * datasheets claim that different models have different number of * registers available for non-volatile storage, but experiments show * that all SoCs have 16 registers available for this purpose. */ static const struct of_device_id sun6i_rtc_dt_ids[] = …; MODULE_DEVICE_TABLE(of, sun6i_rtc_dt_ids); static struct platform_driver sun6i_rtc_driver = …; builtin_platform_driver(…) …;
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