// SPDX-License-Identifier: GPL-2.0+ /* * An RTC driver for the NVIDIA Tegra 200 series internal RTC. * * Copyright (c) 2010-2019, NVIDIA Corporation. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/init.h> #include <linux/io.h> #include <linux/irq.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/mod_devicetable.h> #include <linux/platform_device.h> #include <linux/pm.h> #include <linux/rtc.h> #include <linux/slab.h> /* Set to 1 = busy every eight 32 kHz clocks during copy of sec+msec to AHB. */ #define TEGRA_RTC_REG_BUSY … #define TEGRA_RTC_REG_SECONDS … /* When msec is read, the seconds are buffered into shadow seconds. */ #define TEGRA_RTC_REG_SHADOW_SECONDS … #define TEGRA_RTC_REG_MILLI_SECONDS … #define TEGRA_RTC_REG_SECONDS_ALARM0 … #define TEGRA_RTC_REG_SECONDS_ALARM1 … #define TEGRA_RTC_REG_MILLI_SECONDS_ALARM0 … #define TEGRA_RTC_REG_INTR_MASK … /* write 1 bits to clear status bits */ #define TEGRA_RTC_REG_INTR_STATUS … /* bits in INTR_MASK */ #define TEGRA_RTC_INTR_MASK_MSEC_CDN_ALARM … #define TEGRA_RTC_INTR_MASK_SEC_CDN_ALARM … #define TEGRA_RTC_INTR_MASK_MSEC_ALARM … #define TEGRA_RTC_INTR_MASK_SEC_ALARM1 … #define TEGRA_RTC_INTR_MASK_SEC_ALARM0 … /* bits in INTR_STATUS */ #define TEGRA_RTC_INTR_STATUS_MSEC_CDN_ALARM … #define TEGRA_RTC_INTR_STATUS_SEC_CDN_ALARM … #define TEGRA_RTC_INTR_STATUS_MSEC_ALARM … #define TEGRA_RTC_INTR_STATUS_SEC_ALARM1 … #define TEGRA_RTC_INTR_STATUS_SEC_ALARM0 … struct tegra_rtc_info { … }; /* * RTC hardware is busy when it is updating its values over AHB once every * eight 32 kHz clocks (~250 us). Outside of these updates the CPU is free to * write. CPU is always free to read. */ static inline u32 tegra_rtc_check_busy(struct tegra_rtc_info *info) { … } /* * Wait for hardware to be ready for writing. This function tries to maximize * the amount of time before the next update. It does this by waiting for the * RTC to become busy with its periodic update, then returning once the RTC * first becomes not busy. * * This periodic update (where the seconds and milliseconds are copied to the * AHB side) occurs every eight 32 kHz clocks (~250 us). The behavior of this * function allows us to make some assumptions without introducing a race, * because 250 us is plenty of time to read/write a value. */ static int tegra_rtc_wait_while_busy(struct device *dev) { … } static int tegra_rtc_read_time(struct device *dev, struct rtc_time *tm) { … } static int tegra_rtc_set_time(struct device *dev, struct rtc_time *tm) { … } static int tegra_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alarm) { … } static int tegra_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled) { … } static int tegra_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alarm) { … } static int tegra_rtc_proc(struct device *dev, struct seq_file *seq) { … } static irqreturn_t tegra_rtc_irq_handler(int irq, void *data) { … } static const struct rtc_class_ops tegra_rtc_ops = …; static const struct of_device_id tegra_rtc_dt_match[] = …; MODULE_DEVICE_TABLE(of, tegra_rtc_dt_match); static int tegra_rtc_probe(struct platform_device *pdev) { … } static void tegra_rtc_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int tegra_rtc_suspend(struct device *dev) { … } static int tegra_rtc_resume(struct device *dev) { … } #endif static SIMPLE_DEV_PM_OPS(tegra_rtc_pm_ops, tegra_rtc_suspend, tegra_rtc_resume); static void tegra_rtc_shutdown(struct platform_device *pdev) { … } static struct platform_driver tegra_rtc_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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