// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2009-2013, 2016-2018, The Linux Foundation. All rights reserved. * Copyright (c) 2014, Sony Mobile Communications AB. * */ #include <linux/acpi.h> #include <linux/atomic.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/dmaengine.h> #include <linux/dmapool.h> #include <linux/dma-mapping.h> #include <linux/err.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/scatterlist.h> /* QUP Registers */ #define QUP_CONFIG … #define QUP_STATE … #define QUP_IO_MODE … #define QUP_SW_RESET … #define QUP_OPERATIONAL … #define QUP_ERROR_FLAGS … #define QUP_ERROR_FLAGS_EN … #define QUP_OPERATIONAL_MASK … #define QUP_HW_VERSION … #define QUP_MX_OUTPUT_CNT … #define QUP_OUT_FIFO_BASE … #define QUP_MX_WRITE_CNT … #define QUP_MX_INPUT_CNT … #define QUP_MX_READ_CNT … #define QUP_IN_FIFO_BASE … #define QUP_I2C_CLK_CTL … #define QUP_I2C_STATUS … #define QUP_I2C_MASTER_GEN … /* QUP States and reset values */ #define QUP_RESET_STATE … #define QUP_RUN_STATE … #define QUP_PAUSE_STATE … #define QUP_STATE_MASK … #define QUP_STATE_VALID … #define QUP_I2C_MAST_GEN … #define QUP_I2C_FLUSH … #define QUP_OPERATIONAL_RESET … #define QUP_I2C_STATUS_RESET … /* QUP OPERATIONAL FLAGS */ #define QUP_I2C_NACK_FLAG … #define QUP_OUT_NOT_EMPTY … #define QUP_IN_NOT_EMPTY … #define QUP_OUT_FULL … #define QUP_OUT_SVC_FLAG … #define QUP_IN_SVC_FLAG … #define QUP_MX_OUTPUT_DONE … #define QUP_MX_INPUT_DONE … #define OUT_BLOCK_WRITE_REQ … #define IN_BLOCK_READ_REQ … /* I2C mini core related values */ #define QUP_NO_INPUT … #define QUP_CLOCK_AUTO_GATE … #define I2C_MINI_CORE … #define I2C_N_VAL … #define I2C_N_VAL_V2 … /* Most significant word offset in FIFO port */ #define QUP_MSW_SHIFT … /* Packing/Unpacking words in FIFOs, and IO modes */ #define QUP_OUTPUT_BLK_MODE … #define QUP_OUTPUT_BAM_MODE … #define QUP_INPUT_BLK_MODE … #define QUP_INPUT_BAM_MODE … #define QUP_BAM_MODE … #define QUP_UNPACK_EN … #define QUP_PACK_EN … #define QUP_REPACK_EN … #define QUP_V2_TAGS_EN … #define QUP_OUTPUT_BLOCK_SIZE(x) … #define QUP_OUTPUT_FIFO_SIZE(x) … #define QUP_INPUT_BLOCK_SIZE(x) … #define QUP_INPUT_FIFO_SIZE(x) … /* QUP tags */ #define QUP_TAG_START … #define QUP_TAG_DATA … #define QUP_TAG_STOP … #define QUP_TAG_REC … #define QUP_BAM_INPUT_EOT … #define QUP_BAM_FLUSH_STOP … /* QUP v2 tags */ #define QUP_TAG_V2_START … #define QUP_TAG_V2_DATAWR … #define QUP_TAG_V2_DATAWR_STOP … #define QUP_TAG_V2_DATARD … #define QUP_TAG_V2_DATARD_NACK … #define QUP_TAG_V2_DATARD_STOP … /* Status, Error flags */ #define I2C_STATUS_WR_BUFFER_FULL … #define I2C_STATUS_BUS_ACTIVE … #define I2C_STATUS_ERROR_MASK … #define QUP_STATUS_ERROR_FLAGS … #define QUP_READ_LIMIT … #define SET_BIT … #define RESET_BIT … #define ONE_BYTE … #define QUP_I2C_MX_CONFIG_DURING_RUN … /* Maximum transfer length for single DMA descriptor */ #define MX_TX_RX_LEN … #define MX_BLOCKS … /* Maximum transfer length for all DMA descriptors */ #define MX_DMA_TX_RX_LEN … #define MX_DMA_BLOCKS … /* * Minimum transfer timeout for i2c transfers in seconds. It will be added on * the top of maximum transfer time calculated from i2c bus speed to compensate * the overheads. */ #define TOUT_MIN … /* Default values. Use these if FW query fails */ #define DEFAULT_CLK_FREQ … #define DEFAULT_SRC_CLK … /* * Max tags length (start, stop and maximum 2 bytes address) for each QUP * data transfer */ #define QUP_MAX_TAGS_LEN … /* Max data length for each DATARD tags */ #define RECV_MAX_DATA_LEN … /* TAG length for DATA READ in RX FIFO */ #define READ_RX_TAGS_LEN … static unsigned int scl_freq; module_param_named(scl_freq, scl_freq, uint, 0444); MODULE_PARM_DESC(…) …; /* * count: no of blocks * pos: current block number * tx_tag_len: tx tag length for current block * rx_tag_len: rx tag length for current block * data_len: remaining data length for current message * cur_blk_len: data length for current block * total_tx_len: total tx length including tag bytes for current QUP transfer * total_rx_len: total rx length including tag bytes for current QUP transfer * tx_fifo_data_pos: current byte number in TX FIFO word * tx_fifo_free: number of free bytes in current QUP block write. * rx_fifo_data_pos: current byte number in RX FIFO word * fifo_available: number of available bytes in RX FIFO for current * QUP block read * tx_fifo_data: QUP TX FIFO write works on word basis (4 bytes). New byte write * to TX FIFO will be appended in this data and will be written to * TX FIFO when all the 4 bytes are available. * rx_fifo_data: QUP RX FIFO read works on word basis (4 bytes). This will * contains the 4 bytes of RX data. * cur_data: pointer to tell cur data position for current message * cur_tx_tags: pointer to tell cur position in tags * tx_tags_sent: all tx tag bytes have been written in FIFO word * send_last_word: for tx FIFO, last word send is pending in current block * rx_bytes_read: if all the bytes have been read from rx FIFO. * rx_tags_fetched: all the rx tag bytes have been fetched from rx fifo word * is_tx_blk_mode: whether tx uses block or FIFO mode in case of non BAM xfer. * is_rx_blk_mode: whether rx uses block or FIFO mode in case of non BAM xfer. * tags: contains tx tag bytes for current QUP transfer */ struct qup_i2c_block { … }; struct qup_i2c_tag { … }; struct qup_i2c_bam { … }; struct qup_i2c_dev { … }; static irqreturn_t qup_i2c_interrupt(int irq, void *dev) { … } static int qup_i2c_poll_state_mask(struct qup_i2c_dev *qup, u32 req_state, u32 req_mask) { … } static int qup_i2c_poll_state(struct qup_i2c_dev *qup, u32 req_state) { … } static void qup_i2c_flush(struct qup_i2c_dev *qup) { … } static int qup_i2c_poll_state_valid(struct qup_i2c_dev *qup) { … } static int qup_i2c_poll_state_i2c_master(struct qup_i2c_dev *qup) { … } static int qup_i2c_change_state(struct qup_i2c_dev *qup, u32 state) { … } /* Check if I2C bus returns to IDLE state */ static int qup_i2c_bus_active(struct qup_i2c_dev *qup, int len) { … } static void qup_i2c_write_tx_fifo_v1(struct qup_i2c_dev *qup) { … } static void qup_i2c_set_blk_data(struct qup_i2c_dev *qup, struct i2c_msg *msg) { … } static int qup_i2c_get_data_len(struct qup_i2c_dev *qup) { … } static bool qup_i2c_check_msg_len(struct i2c_msg *msg) { … } static int qup_i2c_set_tags_smb(u16 addr, u8 *tags, struct qup_i2c_dev *qup, struct i2c_msg *msg) { … } static int qup_i2c_set_tags(u8 *tags, struct qup_i2c_dev *qup, struct i2c_msg *msg) { … } static void qup_i2c_bam_cb(void *data) { … } static int qup_sg_set_buf(struct scatterlist *sg, void *buf, unsigned int buflen, struct qup_i2c_dev *qup, int dir) { … } static void qup_i2c_rel_dma(struct qup_i2c_dev *qup) { … } static int qup_i2c_req_dma(struct qup_i2c_dev *qup) { … } static int qup_i2c_bam_make_desc(struct qup_i2c_dev *qup, struct i2c_msg *msg) { … } static int qup_i2c_bam_schedule_desc(struct qup_i2c_dev *qup) { … } static void qup_i2c_bam_clear_tag_buffers(struct qup_i2c_dev *qup) { … } static int qup_i2c_bam_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num) { … } static int qup_i2c_wait_for_complete(struct qup_i2c_dev *qup, struct i2c_msg *msg) { … } static void qup_i2c_read_rx_fifo_v1(struct qup_i2c_dev *qup) { … } static void qup_i2c_write_rx_tags_v1(struct qup_i2c_dev *qup) { … } static void qup_i2c_conf_v1(struct qup_i2c_dev *qup) { … } static void qup_i2c_clear_blk_v1(struct qup_i2c_block *blk) { … } static int qup_i2c_conf_xfer_v1(struct qup_i2c_dev *qup, bool is_rx) { … } static int qup_i2c_write_one(struct qup_i2c_dev *qup) { … } static int qup_i2c_read_one(struct qup_i2c_dev *qup) { … } static int qup_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { … } /* * Configure registers related with reconfiguration during run and call it * before each i2c sub transfer. */ static void qup_i2c_conf_count_v2(struct qup_i2c_dev *qup) { … } /* * Configure registers related with transfer mode (FIFO/Block) * before starting of i2c transfer. It will be called only once in * QUP RESET state. */ static void qup_i2c_conf_mode_v2(struct qup_i2c_dev *qup) { … } /* Clear required variables before starting of any QUP v2 sub transfer. */ static void qup_i2c_clear_blk_v2(struct qup_i2c_block *blk) { … } /* Receive data from RX FIFO for read message in QUP v2 i2c transfer. */ static void qup_i2c_recv_data(struct qup_i2c_dev *qup) { … } /* Receive tags for read message in QUP v2 i2c transfer. */ static void qup_i2c_recv_tags(struct qup_i2c_dev *qup) { … } /* * Read the data and tags from RX FIFO. Since in read case, the tags will be * preceded by received data bytes so * 1. Check if rx_tags_fetched is false i.e. the start of QUP block so receive * all tag bytes and discard that. * 2. Read the data from RX FIFO. When all the data bytes have been read then * set rx_bytes_read to true. */ static void qup_i2c_read_rx_fifo_v2(struct qup_i2c_dev *qup) { … } /* * Write bytes in TX FIFO for write message in QUP v2 i2c transfer. QUP TX FIFO * write works on word basis (4 bytes). Append new data byte write for TX FIFO * in tx_fifo_data and write to TX FIFO when all the 4 bytes are present. */ static void qup_i2c_write_blk_data(struct qup_i2c_dev *qup, u8 **data, unsigned int *len) { … } /* Transfer tags for read message in QUP v2 i2c transfer. */ static void qup_i2c_write_rx_tags_v2(struct qup_i2c_dev *qup) { … } /* * Write the data and tags in TX FIFO. Since in write case, both tags and data * need to be written and QUP write tags can have maximum 256 data length, so * * 1. Check if tx_tags_sent is false i.e. the start of QUP block so write the * tags to TX FIFO and set tx_tags_sent to true. * 2. Check if send_last_word is true. It will be set when last few data bytes * (less than 4 bytes) are remaining to be written in FIFO because of no FIFO * space. All this data bytes are available in tx_fifo_data so write this * in FIFO. * 3. Write the data to TX FIFO and check for cur_blk_len. If it is non zero * then more data is pending otherwise following 3 cases can be possible * a. if tx_fifo_data_pos is zero i.e. all the data bytes in this block * have been written in TX FIFO so nothing else is required. * b. tx_fifo_free is non zero i.e tx FIFO is free so copy the remaining data * from tx_fifo_data to tx FIFO. Since, qup_i2c_write_blk_data do write * in 4 bytes and FIFO space is in multiple of 4 bytes so tx_fifo_free * will be always greater than or equal to 4 bytes. * c. tx_fifo_free is zero. In this case, last few bytes (less than 4 * bytes) are copied to tx_fifo_data but couldn't be sent because of * FIFO full so make send_last_word true. */ static void qup_i2c_write_tx_fifo_v2(struct qup_i2c_dev *qup) { … } /* * Main transfer function which read or write i2c data. * The QUP v2 supports reconfiguration during run in which multiple i2c sub * transfers can be scheduled. */ static int qup_i2c_conf_xfer_v2(struct qup_i2c_dev *qup, bool is_rx, bool is_first, bool change_pause_state) { … } /* * Transfer one read/write message in i2c transfer. It splits the message into * multiple of blk_xfer_limit data length blocks and schedule each * QUP block individually. */ static int qup_i2c_xfer_v2_msg(struct qup_i2c_dev *qup, int msg_id, bool is_rx) { … } /* * QUP v2 supports 3 modes * Programmed IO using FIFO mode : Less than FIFO size * Programmed IO using Block mode : Greater than FIFO size * DMA using BAM : Appropriate for any transaction size but the address should * be DMA applicable * * This function determines the mode which will be used for this transfer. An * i2c transfer contains multiple message. Following are the rules to determine * the mode used. * 1. Determine complete length, maximum tx and rx length for complete transfer. * 2. If complete transfer length is greater than fifo size then use the DMA * mode. * 3. In FIFO or block mode, tx and rx can operate in different mode so check * for maximum tx and rx length to determine mode. */ static int qup_i2c_determine_mode_v2(struct qup_i2c_dev *qup, struct i2c_msg msgs[], int num) { … } static int qup_i2c_xfer_v2(struct i2c_adapter *adap, struct i2c_msg msgs[], int num) { … } static u32 qup_i2c_func(struct i2c_adapter *adap) { … } static const struct i2c_algorithm qup_i2c_algo = …; static const struct i2c_algorithm qup_i2c_algo_v2 = …; /* * The QUP block will issue a NACK and STOP on the bus when reaching * the end of the read, the length of the read is specified as one byte * which limits the possible read to 256 (QUP_READ_LIMIT) bytes. */ static const struct i2c_adapter_quirks qup_i2c_quirks = …; static const struct i2c_adapter_quirks qup_i2c_quirks_v2 = …; static void qup_i2c_enable_clocks(struct qup_i2c_dev *qup) { … } static void qup_i2c_disable_clocks(struct qup_i2c_dev *qup) { … } static const struct acpi_device_id qup_i2c_acpi_match[] = …; MODULE_DEVICE_TABLE(acpi, qup_i2c_acpi_match); static int qup_i2c_probe(struct platform_device *pdev) { … } static void qup_i2c_remove(struct platform_device *pdev) { … } static int qup_i2c_pm_suspend_runtime(struct device *device) { … } static int qup_i2c_pm_resume_runtime(struct device *device) { … } static int qup_i2c_suspend(struct device *device) { … } static int qup_i2c_resume(struct device *device) { … } static const struct dev_pm_ops qup_i2c_qup_pm_ops = …; static const struct of_device_id qup_i2c_dt_match[] = …; MODULE_DEVICE_TABLE(of, qup_i2c_dt_match); static struct platform_driver qup_i2c_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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