// SPDX-License-Identifier: GPL-2.0 /* * Microchip PCI1XXXX I2C adapter driver for PCIe Switch * which has I2C controller in one of its downstream functions * * Copyright (C) 2021 - 2022 Microchip Technology Inc. * * Authors: Tharun Kumar P <[email protected]> * Kumaravel Thiagarajan <[email protected]> */ #include <linux/bits.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/i2c-smbus.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/pci.h> #include <linux/types.h> #define SMBUS_MAST_CORE_ADDR_BASE … #define SMBUS_MAST_SYS_REG_ADDR_BASE … /* SMB register space. */ #define SMB_CORE_CTRL_REG_OFF … #define SMB_CORE_CTRL_ESO … #define SMB_CORE_CTRL_FW_ACK … #define SMB_CORE_CTRL_ACK … #define SMB_CORE_CMD_REG_OFF3 … #define SMB_CORE_CMD_REG_OFF2 … #define SMB_CORE_CMD_REG_OFF1 … #define SMB_CORE_CMD_READM … #define SMB_CORE_CMD_STOP … #define SMB_CORE_CMD_START … #define SMB_CORE_CMD_REG_OFF0 … #define SMB_CORE_CMD_M_PROCEED … #define SMB_CORE_CMD_M_RUN … #define SMB_CORE_SR_HOLD_TIME_REG_OFF … /* * SR_HOLD_TIME_XK_TICKS field will indicate the number of ticks of the * baud clock required to program 'Hold Time' at X KHz. */ #define SR_HOLD_TIME_100K_TICKS … #define SR_HOLD_TIME_400K_TICKS … #define SR_HOLD_TIME_1000K_TICKS … #define SMB_CORE_COMPLETION_REG_OFF3 … #define COMPLETION_MDONE … #define COMPLETION_IDLE … #define COMPLETION_MNAKX … #define SMB_CORE_IDLE_SCALING_REG_OFF … /* * FAIR_BUS_IDLE_MIN_XK_TICKS field will indicate the number of ticks of * the baud clock required to program 'fair idle delay' at X KHz. Fair idle * delay establishes the MCTP T(IDLE_DELAY) period. */ #define FAIR_BUS_IDLE_MIN_100K_TICKS … #define FAIR_BUS_IDLE_MIN_400K_TICKS … #define FAIR_BUS_IDLE_MIN_1000K_TICKS … /* * FAIR_IDLE_DELAY_XK_TICKS field will indicate the number of ticks of the * baud clock required to satisfy the fairness protocol at X KHz. */ #define FAIR_IDLE_DELAY_100K_TICKS … #define FAIR_IDLE_DELAY_400K_TICKS … #define FAIR_IDLE_DELAY_1000K_TICKS … #define SMB_IDLE_SCALING_100K … #define SMB_IDLE_SCALING_400K … #define SMB_IDLE_SCALING_1000K … #define SMB_CORE_CONFIG_REG3 … #define SMB_CONFIG3_ENMI … #define SMB_CONFIG3_ENIDI … #define SMB_CORE_CONFIG_REG2 … #define SMB_CORE_CONFIG_REG1 … #define SMB_CONFIG1_ASR … #define SMB_CONFIG1_ENAB … #define SMB_CONFIG1_RESET … #define SMB_CONFIG1_FEN … #define SMB_CORE_BUS_CLK_REG_OFF … /* * BUS_CLK_XK_LOW_PERIOD_TICKS field defines the number of I2C Baud Clock * periods that make up the low phase of the I2C/SMBus bus clock at X KHz. */ #define BUS_CLK_100K_LOW_PERIOD_TICKS … #define BUS_CLK_400K_LOW_PERIOD_TICKS … #define BUS_CLK_1000K_LOW_PERIOD_TICKS … /* * BUS_CLK_XK_HIGH_PERIOD_TICKS field defines the number of I2C Baud Clock * periods that make up the high phase of the I2C/SMBus bus clock at X KHz. */ #define BUS_CLK_100K_HIGH_PERIOD_TICKS … #define BUS_CLK_400K_HIGH_PERIOD_TICKS … #define BUS_CLK_1000K_HIGH_PERIOD_TICKS … #define BUS_CLK_100K … #define BUS_CLK_400K … #define BUS_CLK_1000K … #define SMB_CORE_CLK_SYNC_REG_OFF … /* * CLK_SYNC_XK defines the number of clock cycles to sync up to the external * clock before comparing the internal and external clocks for clock stretching * at X KHz. */ #define CLK_SYNC_100K … #define CLK_SYNC_400K … #define CLK_SYNC_1000K … #define SMB_CORE_DATA_TIMING_REG_OFF … /* * * FIRST_START_HOLD_XK_TICKS will indicate the number of ticks of the baud * clock required to program 'FIRST_START_HOLD' timer at X KHz. This timer * determines the SCLK hold time following SDAT driven low during the first * START bit in a transfer. */ #define FIRST_START_HOLD_100K_TICKS … #define FIRST_START_HOLD_400K_TICKS … #define FIRST_START_HOLD_1000K_TICKS … /* * STOP_SETUP_XK_TICKS will indicate the number of ticks of the baud clock * required to program 'STOP_SETUP' timer at X KHz. This timer determines the * SDAT setup time from the rising edge of SCLK for a STOP condition. */ #define STOP_SETUP_100K_TICKS … #define STOP_SETUP_400K_TICKS … #define STOP_SETUP_1000K_TICKS … /* * RESTART_SETUP_XK_TICKS will indicate the number of ticks of the baud clock * required to program 'RESTART_SETUP' timer at X KHz. This timer determines the * SDAT setup time from the rising edge of SCLK for a repeated START condition. */ #define RESTART_SETUP_100K_TICKS … #define RESTART_SETUP_400K_TICKS … #define RESTART_SETUP_1000K_TICKS … /* * DATA_HOLD_XK_TICKS will indicate the number of ticks of the baud clock * required to program 'DATA_HOLD' timer at X KHz. This timer determines the * SDAT hold time following SCLK driven low. */ #define DATA_HOLD_100K_TICKS … #define DATA_HOLD_400K_TICKS … #define DATA_HOLD_1000K_TICKS … #define DATA_TIMING_100K … #define DATA_TIMING_400K … #define DATA_TIMING_1000K … #define SMB_CORE_TO_SCALING_REG_OFF … /* * BUS_IDLE_MIN_XK_TICKS defines Bus Idle Minimum Time. * Bus Idle Minimum time = BUS_IDLE_MIN[7:0] x Baud_Clock_Period x * (BUS_IDLE_MIN_XK_TICKS[7] ? 4,1) */ #define BUS_IDLE_MIN_100K_TICKS … #define BUS_IDLE_MIN_400K_TICKS … #define BUS_IDLE_MIN_1000K_TICKS … /* * CTRL_CUM_TIME_OUT_XK_TICKS defines SMBus Controller Cumulative Time-Out. * SMBus Controller Cumulative Time-Out duration = * CTRL_CUM_TIME_OUT_XK_TICKS[7:0] x Baud_Clock_Period x 2048 */ #define CTRL_CUM_TIME_OUT_100K_TICKS … #define CTRL_CUM_TIME_OUT_400K_TICKS … #define CTRL_CUM_TIME_OUT_1000K_TICKS … /* * TARGET_CUM_TIME_OUT_XK_TICKS defines SMBus Target Cumulative Time-Out duration. * SMBus Target Cumulative Time-Out duration = TARGET_CUM_TIME_OUT_XK_TICKS[7:0] x * Baud_Clock_Period x 4096 */ #define TARGET_CUM_TIME_OUT_100K_TICKS … #define TARGET_CUM_TIME_OUT_400K_TICKS … #define TARGET_CUM_TIME_OUT_1000K_TICKS … /* * CLOCK_HIGH_TIME_OUT_XK defines Clock High time out period. * Clock High time out period = CLOCK_HIGH_TIME_OUT_XK[7:0] x Baud_Clock_Period x 8 */ #define CLOCK_HIGH_TIME_OUT_100K_TICKS … #define CLOCK_HIGH_TIME_OUT_400K_TICKS … #define CLOCK_HIGH_TIME_OUT_1000K_TICKS … #define TO_SCALING_100K … #define TO_SCALING_400K … #define TO_SCALING_1000K … #define I2C_SCL_PAD_CTRL_REG_OFF … #define I2C_SDA_PAD_CTRL_REG_OFF … #define I2C_FOD_EN … #define I2C_PULL_UP_EN … #define I2C_PULL_DOWN_EN … #define I2C_INPUT_EN … #define I2C_OUTPUT_EN … #define SMBUS_CONTROL_REG_OFF … #define CTL_RESET_COUNTERS … #define CTL_TRANSFER_DIR … #define CTL_HOST_FIFO_ENTRY … #define CTL_RUN … #define I2C_DIRN_WRITE … #define I2C_DIRN_READ … #define SMBUS_STATUS_REG_OFF … #define STA_DMA_TERM … #define STA_DMA_REQ … #define STA_THRESHOLD … #define STA_BUF_FULL … #define STA_BUF_EMPTY … #define SMBUS_INTR_STAT_REG_OFF … #define INTR_STAT_DMA_TERM … #define INTR_STAT_THRESHOLD … #define INTR_STAT_BUF_FULL … #define INTR_STAT_BUF_EMPTY … #define SMBUS_INTR_MSK_REG_OFF … #define INTR_MSK_DMA_TERM … #define INTR_MSK_THRESHOLD … #define INTR_MSK_BUF_FULL … #define INTR_MSK_BUF_EMPTY … #define ALL_NW_LAYER_INTERRUPTS … #define SMBUS_MCU_COUNTER_REG_OFF … #define SMBALERT_MST_PAD_CTRL_REG_OFF … #define SMBALERT_MST_PU … #define SMBUS_GEN_INT_STAT_REG_OFF … #define SMBUS_GEN_INT_MASK_REG_OFF … #define SMBALERT_INTR_MASK … #define I2C_BUF_MSTR_INTR_MASK … #define I2C_INTR_MASK … #define SMBALERT_WAKE_INTR_MASK … #define I2C_BUF_MSTR_WAKE_INTR_MASK … #define I2C_WAKE_INTR_MASK … #define ALL_HIGH_LAYER_INTR … #define SMBUS_RESET_REG … #define PERI_SMBUS_D3_RESET_DIS … #define SMBUS_MST_BUF … #define SMBUS_BUF_MAX_SIZE … #define I2C_FLAGS_DIRECT_MODE … #define I2C_FLAGS_POLLING_MODE … #define I2C_FLAGS_STOP … #define I2C_FLAGS_SMB_BLK_READ … #define PCI1XXXX_I2C_TIMEOUT_MS … /* General Purpose Register. */ #define SMB_GPR_REG … /* Lock Register. */ #define SMB_GPR_LOCK_REG … #define SMBUS_PERI_LOCK … struct pci1xxxx_i2c { … }; static int set_sys_lock(struct pci1xxxx_i2c *i2c) { … } static int release_sys_lock(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_ack_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk) { … } static void pci1xxxx_i2c_configure_smbalert_pin(struct pci1xxxx_i2c *i2c, bool enable) { … } static void pci1xxxx_i2c_send_start_stop(struct pci1xxxx_i2c *i2c, bool start) { … } /* * When accessing the core control reg, we should not do a read modified write * as they are write '1' to clear bits. Instead we need to write with the * specific bits that needs to be set. */ static void pci1xxxx_i2c_set_clear_FW_ACK(struct pci1xxxx_i2c *i2c, bool set) { … } static void pci1xxxx_i2c_buffer_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr, u8 transferlen, unsigned char *buf) { … } /* * When accessing the core control reg, we should not do a read modified write * as there are write '1' to clear bits. Instead we need to write with the * specific bits that needs to be set. */ static void pci1xxxx_i2c_enable_ESO(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_reset_counters(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_set_transfer_dir(struct pci1xxxx_i2c *i2c, u8 direction) { … } static void pci1xxxx_i2c_set_mcu_count(struct pci1xxxx_i2c *i2c, u8 count) { … } static void pci1xxxx_i2c_set_read_count(struct pci1xxxx_i2c *i2c, u8 readcount) { … } static void pci1xxxx_i2c_set_write_count(struct pci1xxxx_i2c *i2c, u8 writecount) { … } static void pci1xxxx_i2c_set_DMA_run(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_set_mrun_proceed(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_start_DMA(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_config_asr(struct pci1xxxx_i2c *i2c, bool enable) { … } static irqreturn_t pci1xxxx_i2c_isr(int irq, void *dev) { … } static void pci1xxxx_i2c_set_count(struct pci1xxxx_i2c *i2c, u8 mcucount, u8 writecount, u8 readcount) { … } static void pci1xxxx_i2c_set_readm(struct pci1xxxx_i2c *i2c, bool enable) { … } static void pci1xxxx_ack_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 ack_intr_msk) { … } static void pci1xxxx_config_nw_layer_intr(struct pci1xxxx_i2c *i2c, u8 intr_msk, bool enable) { … } static void pci1xxxx_i2c_config_padctrl(struct pci1xxxx_i2c *i2c, bool enable) { … } static void pci1xxxx_i2c_set_mode(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_config_high_level_intr(struct pci1xxxx_i2c *i2c, u16 intr_msk, bool enable) { … } static void pci1xxxx_i2c_configure_core_reg(struct pci1xxxx_i2c *i2c, bool enable) { … } static void pci1xxxx_i2c_set_freq(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_init(struct pci1xxxx_i2c *i2c) { … } static void pci1xxxx_i2c_clear_flags(struct pci1xxxx_i2c *i2c) { … } static int pci1xxxx_i2c_read(struct pci1xxxx_i2c *i2c, u8 slaveaddr, unsigned char *buf, u16 total_len) { … } static int pci1xxxx_i2c_write(struct pci1xxxx_i2c *i2c, u8 slaveaddr, unsigned char *buf, u16 total_len) { … } static int pci1xxxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) { … } /* * List of supported functions by the driver. */ static u32 pci1xxxx_i2c_get_funcs(struct i2c_adapter *adap) { … } static const struct i2c_algorithm pci1xxxx_i2c_algo = …; static const struct i2c_adapter_quirks pci1xxxx_i2c_quirks = …; static const struct i2c_adapter pci1xxxx_i2c_ops = …; static int pci1xxxx_i2c_suspend(struct device *dev) { … } static int pci1xxxx_i2c_resume(struct device *dev) { … } static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_i2c_pm_ops, pci1xxxx_i2c_suspend, pci1xxxx_i2c_resume); static void pci1xxxx_i2c_shutdown(void *data) { … } static int pci1xxxx_i2c_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent) { … } static const struct pci_device_id pci1xxxx_i2c_pci_id_table[] = …; MODULE_DEVICE_TABLE(pci, pci1xxxx_i2c_pci_id_table); static struct pci_driver pci1xxxx_i2c_pci_driver = …; module_pci_driver(…) …; MODULE_LICENSE(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …;
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