/* SPDX-License-Identifier: BSD-3-Clause */ /* * Copyright (c) 2020, MIPI Alliance, Inc. * * Author: Nicolas Pitre <[email protected]> * * Common HCI stuff */ #ifndef HCI_H #define HCI_H #include <linux/io.h> /* Handy logging macro to save on line length */ #define DBG(x, ...) … /* 32-bit word aware bit and mask macros */ #define W0_MASK(h, l) … #define W1_MASK(h, l) … #define W2_MASK(h, l) … #define W3_MASK(h, l) … /* Same for single bit macros (trailing _ to align with W*_MASK width) */ #define W0_BIT_(x) … #define W1_BIT_(x) … #define W2_BIT_(x) … #define W3_BIT_(x) … #define reg_read(r) … #define reg_write(r, v) … #define reg_set(r, v) … #define reg_clear(r, v) … struct hci_cmd_ops; /* Our main structure */ struct i3c_hci { … }; /* * Structure to represent a master initiated transfer. * The rnw, data and data_len fields must be initialized before calling any * hci->cmd->*() method. The cmd method will initialize cmd_desc[] and * possibly modify (clear) the data field. Then xfer->cmd_desc[0] can * be augmented with CMD_0_ROC and/or CMD_0_TOC. * The completion field needs to be initialized before queueing with * hci->io->queue_xfer(), and requires CMD_0_ROC to be set. */ struct hci_xfer { … }; static inline struct hci_xfer *hci_alloc_xfer(unsigned int n) { … } static inline void hci_free_xfer(struct hci_xfer *xfer, unsigned int n) { … } /* This abstracts PIO vs DMA operations */ struct hci_io_ops { … }; extern const struct hci_io_ops mipi_i3c_hci_pio; extern const struct hci_io_ops mipi_i3c_hci_dma; /* Our per device master private data */ struct i3c_hci_dev_data { … }; /* list of quirks */ #define HCI_QUIRK_RAW_CCC … #define HCI_QUIRK_PIO_MODE … #define HCI_QUIRK_OD_PP_TIMING … #define HCI_QUIRK_RESP_BUF_THLD … /* global functions */ void mipi_i3c_hci_resume(struct i3c_hci *hci); void mipi_i3c_hci_pio_reset(struct i3c_hci *hci); void mipi_i3c_hci_dct_index_reset(struct i3c_hci *hci); void amd_set_od_pp_timing(struct i3c_hci *hci); void amd_set_resp_buf_thld(struct i3c_hci *hci); #endif
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