// SPDX-License-Identifier: GPL-2.0 /* * Copyright (c) 2018 Synopsys, Inc. and/or its affiliates. * * Author: Vitor Soares <[email protected]> */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/completion.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/i3c/master.h> #include <linux/interrupt.h> #include <linux/ioport.h> #include <linux/iopoll.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/pinctrl/consumer.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/slab.h> #include "dw-i3c-master.h" #define DEVICE_CTRL … #define DEV_CTRL_ENABLE … #define DEV_CTRL_RESUME … #define DEV_CTRL_HOT_JOIN_NACK … #define DEV_CTRL_I2C_SLAVE_PRESENT … #define DEVICE_ADDR … #define DEV_ADDR_DYNAMIC_ADDR_VALID … #define DEV_ADDR_DYNAMIC(x) … #define HW_CAPABILITY … #define COMMAND_QUEUE_PORT … #define COMMAND_PORT_TOC … #define COMMAND_PORT_READ_TRANSFER … #define COMMAND_PORT_SDAP … #define COMMAND_PORT_ROC … #define COMMAND_PORT_SPEED(x) … #define COMMAND_PORT_DEV_INDEX(x) … #define COMMAND_PORT_CP … #define COMMAND_PORT_CMD(x) … #define COMMAND_PORT_TID(x) … #define COMMAND_PORT_ARG_DATA_LEN(x) … #define COMMAND_PORT_ARG_DATA_LEN_MAX … #define COMMAND_PORT_TRANSFER_ARG … #define COMMAND_PORT_SDA_DATA_BYTE_3(x) … #define COMMAND_PORT_SDA_DATA_BYTE_2(x) … #define COMMAND_PORT_SDA_DATA_BYTE_1(x) … #define COMMAND_PORT_SDA_BYTE_STRB_3 … #define COMMAND_PORT_SDA_BYTE_STRB_2 … #define COMMAND_PORT_SDA_BYTE_STRB_1 … #define COMMAND_PORT_SHORT_DATA_ARG … #define COMMAND_PORT_DEV_COUNT(x) … #define COMMAND_PORT_ADDR_ASSGN_CMD … #define RESPONSE_QUEUE_PORT … #define RESPONSE_PORT_ERR_STATUS(x) … #define RESPONSE_NO_ERROR … #define RESPONSE_ERROR_CRC … #define RESPONSE_ERROR_PARITY … #define RESPONSE_ERROR_FRAME … #define RESPONSE_ERROR_IBA_NACK … #define RESPONSE_ERROR_ADDRESS_NACK … #define RESPONSE_ERROR_OVER_UNDER_FLOW … #define RESPONSE_ERROR_TRANSF_ABORT … #define RESPONSE_ERROR_I2C_W_NACK_ERR … #define RESPONSE_PORT_TID(x) … #define RESPONSE_PORT_DATA_LEN(x) … #define RX_TX_DATA_PORT … #define IBI_QUEUE_STATUS … #define IBI_QUEUE_STATUS_IBI_ID(x) … #define IBI_QUEUE_STATUS_DATA_LEN(x) … #define IBI_QUEUE_IBI_ADDR(x) … #define IBI_QUEUE_IBI_RNW(x) … #define IBI_TYPE_MR(x) … #define IBI_TYPE_HJ(x) … #define IBI_TYPE_SIRQ(x) … #define QUEUE_THLD_CTRL … #define QUEUE_THLD_CTRL_IBI_STAT_MASK … #define QUEUE_THLD_CTRL_IBI_STAT(x) … #define QUEUE_THLD_CTRL_IBI_DATA_MASK … #define QUEUE_THLD_CTRL_IBI_DATA(x) … #define QUEUE_THLD_CTRL_RESP_BUF_MASK … #define QUEUE_THLD_CTRL_RESP_BUF(x) … #define DATA_BUFFER_THLD_CTRL … #define DATA_BUFFER_THLD_CTRL_RX_BUF … #define IBI_QUEUE_CTRL … #define IBI_MR_REQ_REJECT … #define IBI_SIR_REQ_REJECT … #define IBI_REQ_REJECT_ALL … #define RESET_CTRL … #define RESET_CTRL_IBI_QUEUE … #define RESET_CTRL_RX_FIFO … #define RESET_CTRL_TX_FIFO … #define RESET_CTRL_RESP_QUEUE … #define RESET_CTRL_CMD_QUEUE … #define RESET_CTRL_SOFT … #define SLV_EVENT_CTRL … #define INTR_STATUS … #define INTR_STATUS_EN … #define INTR_SIGNAL_EN … #define INTR_FORCE … #define INTR_BUSOWNER_UPDATE_STAT … #define INTR_IBI_UPDATED_STAT … #define INTR_READ_REQ_RECV_STAT … #define INTR_DEFSLV_STAT … #define INTR_TRANSFER_ERR_STAT … #define INTR_DYN_ADDR_ASSGN_STAT … #define INTR_CCC_UPDATED_STAT … #define INTR_TRANSFER_ABORT_STAT … #define INTR_RESP_READY_STAT … #define INTR_CMD_QUEUE_READY_STAT … #define INTR_IBI_THLD_STAT … #define INTR_RX_THLD_STAT … #define INTR_TX_THLD_STAT … #define INTR_ALL … #define INTR_MASTER_MASK … #define QUEUE_STATUS_LEVEL … #define QUEUE_STATUS_IBI_STATUS_CNT(x) … #define QUEUE_STATUS_IBI_BUF_BLR(x) … #define QUEUE_STATUS_LEVEL_RESP(x) … #define QUEUE_STATUS_LEVEL_CMD(x) … #define DATA_BUFFER_STATUS_LEVEL … #define DATA_BUFFER_STATUS_LEVEL_TX(x) … #define PRESENT_STATE … #define CCC_DEVICE_STATUS … #define DEVICE_ADDR_TABLE_POINTER … #define DEVICE_ADDR_TABLE_DEPTH(x) … #define DEVICE_ADDR_TABLE_ADDR(x) … #define DEV_CHAR_TABLE_POINTER … #define VENDOR_SPECIFIC_REG_POINTER … #define SLV_PID_VALUE … #define SLV_CHAR_CTRL … #define SLV_MAX_LEN … #define MAX_READ_TURNAROUND … #define MAX_DATA_SPEED … #define SLV_DEBUG_STATUS … #define SLV_INTR_REQ … #define DEVICE_CTRL_EXTENDED … #define SCL_I3C_OD_TIMING … #define SCL_I3C_PP_TIMING … #define SCL_I3C_TIMING_HCNT(x) … #define SCL_I3C_TIMING_LCNT(x) … #define SCL_I3C_TIMING_CNT_MIN … #define SCL_I2C_FM_TIMING … #define SCL_I2C_FM_TIMING_HCNT(x) … #define SCL_I2C_FM_TIMING_LCNT(x) … #define SCL_I2C_FMP_TIMING … #define SCL_I2C_FMP_TIMING_HCNT(x) … #define SCL_I2C_FMP_TIMING_LCNT(x) … #define SCL_EXT_LCNT_TIMING … #define SCL_EXT_LCNT_4(x) … #define SCL_EXT_LCNT_3(x) … #define SCL_EXT_LCNT_2(x) … #define SCL_EXT_LCNT_1(x) … #define SCL_EXT_TERMN_LCNT_TIMING … #define BUS_FREE_TIMING … #define BUS_I3C_MST_FREE(x) … #define BUS_IDLE_TIMING … #define I3C_VER_ID … #define I3C_VER_TYPE … #define EXTENDED_CAPABILITY … #define SLAVE_CONFIG … #define DEV_ADDR_TABLE_IBI_MDB … #define DEV_ADDR_TABLE_SIR_REJECT … #define DEV_ADDR_TABLE_LEGACY_I2C_DEV … #define DEV_ADDR_TABLE_DYNAMIC_ADDR(x) … #define DEV_ADDR_TABLE_STATIC_ADDR(x) … #define DEV_ADDR_TABLE_LOC(start, idx) … #define I3C_BUS_SDR1_SCL_RATE … #define I3C_BUS_SDR2_SCL_RATE … #define I3C_BUS_SDR3_SCL_RATE … #define I3C_BUS_SDR4_SCL_RATE … #define I3C_BUS_I2C_FM_TLOW_MIN_NS … #define I3C_BUS_I2C_FMP_TLOW_MIN_NS … #define I3C_BUS_THIGH_MAX_NS … #define XFER_TIMEOUT … #define RPM_AUTOSUSPEND_TIMEOUT … struct dw_i3c_cmd { … }; struct dw_i3c_xfer { … }; struct dw_i3c_i2c_dev_data { … }; static u8 even_parity(u8 p) { … } static bool dw_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, const struct i3c_ccc_cmd *cmd) { … } static inline struct dw_i3c_master * to_dw_i3c_master(struct i3c_master_controller *master) { … } static void dw_i3c_master_disable(struct dw_i3c_master *master) { … } static void dw_i3c_master_enable(struct dw_i3c_master *master) { … } static int dw_i3c_master_get_addr_pos(struct dw_i3c_master *master, u8 addr) { … } static int dw_i3c_master_get_free_pos(struct dw_i3c_master *master) { … } static void dw_i3c_master_wr_tx_fifo(struct dw_i3c_master *master, const u8 *bytes, int nbytes) { … } static void dw_i3c_master_read_fifo(struct dw_i3c_master *master, int reg, u8 *bytes, int nbytes) { … } static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master, u8 *bytes, int nbytes) { … } static void dw_i3c_master_read_ibi_fifo(struct dw_i3c_master *master, u8 *bytes, int nbytes) { … } static struct dw_i3c_xfer * dw_i3c_master_alloc_xfer(struct dw_i3c_master *master, unsigned int ncmds) { … } static void dw_i3c_master_free_xfer(struct dw_i3c_xfer *xfer) { … } static void dw_i3c_master_start_xfer_locked(struct dw_i3c_master *master) { … } static void dw_i3c_master_enqueue_xfer(struct dw_i3c_master *master, struct dw_i3c_xfer *xfer) { … } static void dw_i3c_master_dequeue_xfer_locked(struct dw_i3c_master *master, struct dw_i3c_xfer *xfer) { … } static void dw_i3c_master_dequeue_xfer(struct dw_i3c_master *master, struct dw_i3c_xfer *xfer) { … } static void dw_i3c_master_end_xfer_locked(struct dw_i3c_master *master, u32 isr) { … } static void dw_i3c_master_set_intr_regs(struct dw_i3c_master *master) { … } static int dw_i3c_clk_cfg(struct dw_i3c_master *master) { … } static int dw_i2c_clk_cfg(struct dw_i3c_master *master) { … } static int dw_i3c_master_bus_init(struct i3c_master_controller *m) { … } static void dw_i3c_master_bus_cleanup(struct i3c_master_controller *m) { … } static int dw_i3c_ccc_set(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) { … } static int dw_i3c_ccc_get(struct dw_i3c_master *master, struct i3c_ccc_cmd *ccc) { … } static int dw_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, struct i3c_ccc_cmd *ccc) { … } static int dw_i3c_master_daa(struct i3c_master_controller *m) { … } static int dw_i3c_master_priv_xfers(struct i3c_dev_desc *dev, struct i3c_priv_xfer *i3c_xfers, int i3c_nxfers) { … } static int dw_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 old_dyn_addr) { … } static int dw_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) { … } static void dw_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) { … } static int dw_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, const struct i2c_msg *i2c_xfers, int i2c_nxfers) { … } static int dw_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) { … } static void dw_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) { … } static int dw_i3c_master_request_ibi(struct i3c_dev_desc *dev, const struct i3c_ibi_setup *req) { … } static void dw_i3c_master_free_ibi(struct i3c_dev_desc *dev) { … } static void dw_i3c_master_enable_sir_signal(struct dw_i3c_master *master, bool enable) { … } static void dw_i3c_master_set_sir_enabled(struct dw_i3c_master *master, struct i3c_dev_desc *dev, u8 idx, bool enable) { … } static int dw_i3c_master_enable_hotjoin(struct i3c_master_controller *m) { … } static int dw_i3c_master_disable_hotjoin(struct i3c_master_controller *m) { … } static int dw_i3c_master_enable_ibi(struct i3c_dev_desc *dev) { … } static int dw_i3c_master_disable_ibi(struct i3c_dev_desc *dev) { … } static void dw_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot) { … } static void dw_i3c_master_drain_ibi_queue(struct dw_i3c_master *master, int len) { … } static void dw_i3c_master_handle_ibi_sir(struct dw_i3c_master *master, u32 status) { … } /* "ibis": referring to In-Band Interrupts, and not * https://en.wikipedia.org/wiki/Australian_white_ibis. The latter should * not be handled. */ static void dw_i3c_master_irq_handle_ibis(struct dw_i3c_master *master) { … } static irqreturn_t dw_i3c_master_irq_handler(int irq, void *dev_id) { … } static const struct i3c_master_controller_ops dw_mipi_i3c_ops = …; /* default platform ops implementations */ static int dw_i3c_platform_init_nop(struct dw_i3c_master *i3c) { … } static void dw_i3c_platform_set_dat_ibi_nop(struct dw_i3c_master *i3c, struct i3c_dev_desc *dev, bool enable, u32 *dat) { … } static const struct dw_i3c_platform_ops dw_i3c_platform_ops_default = …; static void dw_i3c_hj_work(struct work_struct *work) { … } int dw_i3c_common_probe(struct dw_i3c_master *master, struct platform_device *pdev) { … } EXPORT_SYMBOL_GPL(…); void dw_i3c_common_remove(struct dw_i3c_master *master) { … } EXPORT_SYMBOL_GPL(…); /* base platform implementation */ static int dw_i3c_probe(struct platform_device *pdev) { … } static void dw_i3c_remove(struct platform_device *pdev) { … } static void dw_i3c_master_restore_addrs(struct dw_i3c_master *master) { … } static void dw_i3c_master_restore_timing_regs(struct dw_i3c_master *master) { … } static int dw_i3c_master_enable_clks(struct dw_i3c_master *master) { … } static inline void dw_i3c_master_disable_clks(struct dw_i3c_master *master) { … } static int __maybe_unused dw_i3c_master_runtime_suspend(struct device *dev) { … } static int __maybe_unused dw_i3c_master_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops dw_i3c_pm_ops = …; static const struct of_device_id dw_i3c_master_of_match[] = …; MODULE_DEVICE_TABLE(of, dw_i3c_master_of_match); static struct platform_driver dw_i3c_driver = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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