// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2018 Cadence Design Systems Inc. * * Author: Boris Brezillon <[email protected]> */ #include <linux/bitops.h> #include <linux/clk.h> #include <linux/err.h> #include <linux/errno.h> #include <linux/i3c/master.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/iopoll.h> #include <linux/ioport.h> #include <linux/kernel.h> #include <linux/list.h> #include <linux/module.h> #include <linux/of.h> #include <linux/platform_device.h> #include <linux/slab.h> #include <linux/spinlock.h> #include <linux/workqueue.h> #define DEV_ID … #define DEV_ID_I3C_MASTER … #define CONF_STATUS0 … #define CONF_STATUS0_CMDR_DEPTH(x) … #define CONF_STATUS0_ECC_CHK … #define CONF_STATUS0_INTEG_CHK … #define CONF_STATUS0_CSR_DAP_CHK … #define CONF_STATUS0_TRANS_TOUT_CHK … #define CONF_STATUS0_PROT_FAULTS_CHK … #define CONF_STATUS0_GPO_NUM(x) … #define CONF_STATUS0_GPI_NUM(x) … #define CONF_STATUS0_IBIR_DEPTH(x) … #define CONF_STATUS0_SUPPORTS_DDR … #define CONF_STATUS0_SEC_MASTER … #define CONF_STATUS0_DEVS_NUM(x) … #define CONF_STATUS1 … #define CONF_STATUS1_IBI_HW_RES(x) … #define CONF_STATUS1_CMD_DEPTH(x) … #define CONF_STATUS1_SLVDDR_RX_DEPTH(x) … #define CONF_STATUS1_SLVDDR_TX_DEPTH(x) … #define CONF_STATUS1_IBI_DEPTH(x) … #define CONF_STATUS1_RX_DEPTH(x) … #define CONF_STATUS1_TX_DEPTH(x) … #define REV_ID … #define REV_ID_VID(id) … #define REV_ID_PID(id) … #define REV_ID_REV_MAJOR(id) … #define REV_ID_REV_MINOR(id) … #define CTRL … #define CTRL_DEV_EN … #define CTRL_HALT_EN … #define CTRL_MCS … #define CTRL_MCS_EN … #define CTRL_THD_DELAY(x) … #define CTRL_HJ_DISEC … #define CTRL_MST_ACK … #define CTRL_HJ_ACK … #define CTRL_HJ_INIT … #define CTRL_MST_INIT … #define CTRL_AHDR_OPT … #define CTRL_PURE_BUS_MODE … #define CTRL_MIXED_FAST_BUS_MODE … #define CTRL_MIXED_SLOW_BUS_MODE … #define CTRL_BUS_MODE_MASK … #define THD_DELAY_MAX … #define PRESCL_CTRL0 … #define PRESCL_CTRL0_I2C(x) … #define PRESCL_CTRL0_I3C(x) … #define PRESCL_CTRL0_I3C_MAX … #define PRESCL_CTRL0_I2C_MAX … #define PRESCL_CTRL1 … #define PRESCL_CTRL1_PP_LOW_MASK … #define PRESCL_CTRL1_PP_LOW(x) … #define PRESCL_CTRL1_OD_LOW_MASK … #define PRESCL_CTRL1_OD_LOW(x) … #define MST_IER … #define MST_IDR … #define MST_IMR … #define MST_ICR … #define MST_ISR … #define MST_INT_HALTED … #define MST_INT_MR_DONE … #define MST_INT_IMM_COMP … #define MST_INT_TX_THR … #define MST_INT_TX_OVF … #define MST_INT_IBID_THR … #define MST_INT_IBID_UNF … #define MST_INT_IBIR_THR … #define MST_INT_IBIR_UNF … #define MST_INT_IBIR_OVF … #define MST_INT_RX_THR … #define MST_INT_RX_UNF … #define MST_INT_CMDD_EMP … #define MST_INT_CMDD_THR … #define MST_INT_CMDD_OVF … #define MST_INT_CMDR_THR … #define MST_INT_CMDR_UNF … #define MST_INT_CMDR_OVF … #define MST_STATUS0 … #define MST_STATUS0_IDLE … #define MST_STATUS0_HALTED … #define MST_STATUS0_MASTER_MODE … #define MST_STATUS0_TX_FULL … #define MST_STATUS0_IBID_FULL … #define MST_STATUS0_IBIR_FULL … #define MST_STATUS0_RX_FULL … #define MST_STATUS0_CMDD_FULL … #define MST_STATUS0_CMDR_FULL … #define MST_STATUS0_TX_EMP … #define MST_STATUS0_IBID_EMP … #define MST_STATUS0_IBIR_EMP … #define MST_STATUS0_RX_EMP … #define MST_STATUS0_CMDD_EMP … #define MST_STATUS0_CMDR_EMP … #define CMDR … #define CMDR_NO_ERROR … #define CMDR_DDR_PREAMBLE_ERROR … #define CMDR_DDR_PARITY_ERROR … #define CMDR_DDR_RX_FIFO_OVF … #define CMDR_DDR_TX_FIFO_UNF … #define CMDR_M0_ERROR … #define CMDR_M1_ERROR … #define CMDR_M2_ERROR … #define CMDR_MST_ABORT … #define CMDR_NACK_RESP … #define CMDR_INVALID_DA … #define CMDR_DDR_DROPPED … #define CMDR_ERROR(x) … #define CMDR_XFER_BYTES(x) … #define CMDR_CMDID_HJACK_DISEC … #define CMDR_CMDID_HJACK_ENTDAA … #define CMDR_CMDID(x) … #define IBIR … #define IBIR_ACKED … #define IBIR_SLVID(x) … #define IBIR_ERROR … #define IBIR_XFER_BYTES(x) … #define IBIR_TYPE_IBI … #define IBIR_TYPE_HJ … #define IBIR_TYPE_MR … #define IBIR_TYPE(x) … #define SLV_IER … #define SLV_IDR … #define SLV_IMR … #define SLV_ICR … #define SLV_ISR … #define SLV_INT_TM … #define SLV_INT_ERROR … #define SLV_INT_EVENT_UP … #define SLV_INT_HJ_DONE … #define SLV_INT_MR_DONE … #define SLV_INT_DA_UPD … #define SLV_INT_SDR_FAIL … #define SLV_INT_DDR_FAIL … #define SLV_INT_M_RD_ABORT … #define SLV_INT_DDR_RX_THR … #define SLV_INT_DDR_TX_THR … #define SLV_INT_SDR_RX_THR … #define SLV_INT_SDR_TX_THR … #define SLV_INT_DDR_RX_UNF … #define SLV_INT_DDR_TX_OVF … #define SLV_INT_SDR_RX_UNF … #define SLV_INT_SDR_TX_OVF … #define SLV_INT_DDR_RD_COMP … #define SLV_INT_DDR_WR_COMP … #define SLV_INT_SDR_RD_COMP … #define SLV_INT_SDR_WR_COMP … #define SLV_STATUS0 … #define SLV_STATUS0_REG_ADDR(s) … #define SLV_STATUS0_XFRD_BYTES(s) … #define SLV_STATUS1 … #define SLV_STATUS1_AS(s) … #define SLV_STATUS1_VEN_TM … #define SLV_STATUS1_HJ_DIS … #define SLV_STATUS1_MR_DIS … #define SLV_STATUS1_PROT_ERR … #define SLV_STATUS1_DA(s) … #define SLV_STATUS1_HAS_DA … #define SLV_STATUS1_DDR_RX_FULL … #define SLV_STATUS1_DDR_TX_FULL … #define SLV_STATUS1_DDR_RX_EMPTY … #define SLV_STATUS1_DDR_TX_EMPTY … #define SLV_STATUS1_SDR_RX_FULL … #define SLV_STATUS1_SDR_TX_FULL … #define SLV_STATUS1_SDR_RX_EMPTY … #define SLV_STATUS1_SDR_TX_EMPTY … #define CMD0_FIFO … #define CMD0_FIFO_IS_DDR … #define CMD0_FIFO_IS_CCC … #define CMD0_FIFO_BCH … #define XMIT_BURST_STATIC_SUBADDR … #define XMIT_SINGLE_INC_SUBADDR … #define XMIT_SINGLE_STATIC_SUBADDR … #define XMIT_BURST_WITHOUT_SUBADDR … #define CMD0_FIFO_PRIV_XMIT_MODE(m) … #define CMD0_FIFO_SBCA … #define CMD0_FIFO_RSBC … #define CMD0_FIFO_IS_10B … #define CMD0_FIFO_PL_LEN(l) … #define CMD0_FIFO_PL_LEN_MAX … #define CMD0_FIFO_DEV_ADDR(a) … #define CMD0_FIFO_RNW … #define CMD1_FIFO … #define CMD1_FIFO_CMDID(id) … #define CMD1_FIFO_CSRADDR(a) … #define CMD1_FIFO_CCC(id) … #define TX_FIFO … #define IMD_CMD0 … #define IMD_CMD0_PL_LEN(l) … #define IMD_CMD0_DEV_ADDR(a) … #define IMD_CMD0_RNW … #define IMD_CMD1 … #define IMD_CMD1_CCC(id) … #define IMD_DATA … #define RX_FIFO … #define IBI_DATA_FIFO … #define SLV_DDR_TX_FIFO … #define SLV_DDR_RX_FIFO … #define CMD_IBI_THR_CTRL … #define IBIR_THR(t) … #define CMDR_THR(t) … #define IBI_THR(t) … #define CMD_THR(t) … #define TX_RX_THR_CTRL … #define RX_THR(t) … #define TX_THR(t) … #define SLV_DDR_TX_RX_THR_CTRL … #define SLV_DDR_RX_THR(t) … #define SLV_DDR_TX_THR(t) … #define FLUSH_CTRL … #define FLUSH_IBI_RESP … #define FLUSH_CMD_RESP … #define FLUSH_SLV_DDR_RX_FIFO … #define FLUSH_SLV_DDR_TX_FIFO … #define FLUSH_IMM_FIFO … #define FLUSH_IBI_FIFO … #define FLUSH_RX_FIFO … #define FLUSH_TX_FIFO … #define FLUSH_CMD_FIFO … #define TTO_PRESCL_CTRL0 … #define TTO_PRESCL_CTRL0_DIVB(x) … #define TTO_PRESCL_CTRL0_DIVA(x) … #define TTO_PRESCL_CTRL1 … #define TTO_PRESCL_CTRL1_DIVB(x) … #define TTO_PRESCL_CTRL1_DIVA(x) … #define DEVS_CTRL … #define DEVS_CTRL_DEV_CLR_SHIFT … #define DEVS_CTRL_DEV_CLR_ALL … #define DEVS_CTRL_DEV_CLR(dev) … #define DEVS_CTRL_DEV_ACTIVE(dev) … #define DEVS_CTRL_DEVS_ACTIVE_MASK … #define MAX_DEVS … #define DEV_ID_RR0(d) … #define DEV_ID_RR0_LVR_EXT_ADDR … #define DEV_ID_RR0_HDR_CAP … #define DEV_ID_RR0_IS_I3C … #define DEV_ID_RR0_DEV_ADDR_MASK … #define DEV_ID_RR0_SET_DEV_ADDR(a) … #define DEV_ID_RR0_GET_DEV_ADDR(x) … #define DEV_ID_RR1(d) … #define DEV_ID_RR1_PID_MSB(pid) … #define DEV_ID_RR2(d) … #define DEV_ID_RR2_PID_LSB(pid) … #define DEV_ID_RR2_BCR(bcr) … #define DEV_ID_RR2_DCR(dcr) … #define DEV_ID_RR2_LVR(lvr) … #define SIR_MAP(x) … #define SIR_MAP_DEV_REG(d) … #define SIR_MAP_DEV_SHIFT(d, fs) … #define SIR_MAP_DEV_CONF_MASK(d) … #define SIR_MAP_DEV_CONF(d, c) … #define DEV_ROLE_SLAVE … #define DEV_ROLE_MASTER … #define SIR_MAP_DEV_ROLE(role) … #define SIR_MAP_DEV_SLOW … #define SIR_MAP_DEV_PL(l) … #define SIR_MAP_PL_MAX … #define SIR_MAP_DEV_DA(a) … #define SIR_MAP_DEV_ACK … #define GPIR_WORD(x) … #define GPI_REG(val, id) … #define GPOR_WORD(x) … #define GPO_REG(val, id) … #define ASF_INT_STATUS … #define ASF_INT_RAW_STATUS … #define ASF_INT_MASK … #define ASF_INT_TEST … #define ASF_INT_FATAL_SELECT … #define ASF_INTEGRITY_ERR … #define ASF_PROTOCOL_ERR … #define ASF_TRANS_TIMEOUT_ERR … #define ASF_CSR_ERR … #define ASF_DAP_ERR … #define ASF_SRAM_UNCORR_ERR … #define ASF_SRAM_CORR_ERR … #define ASF_SRAM_CORR_FAULT_STATUS … #define ASF_SRAM_UNCORR_FAULT_STATUS … #define ASF_SRAM_CORR_FAULT_INSTANCE(x) … #define ASF_SRAM_CORR_FAULT_ADDR(x) … #define ASF_SRAM_FAULT_STATS … #define ASF_SRAM_FAULT_UNCORR_STATS(x) … #define ASF_SRAM_FAULT_CORR_STATS(x) … #define ASF_TRANS_TOUT_CTRL … #define ASF_TRANS_TOUT_EN … #define ASF_TRANS_TOUT_VAL(x) … #define ASF_TRANS_TOUT_FAULT_MASK … #define ASF_TRANS_TOUT_FAULT_STATUS … #define ASF_TRANS_TOUT_FAULT_APB … #define ASF_TRANS_TOUT_FAULT_SCL_LOW … #define ASF_TRANS_TOUT_FAULT_SCL_HIGH … #define ASF_TRANS_TOUT_FAULT_FSCL_HIGH … #define ASF_PROTO_FAULT_MASK … #define ASF_PROTO_FAULT_STATUS … #define ASF_PROTO_FAULT_SLVSDR_RD_ABORT … #define ASF_PROTO_FAULT_SLVDDR_FAIL … #define ASF_PROTO_FAULT_S(x) … #define ASF_PROTO_FAULT_MSTSDR_RD_ABORT … #define ASF_PROTO_FAULT_MSTDDR_FAIL … #define ASF_PROTO_FAULT_M(x) … struct cdns_i3c_master_caps { … }; struct cdns_i3c_cmd { … }; struct cdns_i3c_xfer { … }; struct cdns_i3c_data { … }; struct cdns_i3c_master { … }; static inline struct cdns_i3c_master * to_cdns_i3c_master(struct i3c_master_controller *master) { … } static void cdns_i3c_master_wr_to_tx_fifo(struct cdns_i3c_master *master, const u8 *bytes, int nbytes) { … } static void cdns_i3c_master_rd_from_rx_fifo(struct cdns_i3c_master *master, u8 *bytes, int nbytes) { … } static bool cdns_i3c_master_supports_ccc_cmd(struct i3c_master_controller *m, const struct i3c_ccc_cmd *cmd) { … } static int cdns_i3c_master_disable(struct cdns_i3c_master *master) { … } static void cdns_i3c_master_enable(struct cdns_i3c_master *master) { … } static struct cdns_i3c_xfer * cdns_i3c_master_alloc_xfer(struct cdns_i3c_master *master, unsigned int ncmds) { … } static void cdns_i3c_master_free_xfer(struct cdns_i3c_xfer *xfer) { … } static void cdns_i3c_master_start_xfer_locked(struct cdns_i3c_master *master) { … } static void cdns_i3c_master_end_xfer_locked(struct cdns_i3c_master *master, u32 isr) { … } static void cdns_i3c_master_queue_xfer(struct cdns_i3c_master *master, struct cdns_i3c_xfer *xfer) { … } static void cdns_i3c_master_unqueue_xfer(struct cdns_i3c_master *master, struct cdns_i3c_xfer *xfer) { … } static enum i3c_error_code cdns_i3c_cmd_get_err(struct cdns_i3c_cmd *cmd) { … } static int cdns_i3c_master_send_ccc_cmd(struct i3c_master_controller *m, struct i3c_ccc_cmd *cmd) { … } static int cdns_i3c_master_priv_xfers(struct i3c_dev_desc *dev, struct i3c_priv_xfer *xfers, int nxfers) { … } static int cdns_i3c_master_i2c_xfers(struct i2c_dev_desc *dev, const struct i2c_msg *xfers, int nxfers) { … } struct cdns_i3c_i2c_dev_data { … }; static u32 prepare_rr0_dev_address(u32 addr) { … } static void cdns_i3c_master_upd_i3c_addr(struct i3c_dev_desc *dev) { … } static int cdns_i3c_master_get_rr_slot(struct cdns_i3c_master *master, u8 dyn_addr) { … } static int cdns_i3c_master_reattach_i3c_dev(struct i3c_dev_desc *dev, u8 old_dyn_addr) { … } static int cdns_i3c_master_attach_i3c_dev(struct i3c_dev_desc *dev) { … } static void cdns_i3c_master_detach_i3c_dev(struct i3c_dev_desc *dev) { … } static int cdns_i3c_master_attach_i2c_dev(struct i2c_dev_desc *dev) { … } static void cdns_i3c_master_detach_i2c_dev(struct i2c_dev_desc *dev) { … } static void cdns_i3c_master_bus_cleanup(struct i3c_master_controller *m) { … } static void cdns_i3c_master_dev_rr_to_info(struct cdns_i3c_master *master, unsigned int slot, struct i3c_device_info *info) { … } static void cdns_i3c_master_upd_i3c_scl_lim(struct cdns_i3c_master *master) { … } static int cdns_i3c_master_do_daa(struct i3c_master_controller *m) { … } static u8 cdns_i3c_master_calculate_thd_delay(struct cdns_i3c_master *master) { … } static int cdns_i3c_master_bus_init(struct i3c_master_controller *m) { … } static void cdns_i3c_master_handle_ibi(struct cdns_i3c_master *master, u32 ibir) { … } static void cnds_i3c_master_demux_ibis(struct cdns_i3c_master *master) { … } static irqreturn_t cdns_i3c_master_interrupt(int irq, void *data) { … } static int cdns_i3c_master_disable_ibi(struct i3c_dev_desc *dev) { … } static int cdns_i3c_master_enable_ibi(struct i3c_dev_desc *dev) { … } static int cdns_i3c_master_request_ibi(struct i3c_dev_desc *dev, const struct i3c_ibi_setup *req) { … } static void cdns_i3c_master_free_ibi(struct i3c_dev_desc *dev) { … } static void cdns_i3c_master_recycle_ibi_slot(struct i3c_dev_desc *dev, struct i3c_ibi_slot *slot) { … } static const struct i3c_master_controller_ops cdns_i3c_master_ops = …; static void cdns_i3c_master_hj(struct work_struct *work) { … } static struct cdns_i3c_data cdns_i3c_devdata = …; static const struct of_device_id cdns_i3c_master_of_ids[] = …; MODULE_DEVICE_TABLE(of, cdns_i3c_master_of_ids); static int cdns_i3c_master_probe(struct platform_device *pdev) { … } static void cdns_i3c_master_remove(struct platform_device *pdev) { … } static struct platform_driver cdns_i3c_master = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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