// SPDX-License-Identifier: GPL-2.0-or-later /* * Driver for the Conexant CX2584x Audio/Video decoder chip and related cores * * Integrated Consumer Infrared Controller * * Copyright (C) 2010 Andy Walls <[email protected]> */ #include <linux/slab.h> #include <linux/kfifo.h> #include <linux/module.h> #include <media/drv-intf/cx25840.h> #include <media/rc-core.h> #include "cx25840-core.h" static unsigned int ir_debug; module_param(ir_debug, int, 0644); MODULE_PARM_DESC(…) …; #define CX25840_IR_REG_BASE … #define CX25840_IR_CNTRL_REG … #define CNTRL_WIN_3_3 … #define CNTRL_WIN_4_3 … #define CNTRL_WIN_3_4 … #define CNTRL_WIN_4_4 … #define CNTRL_WIN … #define CNTRL_EDG_NONE … #define CNTRL_EDG_FALL … #define CNTRL_EDG_RISE … #define CNTRL_EDG_BOTH … #define CNTRL_EDG … #define CNTRL_DMD … #define CNTRL_MOD … #define CNTRL_RFE … #define CNTRL_TFE … #define CNTRL_RXE … #define CNTRL_TXE … #define CNTRL_RIC … #define CNTRL_TIC … #define CNTRL_CPL … #define CNTRL_LBM … #define CNTRL_R … #define CX25840_IR_TXCLK_REG … #define TXCLK_TCD … #define CX25840_IR_RXCLK_REG … #define RXCLK_RCD … #define CX25840_IR_CDUTY_REG … #define CDUTY_CDC … #define CX25840_IR_STATS_REG … #define STATS_RTO … #define STATS_ROR … #define STATS_RBY … #define STATS_TBY … #define STATS_RSR … #define STATS_TSR … #define CX25840_IR_IRQEN_REG … #define IRQEN_RTE … #define IRQEN_ROE … #define IRQEN_RSE … #define IRQEN_TSE … #define IRQEN_MSK … #define CX25840_IR_FILTR_REG … #define FILTR_LPF … #define CX25840_IR_FIFO_REG … #define FIFO_RXTX … #define FIFO_RXTX_LVL … #define FIFO_RXTX_RTO … #define FIFO_RX_NDV … #define FIFO_RX_DEPTH … #define FIFO_TX_DEPTH … #define CX25840_VIDCLK_FREQ … #define CX25840_IR_REFCLK_FREQ … /* * We use this union internally for convenience, but callers to tx_write * and rx_read will be expecting records of type struct ir_raw_event. * Always ensure the size of this union is dictated by struct ir_raw_event. */ cx25840_ir_fifo_rec; #define CX25840_IR_RX_KFIFO_SIZE … #define CX25840_IR_TX_KFIFO_SIZE … struct cx25840_ir_state { … }; static inline struct cx25840_ir_state *to_ir_state(struct v4l2_subdev *sd) { … } /* * Rx and Tx Clock Divider register computations * * Note the largest clock divider value of 0xffff corresponds to: * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns * which fits in 21 bits, so we'll use unsigned int for time arguments. */ static inline u16 count_to_clock_divider(unsigned int d) { … } static inline u16 carrier_freq_to_clock_divider(unsigned int freq) { … } static inline unsigned int clock_divider_to_carrier_freq(unsigned int divider) { … } static inline unsigned int clock_divider_to_freq(unsigned int divider, unsigned int rollovers) { … } /* * Low Pass Filter register calculations * * Note the largest count value of 0xffff corresponds to: * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns * which fits in 21 bits, so we'll use unsigned int for time arguments. */ static inline u16 count_to_lpf_count(unsigned int d) { … } static inline u16 ns_to_lpf_count(unsigned int ns) { … } static inline unsigned int lpf_count_to_ns(unsigned int count) { … } static inline unsigned int lpf_count_to_us(unsigned int count) { … } /* * FIFO register pulse width count computations */ static u32 clock_divider_to_resolution(u16 divider) { … } static u64 pulse_width_count_to_ns(u16 count, u16 divider) { … } #if 0 /* Keep as we will need this for Transmit functionality */ static u16 ns_to_pulse_width_count(u32 ns, u16 divider) { u64 n; u32 d; u32 rem; /* * The 2 lsb's of the pulse width timer count are not accessible, hence * the (1 << 2) */ n = ((u64) ns) * CX25840_IR_REFCLK_FREQ / 1000000; /* millicycles */ d = (1 << 2) * ((u32) divider + 1) * 1000; /* millicycles/count */ rem = do_div(n, d); if (rem >= d / 2) n++; if (n > FIFO_RXTX) n = FIFO_RXTX; else if (n == 0) n = 1; return (u16) n; } #endif static unsigned int pulse_width_count_to_us(u16 count, u16 divider) { … } /* * Pulse Clocks computations: Combined Pulse Width Count & Rx Clock Counts * * The total pulse clock count is an 18 bit pulse width timer count as the most * significant part and (up to) 16 bit clock divider count as a modulus. * When the Rx clock divider ticks down to 0, it increments the 18 bit pulse * width timer count's least significant bit. */ static u64 ns_to_pulse_clocks(u32 ns) { … } static u16 pulse_clocks_to_clock_divider(u64 count) { … } /* * IR Control Register helpers */ enum tx_fifo_watermark { … }; enum rx_fifo_watermark { … }; static inline void control_tx_irq_watermark(struct i2c_client *c, enum tx_fifo_watermark level) { … } static inline void control_rx_irq_watermark(struct i2c_client *c, enum rx_fifo_watermark level) { … } static inline void control_tx_enable(struct i2c_client *c, bool enable) { … } static inline void control_rx_enable(struct i2c_client *c, bool enable) { … } static inline void control_tx_modulation_enable(struct i2c_client *c, bool enable) { … } static inline void control_rx_demodulation_enable(struct i2c_client *c, bool enable) { … } static inline void control_rx_s_edge_detection(struct i2c_client *c, u32 edge_types) { … } static void control_rx_s_carrier_window(struct i2c_client *c, unsigned int carrier, unsigned int *carrier_range_low, unsigned int *carrier_range_high) { … } static inline void control_tx_polarity_invert(struct i2c_client *c, bool invert) { … } /* * IR Rx & Tx Clock Register helpers */ static unsigned int txclk_tx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) { … } static unsigned int rxclk_rx_s_carrier(struct i2c_client *c, unsigned int freq, u16 *divider) { … } static u32 txclk_tx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) { … } static u32 rxclk_rx_s_max_pulse_width(struct i2c_client *c, u32 ns, u16 *divider) { … } /* * IR Tx Carrier Duty Cycle register helpers */ static unsigned int cduty_tx_s_duty_cycle(struct i2c_client *c, unsigned int duty_cycle) { … } /* * IR Filter Register helpers */ static u32 filter_rx_s_min_width(struct i2c_client *c, u32 min_width_ns) { … } /* * IR IRQ Enable Register helpers */ static inline void irqenable_rx(struct v4l2_subdev *sd, u32 mask) { … } static inline void irqenable_tx(struct v4l2_subdev *sd, u32 mask) { … } /* * V4L2 Subdevice IR Ops */ int cx25840_ir_irq_handler(struct v4l2_subdev *sd, u32 status, bool *handled) { … } /* Receiver */ static int cx25840_ir_rx_read(struct v4l2_subdev *sd, u8 *buf, size_t count, ssize_t *num) { … } static int cx25840_ir_rx_g_parameters(struct v4l2_subdev *sd, struct v4l2_subdev_ir_parameters *p) { … } static int cx25840_ir_rx_shutdown(struct v4l2_subdev *sd) { … } static int cx25840_ir_rx_s_parameters(struct v4l2_subdev *sd, struct v4l2_subdev_ir_parameters *p) { … } /* Transmitter */ static int cx25840_ir_tx_write(struct v4l2_subdev *sd, u8 *buf, size_t count, ssize_t *num) { … } static int cx25840_ir_tx_g_parameters(struct v4l2_subdev *sd, struct v4l2_subdev_ir_parameters *p) { … } static int cx25840_ir_tx_shutdown(struct v4l2_subdev *sd) { … } static int cx25840_ir_tx_s_parameters(struct v4l2_subdev *sd, struct v4l2_subdev_ir_parameters *p) { … } /* * V4L2 Subdevice Core Ops support */ int cx25840_ir_log_status(struct v4l2_subdev *sd) { … } const struct v4l2_subdev_ir_ops cx25840_ir_ops = …; static const struct v4l2_subdev_ir_parameters default_rx_params = …; static const struct v4l2_subdev_ir_parameters default_tx_params = …; int cx25840_ir_probe(struct v4l2_subdev *sd) { … } int cx25840_ir_remove(struct v4l2_subdev *sd) { … }
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