/* SPDX-License-Identifier: GPL-2.0-only */ /* * adv7842 - Analog Devices ADV7842 video decoder driver * * Copyright 2013 Cisco Systems, Inc. and/or its affiliates. All rights reserved. */ #ifndef _ADV7842_ #define _ADV7842_ /* Analog input muxing modes (AFE register 0x02, [2:0]) */ enum adv7842_ain_sel { … }; /* * Bus rotation and reordering. This is used to specify component reordering on * the board and describes the components order on the bus when the ADV7842 * outputs RGB. */ enum adv7842_bus_order { … }; /* Input Color Space (IO register 0x02, [7:4]) */ enum adv7842_inp_color_space { … }; /* Select output format (IO register 0x03, [4:2]) */ enum adv7842_op_format_mode_sel { … }; /* Mode of operation */ enum adv7842_mode { … }; /* Video standard select (IO register 0x00, [5:0]) */ enum adv7842_vid_std_select { … }; enum adv7842_select_input { … }; enum adv7842_drive_strength { … }; struct adv7842_sdp_csc_coeff { … }; struct adv7842_sdp_io_sync_adjustment { … }; /* Platform dependent definition */ struct adv7842_platform_data { … }; #define V4L2_CID_ADV_RX_ANALOG_SAMPLING_PHASE … #define V4L2_CID_ADV_RX_FREE_RUN_COLOR_MANUAL … #define V4L2_CID_ADV_RX_FREE_RUN_COLOR … /* custom ioctl, used to test the external RAM that's used by the * deinterlacer. */ #define ADV7842_CMD_RAM_TEST … #define ADV7842_EDID_PORT_A … #define ADV7842_EDID_PORT_B … #define ADV7842_EDID_PORT_VGA … #define ADV7842_PAD_SOURCE … #endif
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