linux/drivers/media/i2c/ccs-pll.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * drivers/media/i2c/ccs-pll.c
 *
 * Generic MIPI CCS/SMIA/SMIA++ PLL calculator
 *
 * Copyright (C) 2020 Intel Corporation
 * Copyright (C) 2011--2012 Nokia Corporation
 * Contact: Sakari Ailus <[email protected]>
 */

#include <linux/device.h>
#include <linux/gcd.h>
#include <linux/lcm.h>
#include <linux/module.h>

#include "ccs-pll.h"

/* Return an even number or one. */
static inline u32 clk_div_even(u32 a)
{ … }

/* Return an even number or one. */
static inline u32 clk_div_even_up(u32 a)
{ … }

static inline u32 is_one_or_even(u32 a)
{ … }

static inline u32 one_or_more(u32 a)
{ … }

static int bounds_check(struct device *dev, u32 val,
			u32 min, u32 max, const char *prefix,
			char *str)
{ … }

#define PLL_OP …
#define PLL_VT …

static const char *pll_string(unsigned int which)
{ … }

#define PLL_FL(f) …

static void print_pll(struct device *dev, struct ccs_pll *pll)
{ … }

static u32 op_sys_ddr(u32 flags)
{ … }

static u32 op_pix_ddr(u32 flags)
{ … }

static int check_fr_bounds(struct device *dev,
			   const struct ccs_pll_limits *lim,
			   struct ccs_pll *pll, unsigned int which)
{ … }

static int check_bk_bounds(struct device *dev,
			   const struct ccs_pll_limits *lim,
			   struct ccs_pll *pll, unsigned int which)
{ … }

static int check_ext_bounds(struct device *dev, struct ccs_pll *pll)
{ … }

static void
ccs_pll_find_vt_sys_div(struct device *dev, const struct ccs_pll_limits *lim,
			struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
			u16 min_vt_div, u16 max_vt_div,
			u16 *min_sys_div, u16 *max_sys_div)
{ … }

#define CPHY_CONST …
#define DPHY_CONST …
#define PHY_CONST_DIV …

static inline int
__ccs_pll_calculate_vt_tree(struct device *dev,
			    const struct ccs_pll_limits *lim,
			    struct ccs_pll *pll, u32 mul, u32 div)
{ … }

static int ccs_pll_calculate_vt_tree(struct device *dev,
				     const struct ccs_pll_limits *lim,
				     struct ccs_pll *pll)
{ … }

static void
ccs_pll_calculate_vt(struct device *dev, const struct ccs_pll_limits *lim,
		     const struct ccs_pll_branch_limits_bk *op_lim_bk,
		     struct ccs_pll *pll, struct ccs_pll_branch_fr *pll_fr,
		     struct ccs_pll_branch_bk *op_pll_bk, bool cphy,
		     u32 phy_const)
{ … }

/*
 * Heuristically guess the PLL tree for a given common multiplier and
 * divisor. Begin with the operational timing and continue to video
 * timing once operational timing has been verified.
 *
 * @mul is the PLL multiplier and @div is the common divisor
 * (pre_pll_clk_div and op_sys_clk_div combined). The final PLL
 * multiplier will be a multiple of @mul.
 *
 * @return Zero on success, error code on error.
 */
static int
ccs_pll_calculate_op(struct device *dev, const struct ccs_pll_limits *lim,
		     const struct ccs_pll_branch_limits_fr *op_lim_fr,
		     const struct ccs_pll_branch_limits_bk *op_lim_bk,
		     struct ccs_pll *pll, struct ccs_pll_branch_fr *op_pll_fr,
		     struct ccs_pll_branch_bk *op_pll_bk, u32 mul,
		     u32 div, u32 op_sys_clk_freq_hz_sdr, u32 l,
		     bool cphy, u32 phy_const)
{ … }

int ccs_pll_calculate(struct device *dev, const struct ccs_pll_limits *lim,
		      struct ccs_pll *pll)
{ … }
EXPORT_SYMBOL_GPL(…);

MODULE_AUTHOR(…) …;
MODULE_DESCRIPTION(…) …;
MODULE_LICENSE(…) …;