// SPDX-License-Identifier: GPL-2.0 // Copyright (C) 2018 Intel Corporation #include <linux/acpi.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/pm_runtime.h> #include <linux/regulator/consumer.h> #include <media/v4l2-cci.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #include <linux/unaligned.h> #define IMX258_REG_MODE_SELECT … #define IMX258_MODE_STANDBY … #define IMX258_MODE_STREAMING … #define IMX258_REG_RESET … /* Chip ID */ #define IMX258_REG_CHIP_ID … #define IMX258_CHIP_ID … /* V_TIMING internal */ #define IMX258_VTS_30FPS … #define IMX258_VTS_30FPS_2K … #define IMX258_VTS_30FPS_VGA … #define IMX258_VTS_MAX … /* HBLANK control - read only */ #define IMX258_PPL_DEFAULT … /* Exposure control */ #define IMX258_REG_EXPOSURE … #define IMX258_EXPOSURE_OFFSET … #define IMX258_EXPOSURE_MIN … #define IMX258_EXPOSURE_STEP … #define IMX258_EXPOSURE_DEFAULT … #define IMX258_EXPOSURE_MAX … /* Analog gain control */ #define IMX258_REG_ANALOG_GAIN … #define IMX258_ANA_GAIN_MIN … #define IMX258_ANA_GAIN_MAX … #define IMX258_ANA_GAIN_STEP … #define IMX258_ANA_GAIN_DEFAULT … /* Digital gain control */ #define IMX258_REG_GR_DIGITAL_GAIN … #define IMX258_REG_R_DIGITAL_GAIN … #define IMX258_REG_B_DIGITAL_GAIN … #define IMX258_REG_GB_DIGITAL_GAIN … #define IMX258_DGTL_GAIN_MIN … #define IMX258_DGTL_GAIN_MAX … #define IMX258_DGTL_GAIN_DEFAULT … #define IMX258_DGTL_GAIN_STEP … /* HDR control */ #define IMX258_REG_HDR … #define IMX258_HDR_ON … #define IMX258_REG_HDR_RATIO … #define IMX258_HDR_RATIO_MIN … #define IMX258_HDR_RATIO_MAX … #define IMX258_HDR_RATIO_STEP … #define IMX258_HDR_RATIO_DEFAULT … /* Test Pattern Control */ #define IMX258_REG_TEST_PATTERN … #define IMX258_CLK_BLANK_STOP … /* Orientation */ #define REG_MIRROR_FLIP_CONTROL … #define REG_CONFIG_MIRROR_HFLIP … #define REG_CONFIG_MIRROR_VFLIP … /* IMX258 native and active pixel array size. */ #define IMX258_NATIVE_WIDTH … #define IMX258_NATIVE_HEIGHT … #define IMX258_PIXEL_ARRAY_LEFT … #define IMX258_PIXEL_ARRAY_TOP … #define IMX258_PIXEL_ARRAY_WIDTH … #define IMX258_PIXEL_ARRAY_HEIGHT … /* regs */ #define IMX258_REG_PLL_MULT_DRIV … #define IMX258_REG_IVTPXCK_DIV … #define IMX258_REG_IVTSYCK_DIV … #define IMX258_REG_PREPLLCK_VT_DIV … #define IMX258_REG_IOPPXCK_DIV … #define IMX258_REG_IOPSYCK_DIV … #define IMX258_REG_PREPLLCK_OP_DIV … #define IMX258_REG_PHASE_PIX_OUTEN … #define IMX258_REG_PDPIX_DATA_RATE … #define IMX258_REG_SCALE_MODE … #define IMX258_REG_SCALE_MODE_EXT … #define IMX258_REG_AF_WINDOW_MODE … #define IMX258_REG_FRM_LENGTH_CTL … #define IMX258_REG_CSI_LANE_MODE … #define IMX258_REG_X_EVN_INC … #define IMX258_REG_X_ODD_INC … #define IMX258_REG_Y_EVN_INC … #define IMX258_REG_Y_ODD_INC … #define IMX258_REG_BINNING_MODE … #define IMX258_REG_BINNING_TYPE_V … #define IMX258_REG_FORCE_FD_SUM … #define IMX258_REG_DIG_CROP_X_OFFSET … #define IMX258_REG_DIG_CROP_Y_OFFSET … #define IMX258_REG_DIG_CROP_IMAGE_WIDTH … #define IMX258_REG_DIG_CROP_IMAGE_HEIGHT … #define IMX258_REG_SCALE_M … #define IMX258_REG_X_OUT_SIZE … #define IMX258_REG_Y_OUT_SIZE … #define IMX258_REG_X_ADD_STA … #define IMX258_REG_Y_ADD_STA … #define IMX258_REG_X_ADD_END … #define IMX258_REG_Y_ADD_END … #define IMX258_REG_EXCK_FREQ … #define IMX258_REG_CSI_DT_FMT … #define IMX258_REG_LINE_LENGTH_PCK … #define IMX258_REG_SCALE_M_EXT … #define IMX258_REG_FRM_LENGTH_LINES … #define IMX258_REG_FINE_INTEG_TIME … #define IMX258_REG_PLL_IVT_MPY … #define IMX258_REG_PLL_IOP_MPY … #define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_H … #define IMX258_REG_REQ_LINK_BIT_RATE_MBPS_L … struct imx258_reg_list { … }; struct imx258_link_cfg { … }; enum { … }; /* Link frequency config */ struct imx258_link_freq_config { … }; /* Mode : resolution and related config&values */ struct imx258_mode { … }; /* * 4208x3120 @ 30 fps needs 1267Mbps/lane, 4 lanes. * To avoid further computation of clock settings, adopt the same per * lane data rate when using 2 lanes, thus allowing a maximum of 15fps. */ static const struct cci_reg_sequence mipi_1267mbps_19_2mhz_2l[] = …; static const struct cci_reg_sequence mipi_1267mbps_19_2mhz_4l[] = …; static const struct cci_reg_sequence mipi_1272mbps_24mhz_2l[] = …; static const struct cci_reg_sequence mipi_1272mbps_24mhz_4l[] = …; static const struct cci_reg_sequence mipi_640mbps_19_2mhz_2l[] = …; static const struct cci_reg_sequence mipi_640mbps_19_2mhz_4l[] = …; static const struct cci_reg_sequence mipi_642mbps_24mhz_2l[] = …; static const struct cci_reg_sequence mipi_642mbps_24mhz_4l[] = …; static const struct cci_reg_sequence mode_common_regs[] = …; static const struct cci_reg_sequence mode_4208x3120_regs[] = …; static const struct cci_reg_sequence mode_2104_1560_regs[] = …; static const struct cci_reg_sequence mode_1048_780_regs[] = …; struct imx258_variant_cfg { … }; static const struct cci_reg_sequence imx258_cfg_regs[] = …; static const struct imx258_variant_cfg imx258_cfg = …; static const struct cci_reg_sequence imx258_pdaf_cfg_regs[] = …; static const struct imx258_variant_cfg imx258_pdaf_cfg = …; /* * The supported formats. * This table MUST contain 4 entries per format, to cover the various flip * combinations in the order * - no flip * - h flip * - v flip * - h&v flips */ static const u32 codes[] = …; static const char * const imx258_test_pattern_menu[] = …; /* regulator supplies */ static const char * const imx258_supply_name[] = …; #define IMX258_NUM_SUPPLIES … enum { … }; /* * Pixel rate does not necessarily relate to link frequency on this sensor as * there is a FIFO between the pixel array pipeline and the MIPI serializer. * The recommendation from Sony is that the pixel array is always run with a * line length of 5352 pixels, which means that there is a large amount of * blanking time for the 1048x780 mode. There is no need to replicate this * blanking on the CSI2 bus, and the configuration of register 0x0301 allows the * divider to be altered. * * The actual factor between link frequency and pixel rate is in the * imx258_link_cfg, so use this to convert between the two. * bits per pixel being 10, and D-PHY being DDR is assumed by this function, so * the value is only the combination of number of lanes and pixel clock divider. */ static u64 link_freq_to_pixel_rate(u64 f, const struct imx258_link_cfg *link_cfg) { … } /* Menu items for LINK_FREQ V4L2 control */ /* Configurations for supported link frequencies */ static const s64 link_freq_menu_items_19_2[] = …; static const s64 link_freq_menu_items_24[] = …; #define REGS(_list) … /* Link frequency configs */ static const struct imx258_link_freq_config link_freq_configs_19_2[] = …; static const struct imx258_link_freq_config link_freq_configs_24[] = …; /* Mode configs */ static const struct imx258_mode supported_modes[] = …; struct imx258 { … }; static inline struct imx258 *to_imx258(struct v4l2_subdev *_sd) { … } /* Get bayer order based on flip setting. */ static u32 imx258_get_format_code(const struct imx258 *imx258) { … } /* Open sub-device */ static int imx258_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { … } static int imx258_update_digital_gain(struct imx258 *imx258, u32 val) { … } static void imx258_adjust_exposure_range(struct imx258 *imx258) { … } static int imx258_set_ctrl(struct v4l2_ctrl *ctrl) { … } static const struct v4l2_ctrl_ops imx258_ctrl_ops = …; static int imx258_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int imx258_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { … } static void imx258_update_pad_format(struct imx258 *imx258, const struct imx258_mode *mode, struct v4l2_subdev_format *fmt) { … } static int __imx258_get_pad_format(struct imx258 *imx258, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int imx258_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int imx258_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static const struct v4l2_rect * __imx258_get_pad_crop(struct imx258 *imx258, struct v4l2_subdev_state *sd_state, unsigned int pad, enum v4l2_subdev_format_whence which) { … } static int imx258_get_selection(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_selection *sel) { … } /* Start streaming */ static int imx258_start_streaming(struct imx258 *imx258) { … } /* Stop streaming */ static int imx258_stop_streaming(struct imx258 *imx258) { … } static int imx258_power_on(struct device *dev) { … } static int imx258_power_off(struct device *dev) { … } static int imx258_set_stream(struct v4l2_subdev *sd, int enable) { … } /* Verify chip ID */ static int imx258_identify_module(struct imx258 *imx258) { … } static const struct v4l2_subdev_video_ops imx258_video_ops = …; static const struct v4l2_subdev_pad_ops imx258_pad_ops = …; static const struct v4l2_subdev_ops imx258_subdev_ops = …; static const struct v4l2_subdev_internal_ops imx258_internal_ops = …; /* Initialize control handlers */ static int imx258_init_controls(struct imx258 *imx258) { … } static void imx258_free_controls(struct imx258 *imx258) { … } static int imx258_get_regulators(struct imx258 *imx258, struct i2c_client *client) { … } static int imx258_probe(struct i2c_client *client) { … } static void imx258_remove(struct i2c_client *client) { … } static const struct dev_pm_ops imx258_pm_ops = …; #ifdef CONFIG_ACPI static const struct acpi_device_id imx258_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, imx258_acpi_ids); #endif static const struct of_device_id imx258_dt_ids[] = …; MODULE_DEVICE_TABLE(of, imx258_dt_ids); static struct i2c_driver imx258_i2c_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux