// SPDX-License-Identifier: GPL-2.0 // Copyright (c) 2022 Intel Corporation. #include <linux/unaligned.h> #include <linux/acpi.h> #include <linux/i2c.h> #include <linux/module.h> #include <linux/delay.h> #include <linux/pm_runtime.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #define OV08X40_REG_VALUE_08BIT … #define OV08X40_REG_VALUE_16BIT … #define OV08X40_REG_VALUE_24BIT … #define OV08X40_REG_MODE_SELECT … #define OV08X40_MODE_STANDBY … #define OV08X40_MODE_STREAMING … #define OV08X40_REG_AO_STANDBY … #define OV08X40_AO_STREAMING … #define OV08X40_REG_MS_SELECT … #define OV08X40_MS_STANDBY … #define OV08X40_MS_STREAMING … #define OV08X40_REG_SOFTWARE_RST … #define OV08X40_SOFTWARE_RST … /* Chip ID */ #define OV08X40_REG_CHIP_ID … #define OV08X40_CHIP_ID … /* V_TIMING internal */ #define OV08X40_REG_VTS … #define OV08X40_VTS_30FPS … #define OV08X40_VTS_BIN_30FPS … #define OV08X40_VTS_MAX … /* H TIMING internal */ #define OV08X40_REG_HTS … #define OV08X40_HTS_30FPS … /* Exposure control */ #define OV08X40_REG_EXPOSURE … #define OV08X40_EXPOSURE_MAX_MARGIN … #define OV08X40_EXPOSURE_BIN_MAX_MARGIN … #define OV08X40_EXPOSURE_MIN … #define OV08X40_EXPOSURE_STEP … #define OV08X40_EXPOSURE_DEFAULT … /* Short Exposure control */ #define OV08X40_REG_SHORT_EXPOSURE … /* Analog gain control */ #define OV08X40_REG_ANALOG_GAIN … #define OV08X40_ANA_GAIN_MIN … #define OV08X40_ANA_GAIN_MAX … #define OV08X40_ANA_GAIN_STEP … #define OV08X40_ANA_GAIN_DEFAULT … /* Digital gain control */ #define OV08X40_REG_DGTL_GAIN_H … #define OV08X40_REG_DGTL_GAIN_M … #define OV08X40_REG_DGTL_GAIN_L … #define OV08X40_DGTL_GAIN_MIN … #define OV08X40_DGTL_GAIN_MAX … #define OV08X40_DGTL_GAIN_DEFAULT … #define OV08X40_DGTL_GAIN_STEP … #define OV08X40_DGTL_GAIN_L_SHIFT … #define OV08X40_DGTL_GAIN_L_MASK … #define OV08X40_DGTL_GAIN_M_SHIFT … #define OV08X40_DGTL_GAIN_M_MASK … #define OV08X40_DGTL_GAIN_H_SHIFT … #define OV08X40_DGTL_GAIN_H_MASK … /* Test Pattern Control */ #define OV08X40_REG_TEST_PATTERN … #define OV08X40_REG_ISP … #define OV08X40_REG_SHORT_TEST_PATTERN … #define OV08X40_TEST_PATTERN_ENABLE … #define OV08X40_TEST_PATTERN_MASK … #define OV08X40_TEST_PATTERN_BAR_SHIFT … /* Flip Control */ #define OV08X40_REG_VFLIP … #define OV08X40_REG_MIRROR … /* Horizontal Window Offset */ #define OV08X40_REG_H_WIN_OFFSET … /* Vertical Window Offset */ #define OV08X40_REG_V_WIN_OFFSET … /* Burst Register */ #define OV08X40_REG_XTALK_FIRST_A … #define OV08X40_REG_XTALK_LAST_A … #define OV08X40_REG_XTALK_FIRST_B … #define OV08X40_REG_XTALK_LAST_B … enum { … }; struct ov08x40_reg { … }; struct ov08x40_reg_list { … }; /* Link frequency config */ struct ov08x40_link_freq_config { … }; /* Mode : resolution and related config&values */ struct ov08x40_mode { … }; static const struct ov08x40_reg mipi_data_rate_800mbps[] = …; static const struct ov08x40_reg mode_3856x2416_regs[] = …; static const struct ov08x40_reg mode_1928x1208_regs[] = …; static const char * const ov08x40_test_pattern_menu[] = …; /* Configurations for supported link frequencies */ #define OV08X40_LINK_FREQ_400MHZ … #define OV08X40_SCLK_96MHZ … #define OV08X40_EXT_CLK … #define OV08X40_DATA_LANES … /* * pixel_rate = link_freq * data-rate * nr_of_lanes / bits_per_sample * data rate => double data rate; number of lanes => 4; bits per pixel => 10 */ static u64 link_freq_to_pixel_rate(u64 f) { … } /* Menu items for LINK_FREQ V4L2 control */ static const s64 link_freq_menu_items[] = …; /* Link frequency configs */ static const struct ov08x40_link_freq_config link_freq_configs[] = …; /* Mode configs */ static const struct ov08x40_mode supported_modes[] = …; struct ov08x40 { … }; #define to_ov08x40(_sd) … /* Read registers up to 4 at a time */ static int ov08x40_read_reg(struct ov08x40 *ov08x, u16 reg, u32 len, u32 *val) { … } static int ov08x40_burst_fill_regs(struct ov08x40 *ov08x, u16 first_reg, u16 last_reg, u8 val) { … } /* Write registers up to 4 at a time */ static int ov08x40_write_reg(struct ov08x40 *ov08x, u16 reg, u32 len, u32 __val) { … } /* Write a list of registers */ static int ov08x40_write_regs(struct ov08x40 *ov08x, const struct ov08x40_reg *regs, u32 len) { … } static int ov08x40_write_reg_list(struct ov08x40 *ov08x, const struct ov08x40_reg_list *r_list) { … } static int ov08x40_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) { … } static int ov08x40_update_digital_gain(struct ov08x40 *ov08x, u32 d_gain) { … } static int ov08x40_enable_test_pattern(struct ov08x40 *ov08x, u32 pattern) { … } static int ov08x40_set_ctrl_hflip(struct ov08x40 *ov08x, u32 ctrl_val) { … } static int ov08x40_set_ctrl_vflip(struct ov08x40 *ov08x, u32 ctrl_val) { … } static int ov08x40_set_ctrl(struct v4l2_ctrl *ctrl) { … } static const struct v4l2_ctrl_ops ov08x40_ctrl_ops = …; static int ov08x40_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int ov08x40_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { … } static void ov08x40_update_pad_format(const struct ov08x40_mode *mode, struct v4l2_subdev_format *fmt) { … } static int ov08x40_do_get_pad_format(struct ov08x40 *ov08x, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov08x40_get_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov08x40_set_pad_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *fmt) { … } static int ov08x40_start_streaming(struct ov08x40 *ov08x) { … } /* Stop streaming */ static int ov08x40_stop_streaming(struct ov08x40 *ov08x) { … } static int ov08x40_set_stream(struct v4l2_subdev *sd, int enable) { … } /* Verify chip ID */ static int ov08x40_identify_module(struct ov08x40 *ov08x) { … } static const struct v4l2_subdev_video_ops ov08x40_video_ops = …; static const struct v4l2_subdev_pad_ops ov08x40_pad_ops = …; static const struct v4l2_subdev_ops ov08x40_subdev_ops = …; static const struct media_entity_operations ov08x40_subdev_entity_ops = …; static const struct v4l2_subdev_internal_ops ov08x40_internal_ops = …; static int ov08x40_init_controls(struct ov08x40 *ov08x) { … } static void ov08x40_free_controls(struct ov08x40 *ov08x) { … } static int ov08x40_check_hwcfg(struct device *dev) { … } static int ov08x40_probe(struct i2c_client *client) { … } static void ov08x40_remove(struct i2c_client *client) { … } #ifdef CONFIG_ACPI static const struct acpi_device_id ov08x40_acpi_ids[] = …; MODULE_DEVICE_TABLE(acpi, ov08x40_acpi_ids); #endif static struct i2c_driver ov08x40_i2c_driver = …; module_i2c_driver(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
Codebase Browser
linux