// SPDX-License-Identifier: GPL-2.0-only /* * TC358746 - Parallel <-> CSI-2 Bridge * * Copyright 2022 Marco Felsch <[email protected]> * * Notes: * - Currently only 'Parallel-in -> CSI-out' mode is supported! */ #include <linux/bitfield.h> #include <linux/clk.h> #include <linux/clk-provider.h> #include <linux/delay.h> #include <linux/i2c.h> #include <linux/interrupt.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/phy/phy-mipi-dphy.h> #include <linux/property.h> #include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/units.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mc.h> /* 16-bit registers */ #define CHIPID_REG … #define CHIPID … #define SYSCTL_REG … #define SRESET … #define CONFCTL_REG … #define PDATAF_MASK … #define PDATAF_MODE0 … #define PDATAF_MODE1 … #define PDATAF_MODE2 … #define PDATAF(val) … #define PPEN … #define DATALANE_MASK … #define FIFOCTL_REG … #define DATAFMT_REG … #define PDFMT(val) … #define MCLKCTL_REG … #define MCLK_HIGH_MASK … #define MCLK_LOW_MASK … #define MCLK_HIGH(val) … #define MCLK_LOW(val) … #define PLLCTL0_REG … #define PLL_PRD_MASK … #define PLL_PRD(val) … #define PLL_FBD_MASK … #define PLL_FBD(val) … #define PLLCTL1_REG … #define PLL_FRS_MASK … #define PLL_FRS(val) … #define CKEN … #define RESETB … #define PLL_EN … #define CLKCTL_REG … #define MCLKDIV_MASK … #define MCLKDIV(val) … #define MCLKDIV_8 … #define MCLKDIV_4 … #define MCLKDIV_2 … #define WORDCNT_REG … #define PP_MISC_REG … #define FRMSTOP … #define RSTPTR … /* 32-bit registers */ #define CLW_DPHYCONTTX_REG … #define CLW_CNTRL_REG … #define D0W_CNTRL_REG … #define LANEDISABLE … #define STARTCNTRL_REG … #define START … #define LINEINITCNT_REG … #define LPTXTIMECNT_REG … #define TCLK_HEADERCNT_REG … #define TCLK_ZEROCNT(val) … #define TCLK_PREPARECNT(val) … #define TCLK_TRAILCNT_REG … #define THS_HEADERCNT_REG … #define THS_ZEROCNT(val) … #define THS_PREPARECNT(val) … #define TWAKEUP_REG … #define TCLK_POSTCNT_REG … #define THS_TRAILCNT_REG … #define HSTXVREGEN_REG … #define TXOPTIONCNTRL_REG … #define CSI_CONTROL_REG … #define CSI_MODE … #define TXHSMD … #define NOL(val) … #define CSI_CONFW_REG … #define MODE(val) … #define MODE_SET … #define ADDRESS(val) … #define CSI_CONTROL_ADDRESS … #define DATA(val) … #define CSI_START_REG … #define STRT … static const struct v4l2_mbus_framefmt tc358746_def_fmt = …; static const char * const tc358746_supplies[] = …; enum { … }; struct tc358746 { … }; static inline struct tc358746 *to_tc358746(struct v4l2_subdev *sd) { … } static inline struct tc358746 *clk_hw_to_tc358746(struct clk_hw *hw) { … } struct tc358746_format { … }; enum { … }; /* Check tc358746_src_mbus_code() if you add new formats */ static const struct tc358746_format tc358746_formats[] = …; /* Get n-th format for pad */ static const struct tc358746_format * tc358746_get_format_by_idx(unsigned int pad, unsigned int index) { … } static const struct tc358746_format * tc358746_get_format_by_code(unsigned int pad, u32 code) { … } static u32 tc358746_src_mbus_code(u32 code) { … } static bool tc358746_valid_reg(struct device *dev, unsigned int reg) { … } static const struct regmap_config tc358746_regmap_config = …; static int tc358746_write(struct tc358746 *tc358746, u32 reg, u32 val) { … } static int tc358746_read(struct tc358746 *tc358746, u32 reg, u32 *val) { … } static int tc358746_update_bits(struct tc358746 *tc358746, u32 reg, u32 mask, u32 val) { … } static int tc358746_set_bits(struct tc358746 *tc358746, u32 reg, u32 bits) { … } static int tc358746_clear_bits(struct tc358746 *tc358746, u32 reg, u32 bits) { … } static int tc358746_sw_reset(struct tc358746 *tc358746) { … } static int tc358746_apply_pll_config(struct tc358746 *tc358746) { … } static int tc358746_apply_misc_config(struct tc358746 *tc358746) { … } /* Use MHz as base so the div needs no u64 */ static u32 tc358746_cfg_to_cnt(unsigned int cfg_val, unsigned int clk_mhz, unsigned int time_base) { … } static u32 tc358746_ps_to_cnt(unsigned int cfg_val, unsigned int clk_mhz) { … } static u32 tc358746_us_to_cnt(unsigned int cfg_val, unsigned int clk_mhz) { … } static int tc358746_apply_dphy_config(struct tc358746 *tc358746) { … } #define MAX_DATA_LANES … static int tc358746_enable_csi_lanes(struct tc358746 *tc358746, int enable) { … } static int tc358746_enable_csi_module(struct tc358746 *tc358746, int enable) { … } static int tc358746_enable_parallel_port(struct tc358746 *tc358746, int enable) { … } static inline struct v4l2_subdev *tc358746_get_remote_sd(struct media_pad *pad) { … } static int tc358746_s_stream(struct v4l2_subdev *sd, int enable) { … } static int tc358746_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *state) { … } static int tc358746_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int tc358746_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_format *format) { … } static unsigned long tc358746_find_pll_settings(struct tc358746 *tc358746, unsigned long refclk, unsigned long fout) { … } #define TC358746_PRECISION … static int tc358746_link_validate(struct v4l2_subdev *sd, struct media_link *link, struct v4l2_subdev_format *source_fmt, struct v4l2_subdev_format *sink_fmt) { … } static int tc358746_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad, struct v4l2_mbus_config *config) { … } static int __maybe_unused tc358746_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg) { … } static int __maybe_unused tc358746_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg) { … } static const struct v4l2_subdev_core_ops tc358746_core_ops = …; static const struct v4l2_subdev_video_ops tc358746_video_ops = …; static const struct v4l2_subdev_pad_ops tc358746_pad_ops = …; static const struct v4l2_subdev_ops tc358746_ops = …; static const struct v4l2_subdev_internal_ops tc358746_internal_ops = …; static const struct media_entity_operations tc358746_entity_ops = …; static int tc358746_mclk_enable(struct clk_hw *hw) { … } static void tc358746_mclk_disable(struct clk_hw *hw) { … } static long tc358746_find_mclk_settings(struct tc358746 *tc358746, unsigned long mclk_rate) { … } static unsigned long tc358746_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { … } static long tc358746_mclk_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *parent_rate) { … } static int tc358746_mclk_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long parent_rate) { … } static const struct clk_ops tc358746_mclk_ops = …; static int tc358746_setup_mclk_provider(struct tc358746 *tc358746) { … } static int tc358746_init_subdev(struct tc358746 *tc358746, struct i2c_client *client) { … } static int tc358746_init_output_port(struct tc358746 *tc358746, unsigned long refclk) { … } static int tc358746_init_hw(struct tc358746 *tc358746) { … } static int tc358746_init_controls(struct tc358746 *tc358746) { … } static int tc358746_notify_bound(struct v4l2_async_notifier *notifier, struct v4l2_subdev *sd, struct v4l2_async_connection *asd) { … } static const struct v4l2_async_notifier_operations tc358746_notify_ops = …; static int tc358746_async_register(struct tc358746 *tc358746) { … } static int tc358746_probe(struct i2c_client *client) { … } static void tc358746_remove(struct i2c_client *client) { … } /* * This function has been created just to avoid a smatch warning, * please do not merge it into tc358746_suspend until you have * confirmed that it does not introduce a new warning. */ static void tc358746_clk_enable(struct tc358746 *tc358746) { … } static int tc358746_suspend(struct device *dev) { … } static int tc358746_resume(struct device *dev) { … } static DEFINE_RUNTIME_DEV_PM_OPS(tc358746_pm_ops, tc358746_suspend, tc358746_resume, NULL); static const struct of_device_id __maybe_unused tc358746_of_match[] = …; MODULE_DEVICE_TABLE(of, tc358746_of_match); static struct i2c_driver tc358746_driver = …; module_i2c_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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