/* SPDX-License-Identifier: GPL-2.0-only */ /* * drivers/media/i2c/tvp514x_regs.h * * Copyright (C) 2008 Texas Instruments Inc * Author: Vaibhav Hiremath <[email protected]> * * Contributors: * Sivaraj R <[email protected]> * Brijesh R Jadav <[email protected]> * Hardik Shah <[email protected]> * Manjunath Hadli <[email protected]> * Karicheri Muralidharan <[email protected]> */ #ifndef _TVP514X_REGS_H #define _TVP514X_REGS_H /* * TVP5146/47 registers */ #define REG_INPUT_SEL … #define REG_AFE_GAIN_CTRL … #define REG_VIDEO_STD … #define REG_OPERATION_MODE … #define REG_AUTOSWITCH_MASK … #define REG_COLOR_KILLER … #define REG_LUMA_CONTROL1 … #define REG_LUMA_CONTROL2 … #define REG_LUMA_CONTROL3 … #define REG_BRIGHTNESS … #define REG_CONTRAST … #define REG_SATURATION … #define REG_HUE … #define REG_CHROMA_CONTROL1 … #define REG_CHROMA_CONTROL2 … /* 0x0F Reserved */ #define REG_COMP_PR_SATURATION … #define REG_COMP_Y_CONTRAST … #define REG_COMP_PB_SATURATION … /* 0x13 Reserved */ #define REG_COMP_Y_BRIGHTNESS … /* 0x15 Reserved */ #define REG_AVID_START_PIXEL_LSB … #define REG_AVID_START_PIXEL_MSB … #define REG_AVID_STOP_PIXEL_LSB … #define REG_AVID_STOP_PIXEL_MSB … #define REG_HSYNC_START_PIXEL_LSB … #define REG_HSYNC_START_PIXEL_MSB … #define REG_HSYNC_STOP_PIXEL_LSB … #define REG_HSYNC_STOP_PIXEL_MSB … #define REG_VSYNC_START_LINE_LSB … #define REG_VSYNC_START_LINE_MSB … #define REG_VSYNC_STOP_LINE_LSB … #define REG_VSYNC_STOP_LINE_MSB … #define REG_VBLK_START_LINE_LSB … #define REG_VBLK_START_LINE_MSB … #define REG_VBLK_STOP_LINE_LSB … #define REG_VBLK_STOP_LINE_MSB … /* 0x26 - 0x27 Reserved */ #define REG_FAST_SWTICH_CONTROL … /* 0x29 Reserved */ #define REG_FAST_SWTICH_SCART_DELAY … /* 0x2B Reserved */ #define REG_SCART_DELAY … #define REG_CTI_DELAY … #define REG_CTI_CONTROL … /* 0x2F - 0x31 Reserved */ #define REG_SYNC_CONTROL … #define REG_OUTPUT_FORMATTER1 … #define REG_OUTPUT_FORMATTER2 … #define REG_OUTPUT_FORMATTER3 … #define REG_OUTPUT_FORMATTER4 … #define REG_OUTPUT_FORMATTER5 … #define REG_OUTPUT_FORMATTER6 … #define REG_CLEAR_LOST_LOCK … #define REG_STATUS1 … #define REG_STATUS2 … #define REG_AGC_GAIN_STATUS_LSB … #define REG_AGC_GAIN_STATUS_MSB … /* 0x3E Reserved */ #define REG_VIDEO_STD_STATUS … #define REG_GPIO_INPUT1 … #define REG_GPIO_INPUT2 … /* 0x42 - 0x45 Reserved */ #define REG_AFE_COARSE_GAIN_CH1 … #define REG_AFE_COARSE_GAIN_CH2 … #define REG_AFE_COARSE_GAIN_CH3 … #define REG_AFE_COARSE_GAIN_CH4 … #define REG_AFE_FINE_GAIN_PB_B_LSB … #define REG_AFE_FINE_GAIN_PB_B_MSB … #define REG_AFE_FINE_GAIN_Y_G_CHROMA_LSB … #define REG_AFE_FINE_GAIN_Y_G_CHROMA_MSB … #define REG_AFE_FINE_GAIN_PR_R_LSB … #define REG_AFE_FINE_GAIN_PR_R_MSB … #define REG_AFE_FINE_GAIN_CVBS_LUMA_LSB … #define REG_AFE_FINE_GAIN_CVBS_LUMA_MSB … /* 0x52 - 0x68 Reserved */ #define REG_FBIT_VBIT_CONTROL1 … /* 0x6A - 0x6B Reserved */ #define REG_BACKEND_AGC_CONTROL … /* 0x6D - 0x6E Reserved */ #define REG_AGC_DECREMENT_SPEED_CONTROL … #define REG_ROM_VERSION … /* 0x71 - 0x73 Reserved */ #define REG_AGC_WHITE_PEAK_PROCESSING … #define REG_FBIT_VBIT_CONTROL2 … #define REG_VCR_TRICK_MODE_CONTROL … #define REG_HORIZONTAL_SHAKE_INCREMENT … #define REG_AGC_INCREMENT_SPEED … #define REG_AGC_INCREMENT_DELAY … /* 0x7A - 0x7F Reserved */ #define REG_CHIP_ID_MSB … #define REG_CHIP_ID_LSB … /* 0x82 Reserved */ #define REG_CPLL_SPEED_CONTROL … /* 0x84 - 0x96 Reserved */ #define REG_STATUS_REQUEST … /* 0x98 - 0x99 Reserved */ #define REG_VERTICAL_LINE_COUNT_LSB … #define REG_VERTICAL_LINE_COUNT_MSB … /* 0x9C - 0x9D Reserved */ #define REG_AGC_DECREMENT_DELAY … /* 0x9F - 0xB0 Reserved */ #define REG_VDP_TTX_FILTER_1_MASK1 … #define REG_VDP_TTX_FILTER_1_MASK2 … #define REG_VDP_TTX_FILTER_1_MASK3 … #define REG_VDP_TTX_FILTER_1_MASK4 … #define REG_VDP_TTX_FILTER_1_MASK5 … #define REG_VDP_TTX_FILTER_2_MASK1 … #define REG_VDP_TTX_FILTER_2_MASK2 … #define REG_VDP_TTX_FILTER_2_MASK3 … #define REG_VDP_TTX_FILTER_2_MASK4 … #define REG_VDP_TTX_FILTER_2_MASK5 … #define REG_VDP_TTX_FILTER_CONTROL … #define REG_VDP_FIFO_WORD_COUNT … #define REG_VDP_FIFO_INTERRUPT_THRLD … /* 0xBE Reserved */ #define REG_VDP_FIFO_RESET … #define REG_VDP_FIFO_OUTPUT_CONTROL … #define REG_VDP_LINE_NUMBER_INTERRUPT … #define REG_VDP_PIXEL_ALIGNMENT_LSB … #define REG_VDP_PIXEL_ALIGNMENT_MSB … /* 0xC4 - 0xD5 Reserved */ #define REG_VDP_LINE_START … #define REG_VDP_LINE_STOP … #define REG_VDP_GLOBAL_LINE_MODE … #define REG_VDP_FULL_FIELD_ENABLE … #define REG_VDP_FULL_FIELD_MODE … /* 0xDB - 0xDF Reserved */ #define REG_VBUS_DATA_ACCESS_NO_VBUS_ADDR_INCR … #define REG_VBUS_DATA_ACCESS_VBUS_ADDR_INCR … #define REG_FIFO_READ_DATA … /* 0xE3 - 0xE7 Reserved */ #define REG_VBUS_ADDRESS_ACCESS1 … #define REG_VBUS_ADDRESS_ACCESS2 … #define REG_VBUS_ADDRESS_ACCESS3 … /* 0xEB - 0xEF Reserved */ #define REG_INTERRUPT_RAW_STATUS0 … #define REG_INTERRUPT_RAW_STATUS1 … #define REG_INTERRUPT_STATUS0 … #define REG_INTERRUPT_STATUS1 … #define REG_INTERRUPT_MASK0 … #define REG_INTERRUPT_MASK1 … #define REG_INTERRUPT_CLEAR0 … #define REG_INTERRUPT_CLEAR1 … /* 0xF8 - 0xFF Reserved */ /* * Mask and bit definitions of TVP5146/47 registers */ /* The ID values we are looking for */ #define TVP514X_CHIP_ID_MSB … #define TVP5146_CHIP_ID_LSB … #define TVP5147_CHIP_ID_LSB … #define VIDEO_STD_MASK … #define VIDEO_STD_AUTO_SWITCH_BIT … #define VIDEO_STD_NTSC_MJ_BIT … #define VIDEO_STD_PAL_BDGHIN_BIT … #define VIDEO_STD_PAL_M_BIT … #define VIDEO_STD_PAL_COMBINATION_N_BIT … #define VIDEO_STD_NTSC_4_43_BIT … #define VIDEO_STD_SECAM_BIT … #define VIDEO_STD_PAL_60_BIT … /* * Status bit */ #define STATUS_TV_VCR_BIT … #define STATUS_HORZ_SYNC_LOCK_BIT … #define STATUS_VIRT_SYNC_LOCK_BIT … #define STATUS_CLR_SUBCAR_LOCK_BIT … #define STATUS_LOST_LOCK_DETECT_BIT … #define STATUS_FEILD_RATE_BIT … #define STATUS_LINE_ALTERNATING_BIT … #define STATUS_PEAK_WHITE_DETECT_BIT … /* Tokens for register write */ #define TOK_WRITE … #define TOK_TERM … #define TOK_DELAY … #define TOK_SKIP … /** * struct tvp514x_reg - Structure for TVP5146/47 register initialization values * @token: Token: TOK_WRITE, TOK_TERM etc.. * @reg: Register offset * @val: Register Value for TOK_WRITE or delay in ms for TOK_DELAY */ struct tvp514x_reg { … }; #endif /* ifndef _TVP514X_REGS_H */
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