/* MaxLinear MXL5005S VSB/QAM/DVBT tuner driver Copyright (C) 2008 MaxLinear Copyright (C) 2006 Steven Toth <[email protected]> Functions: mxl5005s_reset() mxl5005s_writereg() mxl5005s_writeregs() mxl5005s_init() mxl5005s_reconfigure() mxl5005s_AssignTunerMode() mxl5005s_set_params() mxl5005s_get_frequency() mxl5005s_get_bandwidth() mxl5005s_release() mxl5005s_attach() Copyright (C) 2008 Realtek Copyright (C) 2008 Jan Hoogenraad Functions: mxl5005s_SetRfFreqHz() This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ /* History of this driver (Steven Toth): I was given a public release of a linux driver that included support for the MaxLinear MXL5005S silicon tuner. Analysis of the tuner driver showed clearly three things. 1. The tuner driver didn't support the LinuxTV tuner API so the code Realtek added had to be removed. 2. A significant amount of the driver is reference driver code from MaxLinear, I felt it was important to identify and preserve this. 3. New code has to be added to interface correctly with the LinuxTV API, as a regular kernel module. Other than the reference driver enum's, I've clearly marked sections of the code and retained the copyright of the respective owners. */ #include <linux/kernel.h> #include <linux/init.h> #include <linux/module.h> #include <linux/string.h> #include <linux/slab.h> #include <linux/delay.h> #include <media/dvb_frontend.h> #include "mxl5005s.h" static int debug; #define dprintk(level, arg...) … #define TUNER_REGS_NUM … #define INITCTRL_NUM … #ifdef _MXL_PRODUCTION #define CHCTRL_NUM … #else #define CHCTRL_NUM … #endif #define MXLCTRL_NUM … #define MASTER_CONTROL_ADDR … /* Enumeration of Master Control Register State */ enum master_control_state { … }; /* Enumeration of MXL5005 Tuner Modulation Type */ enum { … }; /* MXL5005 Tuner Register Struct */ struct TunerReg { … }; enum { … }; /* * The following context is source code provided by MaxLinear. * MaxLinear source code - Common_MXL.h (?) */ /* Constants */ #define MXL5005S_REG_WRITING_TABLE_LEN_MAX … #define MXL5005S_LATCH_BYTE … /* Register address, MSB, and LSB */ #define MXL5005S_BB_IQSWAP_ADDR … #define MXL5005S_BB_IQSWAP_MSB … #define MXL5005S_BB_IQSWAP_LSB … #define MXL5005S_BB_DLPF_BANDSEL_ADDR … #define MXL5005S_BB_DLPF_BANDSEL_MSB … #define MXL5005S_BB_DLPF_BANDSEL_LSB … /* Standard modes */ enum { … }; #define MXL5005S_STANDARD_MODE_NUM … /* Bandwidth modes */ enum { … }; #define MXL5005S_BANDWIDTH_MODE_NUM … /* MXL5005 Tuner Control Struct */ struct TunerControl { … }; /* MXL5005 Tuner Struct */ struct mxl5005s_state { … }; static u16 MXL_GetMasterControl(u8 *MasterReg, int state); static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value); static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value); static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal); static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static u32 MXL_Ceiling(u32 value, u32 resolution); static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal); static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup); static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val); static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq); static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe); static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe); static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count); static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len); static u16 MXL_IFSynthInit(struct dvb_frontend *fe); static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth); /* ---------------------------------------------------------------- * Begin: Custom code salvaged from the Realtek driver. * Copyright (C) 2008 Realtek * Copyright (C) 2008 Jan Hoogenraad * This code is placed under the terms of the GNU General Public License * * Released by Realtek under GPLv2. * Thanks to Realtek for a lot of support we received ! * * Revision: 080314 - original version */ static int mxl5005s_SetRfFreqHz(struct dvb_frontend *fe, unsigned long RfFreqHz) { … } /* End: Custom code taken from the Realtek driver */ /* ---------------------------------------------------------------- * Begin: Reference driver code found in the Realtek driver. * Copyright (C) 2008 MaxLinear */ static u16 MXL5005_RegisterInit(struct dvb_frontend *fe) { … } static u16 MXL5005_ControlInit(struct dvb_frontend *fe) { … } static void InitTunerControls(struct dvb_frontend *fe) { … } static u16 MXL5005_TunerConfig(struct dvb_frontend *fe, u8 Mode, /* 0: Analog Mode ; 1: Digital Mode */ u8 IF_mode, /* for Analog Mode, 0: zero IF; 1: low IF */ u32 Bandwidth, /* filter channel bandwidth (6, 7, 8) */ u32 IF_out, /* Desired IF Out Frequency */ u32 Fxtal, /* XTAL Frequency */ u8 AGC_Mode, /* AGC Mode - Dual AGC: 0, Single AGC: 1 */ u16 TOP, /* 0: Dual AGC; Value: take over point */ u16 IF_OUT_LOAD, /* IF Out Load Resistor (200 / 300 Ohms) */ u8 CLOCK_OUT, /* 0: turn off clk out; 1: turn on clock out */ u8 DIV_OUT, /* 0: Div-1; 1: Div-4 */ u8 CAPSELECT, /* 0: disable On-Chip pulling cap; 1: enable */ u8 EN_RSSI, /* 0: disable RSSI; 1: enable RSSI */ /* Modulation Type; */ /* 0 - Default; 1 - DVB-T; 2 - ATSC; 3 - QAM; 4 - Analog Cable */ u8 Mod_Type, /* Tracking Filter */ /* 0 - Default; 1 - Off; 2 - Type C; 3 - Type C-H */ u8 TF_Type ) { … } static void MXL_SynthIFLO_Calc(struct dvb_frontend *fe) { … } static void MXL_SynthRFTGLO_Calc(struct dvb_frontend *fe) { … } static u16 MXL_OverwriteICDefault(struct dvb_frontend *fe) { … } static u16 MXL_BlockInit(struct dvb_frontend *fe) { … } static u16 MXL_IFSynthInit(struct dvb_frontend *fe) { … } static u16 MXL_TuneRF(struct dvb_frontend *fe, u32 RF_Freq) { … } static u16 MXL_SetGPIO(struct dvb_frontend *fe, u8 GPIO_Num, u8 GPIO_Val) { … } static u16 MXL_ControlWrite(struct dvb_frontend *fe, u16 ControlNum, u32 value) { … } static u16 MXL_ControlWrite_Group(struct dvb_frontend *fe, u16 controlNum, u32 value, u16 controlGroup) { … } static u16 MXL_RegRead(struct dvb_frontend *fe, u8 RegNum, u8 *RegVal) { … } static u16 MXL_ControlRead(struct dvb_frontend *fe, u16 controlNum, u32 *value) { … } static void MXL_RegWriteBit(struct dvb_frontend *fe, u8 address, u8 bit, u8 bitVal) { … } static u32 MXL_Ceiling(u32 value, u32 resolution) { … } /* Retrieve the Initialization Registers */ static u16 MXL_GetInitRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { … } static u16 MXL_GetCHRegister(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { … } static u16 MXL_GetCHRegister_ZeroIF(struct dvb_frontend *fe, u8 *RegNum, u8 *RegVal, int *count) { … } static u16 MXL_GetMasterControl(u8 *MasterReg, int state) { … } #ifdef _MXL_PRODUCTION static u16 MXL_VCORange_Test(struct dvb_frontend *fe, int VCO_Range) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0 ; if (VCO_Range == 1) { status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); if (state->Mode == 0 && state->IF_Mode == 1) { /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 180224); } if (state->Mode == 0 && state->IF_Mode == 0) { /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 222822); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 56); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 229376); } } if (VCO_Range == 2) { status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); if (state->Mode == 0 && state->IF_Mode == 1) { /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 0 && state->IF_Mode == 0) { /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 1); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 41); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 16384); } } if (VCO_Range == 3) { status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); if (state->Mode == 0 && state->IF_Mode == 1) { /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); } if (state->Mode == 0 && state->IF_Mode == 0) { /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 44); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 173670); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 8); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 42); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 245760); } } if (VCO_Range == 4) { status += MXL_ControlWrite(fe, RFSYN_EN_DIV, 1); status += MXL_ControlWrite(fe, RFSYN_EN_OUTMUX, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_DIVM, 0); status += MXL_ControlWrite(fe, RFSYN_DIVM, 1); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_OUT, 1); status += MXL_ControlWrite(fe, RFSYN_RF_DIV_BIAS, 1); status += MXL_ControlWrite(fe, DN_SEL_FREQ, 0); status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); if (state->Mode == 0 && state->IF_Mode == 1) { /* Analog Low IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 0 && state->IF_Mode == 0) { /* Analog Zero IF Mode */ status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 206438); } if (state->Mode == 1) /* Digital Mode */ { status += MXL_ControlWrite(fe, RFSYN_SEL_VCO_HI, 0); status += MXL_ControlWrite(fe, RFSYN_VCO_BIAS, 40); status += MXL_ControlWrite(fe, CHCAL_INT_MOD_RF, 27); status += MXL_ControlWrite(fe, CHCAL_FRAC_MOD_RF, 212992); } } return status; } static u16 MXL_Hystersis_Test(struct dvb_frontend *fe, int Hystersis) { struct mxl5005s_state *state = fe->tuner_priv; u16 status = 0; if (Hystersis == 1) status += MXL_ControlWrite(fe, DN_BYPASS_AGC_I2C, 1); return status; } #endif /* End: Reference driver code found in the Realtek driver that * is copyright MaxLinear */ /* ---------------------------------------------------------------- * Begin: Everything after here is new code to adapt the * proprietary Realtek driver into a Linux API tuner. * Copyright (C) 2008 Steven Toth <[email protected]> */ static int mxl5005s_reset(struct dvb_frontend *fe) { … } /* Write a single byte to a single reg, latch the value if required by * following the transaction with the latch byte. */ static int mxl5005s_writereg(struct dvb_frontend *fe, u8 reg, u8 val, int latch) { … } static int mxl5005s_writeregs(struct dvb_frontend *fe, u8 *addrtable, u8 *datatable, u8 len) { … } static int mxl5005s_init(struct dvb_frontend *fe) { … } static int mxl5005s_reconfigure(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { … } static int mxl5005s_AssignTunerMode(struct dvb_frontend *fe, u32 mod_type, u32 bandwidth) { … } static int mxl5005s_set_params(struct dvb_frontend *fe) { … } static int mxl5005s_get_frequency(struct dvb_frontend *fe, u32 *frequency) { … } static int mxl5005s_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth) { … } static int mxl5005s_get_if_frequency(struct dvb_frontend *fe, u32 *frequency) { … } static void mxl5005s_release(struct dvb_frontend *fe) { … } static const struct dvb_tuner_ops mxl5005s_tuner_ops = …; struct dvb_frontend *mxl5005s_attach(struct dvb_frontend *fe, struct i2c_adapter *i2c, struct mxl5005s_config *config) { … } EXPORT_SYMBOL_GPL(…); MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …;
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