/* SPDX-License-Identifier: GPL-2.0 */ #define AUD_COMM_EXEC__A … #define AUD_COMM_EXEC_STOP … #define FEC_COMM_EXEC__A … #define FEC_COMM_EXEC_STOP … #define FEC_COMM_EXEC_ACTIVE … #define FEC_DI_COMM_EXEC__A … #define FEC_DI_COMM_EXEC_STOP … #define FEC_DI_INPUT_CTL__A … #define FEC_RS_COMM_EXEC__A … #define FEC_RS_COMM_EXEC_STOP … #define FEC_RS_MEASUREMENT_PERIOD__A … #define FEC_RS_MEASUREMENT_PRESCALE__A … #define FEC_RS_NR_BIT_ERRORS__A … #define FEC_OC_MODE__A … #define FEC_OC_MODE_PARITY__M … #define FEC_OC_DTO_MODE__A … #define FEC_OC_DTO_MODE_DYNAMIC__M … #define FEC_OC_DTO_MODE_OFFSET_ENABLE__M … #define FEC_OC_DTO_PERIOD__A … #define FEC_OC_DTO_BURST_LEN__A … #define FEC_OC_FCT_MODE__A … #define FEC_OC_FCT_MODE__PRE … #define FEC_OC_FCT_MODE_RAT_ENA__M … #define FEC_OC_FCT_MODE_VIRT_ENA__M … #define FEC_OC_TMD_MODE__A … #define FEC_OC_TMD_COUNT__A … #define FEC_OC_TMD_HI_MARGIN__A … #define FEC_OC_TMD_LO_MARGIN__A … #define FEC_OC_TMD_INT_UPD_RATE__A … #define FEC_OC_AVR_PARM_A__A … #define FEC_OC_AVR_PARM_B__A … #define FEC_OC_RCN_GAIN__A … #define FEC_OC_RCN_CTL_RATE_LO__A … #define FEC_OC_RCN_CTL_STEP_LO__A … #define FEC_OC_RCN_CTL_STEP_HI__A … #define FEC_OC_SNC_MODE__A … #define FEC_OC_SNC_MODE_SHUTDOWN__M … #define FEC_OC_SNC_LWM__A … #define FEC_OC_SNC_HWM__A … #define FEC_OC_SNC_UNLOCK__A … #define FEC_OC_SNC_FAIL_PERIOD__A … #define FEC_OC_IPR_MODE__A … #define FEC_OC_IPR_MODE_SERIAL__M … #define FEC_OC_IPR_MODE_MCLK_DIS_DAT_ABS__M … #define FEC_OC_IPR_MODE_MVAL_DIS_PAR__M … #define FEC_OC_IPR_INVERT__A … #define FEC_OC_IPR_INVERT_MD0__M … #define FEC_OC_IPR_INVERT_MD1__M … #define FEC_OC_IPR_INVERT_MD2__M … #define FEC_OC_IPR_INVERT_MD3__M … #define FEC_OC_IPR_INVERT_MD4__M … #define FEC_OC_IPR_INVERT_MD5__M … #define FEC_OC_IPR_INVERT_MD6__M … #define FEC_OC_IPR_INVERT_MD7__M … #define FEC_OC_IPR_INVERT_MERR__M … #define FEC_OC_IPR_INVERT_MSTRT__M … #define FEC_OC_IPR_INVERT_MVAL__M … #define FEC_OC_IPR_INVERT_MCLK__M … #define FEC_OC_OCR_INVERT__A … #define IQM_COMM_EXEC__A … #define IQM_COMM_EXEC_B_STOP … #define IQM_COMM_EXEC_B_ACTIVE … #define IQM_FS_RATE_OFS_LO__A … #define IQM_FS_ADJ_SEL__A … #define IQM_FS_ADJ_SEL_B_OFF … #define IQM_FS_ADJ_SEL_B_QAM … #define IQM_FS_ADJ_SEL_B_VSB … #define IQM_FD_RATESEL__A … #define IQM_RC_RATE_OFS_LO__A … #define IQM_RC_RATE_OFS_LO__W … #define IQM_RC_RATE_OFS_LO__M … #define IQM_RC_RATE_OFS_HI__M … #define IQM_RC_ADJ_SEL__A … #define IQM_RC_ADJ_SEL_B_OFF … #define IQM_RC_ADJ_SEL_B_QAM … #define IQM_RC_ADJ_SEL_B_VSB … #define IQM_RC_STRETCH__A … #define IQM_CF_COMM_INT_MSK__A … #define IQM_CF_SYMMETRIC__A … #define IQM_CF_MIDTAP__A … #define IQM_CF_MIDTAP_RE__B … #define IQM_CF_MIDTAP_IM__B … #define IQM_CF_OUT_ENA__A … #define IQM_CF_OUT_ENA_QAM__B … #define IQM_CF_OUT_ENA_OFDM__M … #define IQM_CF_ADJ_SEL__A … #define IQM_CF_SCALE__A … #define IQM_CF_SCALE_SH__A … #define IQM_CF_SCALE_SH__PRE … #define IQM_CF_POW_MEAS_LEN__A … #define IQM_CF_DS_ENA__A … #define IQM_CF_TAP_RE0__A … #define IQM_CF_TAP_IM0__A … #define IQM_CF_CLP_VAL__A … #define IQM_CF_DATATH__A … #define IQM_CF_PKDTH__A … #define IQM_CF_WND_LEN__A … #define IQM_CF_DET_LCT__A … #define IQM_CF_BYPASSDET__A … #define IQM_AF_COMM_EXEC__A … #define IQM_AF_COMM_EXEC_ACTIVE … #define IQM_AF_CLKNEG__A … #define IQM_AF_CLKNEG_CLKNEGDATA__M … #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_POS … #define IQM_AF_CLKNEG_CLKNEGDATA_CLK_ADC_DATA_NEG … #define IQM_AF_START_LOCK__A … #define IQM_AF_PHASE0__A … #define IQM_AF_PHASE1__A … #define IQM_AF_PHASE2__A … #define IQM_AF_CLP_LEN__A … #define IQM_AF_CLP_TH__A … #define IQM_AF_SNS_LEN__A … #define IQM_AF_AGC_IF__A … #define IQM_AF_AGC_RF__A … #define IQM_AF_PDREF__A … #define IQM_AF_PDREF__M … #define IQM_AF_STDBY__A … #define IQM_AF_STDBY_STDBY_ADC_STANDBY … #define IQM_AF_STDBY_STDBY_AMP_STANDBY … #define IQM_AF_STDBY_STDBY_PD_STANDBY … #define IQM_AF_STDBY_STDBY_TAGC_IF_STANDBY … #define IQM_AF_STDBY_STDBY_TAGC_RF_STANDBY … #define IQM_AF_AMUX__A … #define IQM_AF_AMUX_SIGNAL2ADC … #define IQM_AF_UPD_SEL__A … #define IQM_AF_INC_LCT__A … #define IQM_AF_INC_BYPASS__A … #define OFDM_CP_COMM_EXEC__A … #define OFDM_CP_COMM_EXEC_STOP … #define OFDM_EC_SB_PRIOR__A … #define OFDM_EC_SB_PRIOR_HI … #define OFDM_EC_SB_PRIOR_LO … #define OFDM_EC_VD_ERR_BIT_CNT__A … #define OFDM_EC_VD_IN_BIT_CNT__A … #define OFDM_EQ_TOP_TD_TPS_CONST__A … #define OFDM_EQ_TOP_TD_TPS_CONST__M … #define OFDM_EQ_TOP_TD_TPS_CONST_64QAM … #define OFDM_EQ_TOP_TD_TPS_CODE_HP__A … #define OFDM_EQ_TOP_TD_TPS_CODE_HP__M … #define OFDM_EQ_TOP_TD_TPS_CODE_LP_7_8 … #define OFDM_EQ_TOP_TD_SQR_ERR_I__A … #define OFDM_EQ_TOP_TD_SQR_ERR_Q__A … #define OFDM_EQ_TOP_TD_SQR_ERR_EXP__A … #define OFDM_EQ_TOP_TD_REQ_SMB_CNT__A … #define OFDM_EQ_TOP_TD_TPS_PWR_OFS__A … #define OFDM_LC_COMM_EXEC__A … #define OFDM_LC_COMM_EXEC_STOP … #define OFDM_SC_COMM_EXEC__A … #define OFDM_SC_COMM_EXEC_STOP … #define OFDM_SC_COMM_STATE__A … #define OFDM_SC_RA_RAM_PARAM0__A … #define OFDM_SC_RA_RAM_PARAM1__A … #define OFDM_SC_RA_RAM_CMD_ADDR__A … #define OFDM_SC_RA_RAM_CMD__A … #define OFDM_SC_RA_RAM_CMD_NULL … #define OFDM_SC_RA_RAM_CMD_PROC_START … #define OFDM_SC_RA_RAM_CMD_SET_PREF_PARAM … #define OFDM_SC_RA_RAM_CMD_PROGRAM_PARAM … #define OFDM_SC_RA_RAM_CMD_GET_OP_PARAM … #define OFDM_SC_RA_RAM_CMD_USER_IO … #define OFDM_SC_RA_RAM_CMD_SET_TIMER … #define OFDM_SC_RA_RAM_CMD_SET_ECHO_TIMING … #define OFDM_SC_RA_RAM_SW_EVENT_RUN_NMASK__M … #define OFDM_SC_RA_RAM_LOCKTRACK_MIN … #define OFDM_SC_RA_RAM_OP_PARAM__A … #define OFDM_SC_RA_RAM_OP_PARAM_MODE__M … #define OFDM_SC_RA_RAM_OP_PARAM_MODE_2K … #define OFDM_SC_RA_RAM_OP_PARAM_MODE_8K … #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_32 … #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_16 … #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_8 … #define OFDM_SC_RA_RAM_OP_PARAM_GUARD_4 … #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QPSK … #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM16 … #define OFDM_SC_RA_RAM_OP_PARAM_CONST_QAM64 … #define OFDM_SC_RA_RAM_OP_PARAM_HIER_NO … #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A1 … #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A2 … #define OFDM_SC_RA_RAM_OP_PARAM_HIER_A4 … #define OFDM_SC_RA_RAM_OP_PARAM_RATE_1_2 … #define OFDM_SC_RA_RAM_OP_PARAM_RATE_2_3 … #define OFDM_SC_RA_RAM_OP_PARAM_RATE_3_4 … #define OFDM_SC_RA_RAM_OP_PARAM_RATE_5_6 … #define OFDM_SC_RA_RAM_OP_PARAM_RATE_7_8 … #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_HI … #define OFDM_SC_RA_RAM_OP_PARAM_PRIO_LO … #define OFDM_SC_RA_RAM_OP_AUTO_MODE__M … #define OFDM_SC_RA_RAM_OP_AUTO_GUARD__M … #define OFDM_SC_RA_RAM_OP_AUTO_CONST__M … #define OFDM_SC_RA_RAM_OP_AUTO_HIER__M … #define OFDM_SC_RA_RAM_OP_AUTO_RATE__M … #define OFDM_SC_RA_RAM_LOCK__A … #define OFDM_SC_RA_RAM_LOCK_DEMOD__M … #define OFDM_SC_RA_RAM_LOCK_FEC__M … #define OFDM_SC_RA_RAM_LOCK_MPEG__M … #define OFDM_SC_RA_RAM_LOCK_NODVBT__M … #define OFDM_SC_RA_RAM_BE_OPT_DELAY__A … #define OFDM_SC_RA_RAM_BE_OPT_INIT_DELAY__A … #define OFDM_SC_RA_RAM_ECHO_THRES__A … #define OFDM_SC_RA_RAM_ECHO_THRES_8K__B … #define OFDM_SC_RA_RAM_ECHO_THRES_8K__M … #define OFDM_SC_RA_RAM_ECHO_THRES_2K__B … #define OFDM_SC_RA_RAM_ECHO_THRES_2K__M … #define OFDM_SC_RA_RAM_CONFIG__A … #define OFDM_SC_RA_RAM_CONFIG_NE_FIX_ENABLE__M … #define OFDM_SC_RA_RAM_FR_THRES_8K__A … #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_LEFT__A … #define OFDM_SC_RA_RAM_NI_INIT_2K_PER_RIGHT__A … #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_LEFT__A … #define OFDM_SC_RA_RAM_NI_INIT_8K_PER_RIGHT__A … #define OFDM_SC_RA_RAM_SRMM_FIX_FACT_8K__A … #define QAM_COMM_EXEC__A … #define QAM_COMM_EXEC_STOP … #define QAM_COMM_EXEC_ACTIVE … #define QAM_TOP_ANNEX_A … #define QAM_TOP_ANNEX_C … #define QAM_SL_ERR_POWER__A … #define QAM_DQ_QUAL_FUN0__A … #define QAM_DQ_QUAL_FUN1__A … #define QAM_DQ_QUAL_FUN2__A … #define QAM_DQ_QUAL_FUN3__A … #define QAM_DQ_QUAL_FUN4__A … #define QAM_DQ_QUAL_FUN5__A … #define QAM_LC_MODE__A … #define QAM_LC_QUAL_TAB0__A … #define QAM_LC_QUAL_TAB1__A … #define QAM_LC_QUAL_TAB2__A … #define QAM_LC_QUAL_TAB3__A … #define QAM_LC_QUAL_TAB4__A … #define QAM_LC_QUAL_TAB5__A … #define QAM_LC_QUAL_TAB6__A … #define QAM_LC_QUAL_TAB8__A … #define QAM_LC_QUAL_TAB9__A … #define QAM_LC_QUAL_TAB10__A … #define QAM_LC_QUAL_TAB12__A … #define QAM_LC_QUAL_TAB15__A … #define QAM_LC_QUAL_TAB16__A … #define QAM_LC_QUAL_TAB20__A … #define QAM_LC_QUAL_TAB25__A … #define QAM_LC_LPF_FACTORP__A … #define QAM_LC_LPF_FACTORI__A … #define QAM_LC_RATE_LIMIT__A … #define QAM_LC_SYMBOL_FREQ__A … #define QAM_SY_TIMEOUT__A … #define QAM_SY_TIMEOUT__PRE … #define QAM_SY_SYNC_LWM__A … #define QAM_SY_SYNC_AWM__A … #define QAM_SY_SYNC_HWM__A … #define QAM_SY_SP_INV__A … #define QAM_SY_SP_INV_SPECTRUM_INV_DIS … #define SCU_COMM_EXEC__A … #define SCU_COMM_EXEC_STOP … #define SCU_COMM_EXEC_ACTIVE … #define SCU_COMM_EXEC_HOLD … #define SCU_RAM_DRIVER_DEBUG__A … #define SCU_RAM_QAM_FSM_STEP_PERIOD__A … #define SCU_RAM_GPIO__A … #define SCU_RAM_GPIO_HW_LOCK_IND_DISABLE … #define SCU_RAM_AGC_CLP_CTRL_MODE__A … #define SCU_RAM_FEC_ACCUM_PKT_FAILURES__A … #define SCU_RAM_FEC_PRE_RS_BER_FILTER_SH__A … #define SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A … #define SCU_RAM_AGC_KI_CYCLEN__A … #define SCU_RAM_AGC_SNS_CYCLEN__A … #define SCU_RAM_AGC_RF_SNS_DEV_MAX__A … #define SCU_RAM_AGC_RF_SNS_DEV_MIN__A … #define SCU_RAM_AGC_RF_MAX__A … #define SCU_RAM_AGC_CONFIG__A … #define SCU_RAM_AGC_CONFIG_DISABLE_RF_AGC__M … #define SCU_RAM_AGC_CONFIG_DISABLE_IF_AGC__M … #define SCU_RAM_AGC_CONFIG_INV_IF_POL__M … #define SCU_RAM_AGC_CONFIG_INV_RF_POL__M … #define SCU_RAM_AGC_KI__A … #define SCU_RAM_AGC_KI_RF__B … #define SCU_RAM_AGC_KI_RF__M … #define SCU_RAM_AGC_KI_IF__B … #define SCU_RAM_AGC_KI_IF__M … #define SCU_RAM_AGC_KI_RED__A … #define SCU_RAM_AGC_KI_RED_RAGC_RED__B … #define SCU_RAM_AGC_KI_RED_RAGC_RED__M … #define SCU_RAM_AGC_KI_RED_IAGC_RED__B … #define SCU_RAM_AGC_KI_RED_IAGC_RED__M … #define SCU_RAM_AGC_KI_INNERGAIN_MIN__A … #define SCU_RAM_AGC_KI_MINGAIN__A … #define SCU_RAM_AGC_KI_MAXGAIN__A … #define SCU_RAM_AGC_KI_MAXMINGAIN_TH__A … #define SCU_RAM_AGC_KI_MIN__A … #define SCU_RAM_AGC_KI_MAX__A … #define SCU_RAM_AGC_CLP_SUM__A … #define SCU_RAM_AGC_CLP_SUM_MIN__A … #define SCU_RAM_AGC_CLP_SUM_MAX__A … #define SCU_RAM_AGC_CLP_CYCLEN__A … #define SCU_RAM_AGC_CLP_CYCCNT__A … #define SCU_RAM_AGC_CLP_DIR_TO__A … #define SCU_RAM_AGC_CLP_DIR_WD__A … #define SCU_RAM_AGC_CLP_DIR_STP__A … #define SCU_RAM_AGC_SNS_SUM__A … #define SCU_RAM_AGC_SNS_SUM_MIN__A … #define SCU_RAM_AGC_SNS_SUM_MAX__A … #define SCU_RAM_AGC_SNS_CYCCNT__A … #define SCU_RAM_AGC_SNS_DIR_TO__A … #define SCU_RAM_AGC_SNS_DIR_WD__A … #define SCU_RAM_AGC_SNS_DIR_STP__A … #define SCU_RAM_AGC_INGAIN_TGT__A … #define SCU_RAM_AGC_INGAIN_TGT_MIN__A … #define SCU_RAM_AGC_INGAIN_TGT_MAX__A … #define SCU_RAM_AGC_IF_IACCU_HI__A … #define SCU_RAM_AGC_IF_IACCU_LO__A … #define SCU_RAM_AGC_IF_IACCU_HI_TGT__A … #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A … #define SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A … #define SCU_RAM_AGC_RF_IACCU_HI__A … #define SCU_RAM_AGC_RF_IACCU_LO__A … #define SCU_RAM_AGC_RF_IACCU_HI_CO__A … #define SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A … #define SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A … #define SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A … #define SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A … #define SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A … #define SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A … #define SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A … #define SCU_RAM_QAM_FSM_RTH__A … #define SCU_RAM_QAM_FSM_FTH__A … #define SCU_RAM_QAM_FSM_PTH__A … #define SCU_RAM_QAM_FSM_MTH__A … #define SCU_RAM_QAM_FSM_CTH__A … #define SCU_RAM_QAM_FSM_QTH__A … #define SCU_RAM_QAM_FSM_RATE_LIM__A … #define SCU_RAM_QAM_FSM_FREQ_LIM__A … #define SCU_RAM_QAM_FSM_COUNT_LIM__A … #define SCU_RAM_QAM_LC_CA_COARSE__A … #define SCU_RAM_QAM_LC_CA_FINE__A … #define SCU_RAM_QAM_LC_CP_COARSE__A … #define SCU_RAM_QAM_LC_CP_MEDIUM__A … #define SCU_RAM_QAM_LC_CP_FINE__A … #define SCU_RAM_QAM_LC_CI_COARSE__A … #define SCU_RAM_QAM_LC_CI_MEDIUM__A … #define SCU_RAM_QAM_LC_CI_FINE__A … #define SCU_RAM_QAM_LC_EP_COARSE__A … #define SCU_RAM_QAM_LC_EP_MEDIUM__A … #define SCU_RAM_QAM_LC_EP_FINE__A … #define SCU_RAM_QAM_LC_EI_COARSE__A … #define SCU_RAM_QAM_LC_EI_MEDIUM__A … #define SCU_RAM_QAM_LC_EI_FINE__A … #define SCU_RAM_QAM_LC_CF_COARSE__A … #define SCU_RAM_QAM_LC_CF_MEDIUM__A … #define SCU_RAM_QAM_LC_CF_FINE__A … #define SCU_RAM_QAM_LC_CF1_COARSE__A … #define SCU_RAM_QAM_LC_CF1_MEDIUM__A … #define SCU_RAM_QAM_LC_CF1_FINE__A … #define SCU_RAM_QAM_SL_SIG_POWER__A … #define SCU_RAM_QAM_EQ_CMA_RAD0__A … #define SCU_RAM_QAM_EQ_CMA_RAD1__A … #define SCU_RAM_QAM_EQ_CMA_RAD2__A … #define SCU_RAM_QAM_EQ_CMA_RAD3__A … #define SCU_RAM_QAM_EQ_CMA_RAD4__A … #define SCU_RAM_QAM_EQ_CMA_RAD5__A … #define SCU_RAM_QAM_LOCKED_LOCKED_DEMOD_LOCKED … #define SCU_RAM_QAM_LOCKED_LOCKED_LOCKED … #define SCU_RAM_QAM_LOCKED_LOCKED_NEVER_LOCK … #define SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A … #define SCU_RAM_DRIVER_VER_HI__A … #define SCU_RAM_DRIVER_VER_LO__A … #define SCU_RAM_PARAM_15__A … #define SCU_RAM_PARAM_0__A … #define SCU_RAM_COMMAND__A … #define SCU_RAM_COMMAND_CMD_DEMOD_RESET … #define SCU_RAM_COMMAND_CMD_DEMOD_SET_ENV … #define SCU_RAM_COMMAND_CMD_DEMOD_SET_PARAM … #define SCU_RAM_COMMAND_CMD_DEMOD_START … #define SCU_RAM_COMMAND_CMD_DEMOD_GET_LOCK … #define SCU_RAM_COMMAND_CMD_DEMOD_STOP … #define SCU_RAM_COMMAND_STANDARD_QAM … #define SCU_RAM_COMMAND_STANDARD_OFDM … #define SIO_TOP_COMM_KEY__A … #define SIO_TOP_COMM_KEY_KEY … #define SIO_TOP_JTAGID_LO__A … #define SIO_HI_RA_RAM_RES__A … #define SIO_HI_RA_RAM_CMD__A … #define SIO_HI_RA_RAM_CMD_RESET … #define SIO_HI_RA_RAM_CMD_CONFIG … #define SIO_HI_RA_RAM_CMD_BRDCTRL … #define SIO_HI_RA_RAM_PAR_1__A … #define SIO_HI_RA_RAM_PAR_1_PAR1_SEC_KEY … #define SIO_HI_RA_RAM_PAR_2__A … #define SIO_HI_RA_RAM_PAR_2_CFG_DIV__M … #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_OPEN … #define SIO_HI_RA_RAM_PAR_2_BRD_CFG_CLOSED … #define SIO_HI_RA_RAM_PAR_3__A … #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SDA__M … #define SIO_HI_RA_RAM_PAR_3_CFG_DBL_SCL__B … #define SIO_HI_RA_RAM_PAR_3_ACP_RW_READ … #define SIO_HI_RA_RAM_PAR_3_ACP_RW_WRITE … #define SIO_HI_RA_RAM_PAR_4__A … #define SIO_HI_RA_RAM_PAR_5__A … #define SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE … #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP__M … #define SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ … #define SIO_HI_RA_RAM_PAR_6__A … #define SIO_CC_PLL_LOCK__A … #define SIO_CC_PWD_MODE__A … #define SIO_CC_PWD_MODE_LEVEL_NONE … #define SIO_CC_PWD_MODE_LEVEL_OFDM … #define SIO_CC_PWD_MODE_LEVEL_CLOCK … #define SIO_CC_PWD_MODE_LEVEL_PLL … #define SIO_CC_PWD_MODE_LEVEL_OSC … #define SIO_CC_SOFT_RST__A … #define SIO_CC_SOFT_RST_OFDM__M … #define SIO_CC_SOFT_RST_SYS__M … #define SIO_CC_SOFT_RST_OSC__M … #define SIO_CC_UPDATE__A … #define SIO_CC_UPDATE_KEY … #define SIO_OFDM_SH_OFDM_RING_ENABLE__A … #define SIO_OFDM_SH_OFDM_RING_ENABLE_OFF … #define SIO_OFDM_SH_OFDM_RING_ENABLE_ON … #define SIO_OFDM_SH_OFDM_RING_STATUS__A … #define SIO_OFDM_SH_OFDM_RING_STATUS_DOWN … #define SIO_OFDM_SH_OFDM_RING_STATUS_ENABLED … #define SIO_BL_COMM_EXEC__A … #define SIO_BL_COMM_EXEC_ACTIVE … #define SIO_BL_STATUS__A … #define SIO_BL_MODE__A … #define SIO_BL_MODE_DIRECT … #define SIO_BL_MODE_CHAIN … #define SIO_BL_ENABLE__A … #define SIO_BL_ENABLE_ON … #define SIO_BL_TGT_HDR__A … #define SIO_BL_TGT_ADDR__A … #define SIO_BL_SRC_ADDR__A … #define SIO_BL_SRC_LEN__A … #define SIO_BL_CHAIN_ADDR__A … #define SIO_BL_CHAIN_LEN__A … #define SIO_PDR_MON_CFG__A … #define SIO_PDR_UIO_IN_HI__A … #define SIO_PDR_UIO_OUT_LO__A … #define SIO_PDR_OHW_CFG__A … #define SIO_PDR_OHW_CFG_FREF_SEL__M … #define SIO_PDR_GPIO_CFG__A … #define SIO_PDR_MSTRT_CFG__A … #define SIO_PDR_MERR_CFG__A … #define SIO_PDR_MCLK_CFG__A … #define SIO_PDR_MCLK_CFG_DRIVE__B … #define SIO_PDR_MVAL_CFG__A … #define SIO_PDR_MD0_CFG__A … #define SIO_PDR_MD0_CFG_DRIVE__B … #define SIO_PDR_MD1_CFG__A … #define SIO_PDR_MD2_CFG__A … #define SIO_PDR_MD3_CFG__A … #define SIO_PDR_MD4_CFG__A … #define SIO_PDR_MD5_CFG__A … #define SIO_PDR_MD6_CFG__A … #define SIO_PDR_MD7_CFG__A … #define SIO_PDR_SMA_RX_CFG__A … #define SIO_PDR_SMA_TX_CFG__A …
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