linux/drivers/media/dvb-frontends/mxl5xx.c

// SPDX-License-Identifier: GPL-2.0
/*
 * Driver for the MaxLinear MxL5xx family of tuners/demods
 *
 * Copyright (C) 2014-2015 Ralph Metzler <[email protected]>
 *                         Marcus Metzler <[email protected]>
 *                         developed for Digital Devices GmbH
 *
 * based on code:
 * Copyright (c) 2011-2013 MaxLinear, Inc. All rights reserved
 * which was released under GPL V2
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/mutex.h>
#include <linux/vmalloc.h>
#include <asm/div64.h>
#include <linux/unaligned.h>

#include <media/dvb_frontend.h>
#include "mxl5xx.h"
#include "mxl5xx_regs.h"
#include "mxl5xx_defs.h"

#define BYTE0(v)
#define BYTE1(v)
#define BYTE2(v)
#define BYTE3(v)

static LIST_HEAD(mxllist);

struct mxl_base {};

struct mxl {};

static void convert_endian(u8 flag, u32 size, u8 *d)
{}

static int i2c_write(struct i2c_adapter *adap, u8 adr,
			    u8 *data, u32 len)
{}

static int i2c_read(struct i2c_adapter *adap, u8 adr,
			   u8 *data, u32 len)
{}

static int i2cread(struct mxl *state, u8 *data, int len)
{}

static int i2cwrite(struct mxl *state, u8 *data, int len)
{}

static int read_register_unlocked(struct mxl *state, u32 reg, u32 *val)
{}

#define DMA_I2C_INTERRUPT_ADDR
#define DMA_INTR_PROT_WR_CMP

static int send_command(struct mxl *state, u32 size, u8 *buf)
{}

static int write_register(struct mxl *state, u32 reg, u32 val)
{}

static int write_firmware_block(struct mxl *state,
				u32 reg, u32 size, u8 *reg_data_ptr)
{}

static int read_register(struct mxl *state, u32 reg, u32 *val)
{}

static int read_register_block(struct mxl *state, u32 reg, u32 size, u8 *data)
{}

static int read_by_mnemonic(struct mxl *state,
			    u32 reg, u8 lsbloc, u8 numofbits, u32 *val)
{}


static int update_by_mnemonic(struct mxl *state,
			      u32 reg, u8 lsbloc, u8 numofbits, u32 val)
{}

static int firmware_is_alive(struct mxl *state)
{}

static int init(struct dvb_frontend *fe)
{}

static void release(struct dvb_frontend *fe)
{}

static enum dvbfe_algo get_algo(struct dvb_frontend *fe)
{}

static u32 gold2root(u32 gold)
{}

static int cfg_scrambler(struct mxl *state, u32 gold)
{}

static int cfg_demod_abort_tune(struct mxl *state)
{}

static int send_master_cmd(struct dvb_frontend *fe,
			   struct dvb_diseqc_master_cmd *cmd)
{}

static int set_parameters(struct dvb_frontend *fe)
{}

static int enable_tuner(struct mxl *state, u32 tuner, u32 enable);

static int sleep(struct dvb_frontend *fe)
{}

static int read_snr(struct dvb_frontend *fe)
{}

static int read_ber(struct dvb_frontend *fe)
{}

static int read_signal_strength(struct dvb_frontend *fe)
{}

static int read_status(struct dvb_frontend *fe, enum fe_status *status)
{}

static int tune(struct dvb_frontend *fe, bool re_tune,
		unsigned int mode_flags,
		unsigned int *delay, enum fe_status *status)
{}

static enum fe_code_rate conv_fec(enum MXL_HYDRA_FEC_E fec)
{}

static int get_frontend(struct dvb_frontend *fe,
			struct dtv_frontend_properties *p)
{}

static int set_input(struct dvb_frontend *fe, int input)
{}

static const struct dvb_frontend_ops mxl_ops =;

static struct mxl_base *match_base(struct i2c_adapter  *i2c, u8 adr)
{}

static void cfg_dev_xtal(struct mxl *state, u32 freq, u32 cap, u32 enable)
{}

static u32 get_big_endian(u8 num_of_bits, const u8 buf[])
{}

static int write_fw_segment(struct mxl *state,
			    u32 mem_addr, u32 total_size, u8 *data_ptr)
{}

static int do_firmware_download(struct mxl *state, u8 *mbin_buffer_ptr,
				u32 mbin_buffer_size)

{}

static int check_fw(struct mxl *state, u8 *mbin, u32 mbin_len)
{}

static int firmware_download(struct mxl *state, u8 *mbin, u32 mbin_len)
{}

static int cfg_ts_pad_mux(struct mxl *state, enum MXL_BOOL_E enable_serial_ts)
{}

static int set_drive_strength(struct mxl *state,
		enum MXL_HYDRA_TS_DRIVE_STRENGTH_E ts_drive_strength)
{}

static int enable_tuner(struct mxl *state, u32 tuner, u32 enable)
{}


static int config_ts(struct mxl *state, enum MXL_HYDRA_DEMOD_ID_E demod_id,
		     struct MXL_HYDRA_MPEGOUT_PARAM_T *mpeg_out_param_ptr)
{}

static int config_mux(struct mxl *state)
{}

static int load_fw(struct mxl *state, struct mxl5xx_cfg *cfg)
{}

static int validate_sku(struct mxl *state)
{}

static int get_fwinfo(struct mxl *state)
{}


static u8 ts_map1_to_1[MXL_HYDRA_DEMOD_MAX] =;

static u8 ts_map54x[MXL_HYDRA_DEMOD_MAX] =;

static int probe(struct mxl *state, struct mxl5xx_cfg *cfg)
{}

struct dvb_frontend *mxl5xx_attach(struct i2c_adapter *i2c,
	struct mxl5xx_cfg *cfg, u32 demod, u32 tuner,
	int (**fn_set_input)(struct dvb_frontend *, int))
{}
EXPORT_SYMBOL_GPL();

MODULE_DESCRIPTION();
MODULE_AUTHOR();
MODULE_LICENSE();