linux/drivers/media/dvb-frontends/stv0367_regs.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * stv0367_regs.h
 *
 * Driver for ST STV0367 DVB-T & DVB-C demodulator IC.
 *
 * Copyright (C) ST Microelectronics.
 * Copyright (C) 2010,2011 NetUP Inc.
 * Copyright (C) 2010,2011 Igor M. Liplianin <[email protected]>
 */

#ifndef STV0367_REGS_H
#define STV0367_REGS_H

/* ID */
#define R367TER_ID
#define F367TER_IDENTIFICATIONREG

/* I2CRPT */
#define R367TER_I2CRPT
#define F367TER_I2CT_ON
#define F367TER_ENARPT_LEVEL
#define F367TER_SCLT_DELAY
#define F367TER_SCLT_NOD
#define F367TER_STOP_ENABLE
#define F367TER_SDAT_NOD

/* TOPCTRL */
#define R367TER_TOPCTRL
#define F367TER_STDBY
#define F367TER_STDBY_FEC
#define F367TER_STDBY_CORE
#define F367TER_QAM_COFDM
#define F367TER_TS_DIS
#define F367TER_DIR_CLK_216
#define F367TER_TUNER_BB
#define F367TER_DVBT_H

/* IOCFG0 */
#define R367TER_IOCFG0
#define F367TER_OP0_SD
#define F367TER_OP0_VAL
#define F367TER_OP0_OD
#define F367TER_OP0_INV
#define F367TER_OP0_DACVALUE_HI

/* DAc0R */
#define R367TER_DAC0R
#define F367TER_OP0_DACVALUE_LO

/* IOCFG1 */
#define R367TER_IOCFG1
#define F367TER_IP0
#define F367TER_OP1_OD
#define F367TER_OP1_INV
#define F367TER_OP1_DACVALUE_HI

/* DAC1R */
#define R367TER_DAC1R
#define F367TER_OP1_DACVALUE_LO

/* IOCFG2 */
#define R367TER_IOCFG2
#define F367TER_OP2_LOCK_CONF
#define F367TER_OP2_OD
#define F367TER_OP2_VAL
#define F367TER_OP1_LOCK_CONF

/* SDFR */
#define R367TER_SDFR
#define F367TER_OP0_FREQ
#define F367TER_OP1_FREQ

/* STATUS */
#define R367TER_STATUS
#define F367TER_TPS_LOCK
#define F367TER_SYR_LOCK
#define F367TER_AGC_LOCK
#define F367TER_PRF
#define F367TER_LK
#define F367TER_PR

/* AUX_CLK */
#define R367TER_AUX_CLK
#define F367TER_AUXFEC_CTL
#define F367TER_DIS_CKX4
#define F367TER_CKSEL
#define F367TER_CKDIV_PROG
#define F367TER_AUXCLK_ENA

/* FREESYS1 */
#define R367TER_FREESYS1
#define F367TER_FREE_SYS1

/* FREESYS2 */
#define R367TER_FREESYS2
#define F367TER_FREE_SYS2

/* FREESYS3 */
#define R367TER_FREESYS3
#define F367TER_FREE_SYS3

/* GPIO_CFG */
#define R367TER_GPIO_CFG
#define F367TER_GPIO7_NOD
#define F367TER_GPIO7_CFG
#define F367TER_GPIO6_NOD
#define F367TER_GPIO6_CFG
#define F367TER_GPIO5_NOD
#define F367TER_GPIO5_CFG
#define F367TER_GPIO4_NOD
#define F367TER_GPIO4_CFG

/* GPIO_CMD */
#define R367TER_GPIO_CMD
#define F367TER_GPIO7_VAL
#define F367TER_GPIO6_VAL
#define F367TER_GPIO5_VAL
#define F367TER_GPIO4_VAL

/* AGC2MAX */
#define R367TER_AGC2MAX
#define F367TER_AGC2_MAX

/* AGC2MIN */
#define R367TER_AGC2MIN
#define F367TER_AGC2_MIN

/* AGC1MAX */
#define R367TER_AGC1MAX
#define F367TER_AGC1_MAX

/* AGC1MIN */
#define R367TER_AGC1MIN
#define F367TER_AGC1_MIN

/* AGCR */
#define R367TER_AGCR
#define F367TER_RATIO_A
#define F367TER_RATIO_B
#define F367TER_RATIO_C

/* AGC2TH */
#define R367TER_AGC2TH
#define F367TER_AGC2_THRES

/* AGC12c */
#define R367TER_AGC12C
#define F367TER_AGC1_IV
#define F367TER_AGC1_OD
#define F367TER_AGC1_LOAD
#define F367TER_AGC2_IV
#define F367TER_AGC2_OD
#define F367TER_AGC2_LOAD
#define F367TER_AGC12_MODE

/* AGCCTRL1 */
#define R367TER_AGCCTRL1
#define F367TER_DAGC_ON
#define F367TER_INVERT_AGC12
#define F367TER_AGC1_MODE
#define F367TER_AGC2_MODE

/* AGCCTRL2 */
#define R367TER_AGCCTRL2
#define F367TER_FRZ2_CTRL
#define F367TER_FRZ1_CTRL
#define F367TER_TIME_CST

/* AGC1VAL1 */
#define R367TER_AGC1VAL1
#define F367TER_AGC1_VAL_LO

/* AGC1VAL2 */
#define R367TER_AGC1VAL2
#define F367TER_AGC1_VAL_HI

/* AGC2VAL1 */
#define R367TER_AGC2VAL1
#define F367TER_AGC2_VAL_LO

/* AGC2VAL2 */
#define R367TER_AGC2VAL2
#define F367TER_AGC2_VAL_HI

/* AGC2PGA */
#define R367TER_AGC2PGA
#define F367TER_AGC2_PGA

/* OVF_RATE1 */
#define R367TER_OVF_RATE1
#define F367TER_OVF_RATE_HI

/* OVF_RATE2 */
#define R367TER_OVF_RATE2
#define F367TER_OVF_RATE_LO

/* GAIN_SRC1 */
#define R367TER_GAIN_SRC1
#define F367TER_INV_SPECTR
#define F367TER_IQ_INVERT
#define F367TER_INR_BYPASS
#define F367TER_STATUS_INV_SPECRUM
#define F367TER_GAIN_SRC_HI

/* GAIN_SRC2 */
#define R367TER_GAIN_SRC2
#define F367TER_GAIN_SRC_LO

/* INC_DEROT1 */
#define R367TER_INC_DEROT1
#define F367TER_INC_DEROT_HI

/* INC_DEROT2 */
#define R367TER_INC_DEROT2
#define F367TER_INC_DEROT_LO

/* PPM_CPAMP_DIR */
#define R367TER_PPM_CPAMP_DIR
#define F367TER_PPM_CPAMP_DIRECT

/* PPM_CPAMP_INV */
#define R367TER_PPM_CPAMP_INV
#define F367TER_PPM_CPAMP_INVER

/* FREESTFE_1 */
#define R367TER_FREESTFE_1
#define F367TER_SYMBOL_NUMBER_INC
#define F367TER_SEL_LSB
#define F367TER_AVERAGE_ON
#define F367TER_DC_ADJ

/* FREESTFE_2 */
#define R367TER_FREESTFE_2
#define F367TER_SEL_SRCOUT
#define F367TER_SEL_SYRTHR

/* DCOFFSET */
#define R367TER_DCOFFSET
#define F367TER_SELECT_I_Q
#define F367TER_DC_OFFSET

/* EN_PROCESS */
#define R367TER_EN_PROCESS
#define F367TER_FREE
#define F367TER_ENAB_MANUAL

/* SDI_SMOOTHER */
#define R367TER_SDI_SMOOTHER
#define F367TER_DIS_SMOOTH
#define F367TER_SDI_INC_SMOOTHER

/* FE_LOOP_OPEN */
#define R367TER_FE_LOOP_OPEN
#define F367TER_TRL_LOOP_OP
#define F367TER_CRL_LOOP_OP

/* FREQOFF1 */
#define R367TER_FREQOFF1
#define F367TER_FREQ_OFFSET_LOOP_OPEN_VHI

/* FREQOFF2 */
#define R367TER_FREQOFF2
#define F367TER_FREQ_OFFSET_LOOP_OPEN_HI

/* FREQOFF3 */
#define R367TER_FREQOFF3
#define F367TER_FREQ_OFFSET_LOOP_OPEN_LO

/* TIMOFF1 */
#define R367TER_TIMOFF1
#define F367TER_TIM_OFFSET_LOOP_OPEN_HI

/* TIMOFF2 */
#define R367TER_TIMOFF2
#define F367TER_TIM_OFFSET_LOOP_OPEN_LO

/* EPQ */
#define R367TER_EPQ
#define F367TER_EPQ1

/* EPQAUTO */
#define R367TER_EPQAUTO
#define F367TER_EPQ2

/* SYR_UPDATE */
#define R367TER_SYR_UPDATE
#define F367TER_SYR_PROTV
#define F367TER_SYR_PROTV_GAIN
#define F367TER_SYR_FILTER
#define F367TER_SYR_TRACK_THRES

/* CHPFREE */
#define R367TER_CHPFREE
#define F367TER_CHP_FREE

/* PPM_STATE_MAC */
#define R367TER_PPM_STATE_MAC
#define F367TER_PPM_STATE_MACHINE_DECODER

/* INR_THRESHOLD */
#define R367TER_INR_THRESHOLD
#define F367TER_INR_THRESH

/* EPQ_TPS_ID_CELL */
#define R367TER_EPQ_TPS_ID_CELL
#define F367TER_ENABLE_LGTH_TO_CF
#define F367TER_DIS_TPS_RSVD
#define F367TER_DIS_BCH
#define F367TER_DIS_ID_CEL
#define F367TER_TPS_ADJUST_SYM

/* EPQ_CFG */
#define R367TER_EPQ_CFG
#define F367TER_EPQ_RANGE
#define F367TER_EPQ_SOFT

/* EPQ_STATUS */
#define R367TER_EPQ_STATUS
#define F367TER_SLOPE_INC
#define F367TER_TPS_FIELD

/* AUTORELOCK */
#define R367TER_AUTORELOCK
#define F367TER_BYPASS_BER_TEMPO
#define F367TER_BER_TEMPO
#define F367TER_BYPASS_COFDM_TEMPO
#define F367TER_COFDM_TEMPO

/* BER_THR_VMSB */
#define R367TER_BER_THR_VMSB
#define F367TER_BER_THRESHOLD_HI

/* BER_THR_MSB */
#define R367TER_BER_THR_MSB
#define F367TER_BER_THRESHOLD_MID

/* BER_THR_LSB */
#define R367TER_BER_THR_LSB
#define F367TER_BER_THRESHOLD_LO

/* CCD */
#define R367TER_CCD
#define F367TER_CCD_DETECTED
#define F367TER_CCD_RESET
#define F367TER_CCD_THRESHOLD

/* SPECTR_CFG */
#define R367TER_SPECTR_CFG
#define F367TER_SPECT_CFG

/* CONSTMU_MSB */
#define R367TER_CONSTMU_MSB
#define F367TER_CONSTMU_FREEZE
#define F367TER_CONSTNU_FORCE_EN
#define F367TER_CONST_MU_MSB

/* CONSTMU_LSB */
#define R367TER_CONSTMU_LSB
#define F367TER_CONST_MU_LSB

/* CONSTMU_MAX_MSB */
#define R367TER_CONSTMU_MAX_MSB
#define F367TER_CONST_MU_MAX_MSB

/* CONSTMU_MAX_LSB */
#define R367TER_CONSTMU_MAX_LSB
#define F367TER_CONST_MU_MAX_LSB

/* ALPHANOISE */
#define R367TER_ALPHANOISE
#define F367TER_USE_ALLFILTER
#define F367TER_INTER_ON
#define F367TER_ALPHA_NOISE

/* MAXGP_MSB */
#define R367TER_MAXGP_MSB
#define F367TER_MUFILTER_LENGTH
#define F367TER_MAX_GP_MSB

/* MAXGP_LSB */
#define R367TER_MAXGP_LSB
#define F367TER_MAX_GP_LSB

/* ALPHAMSB */
#define R367TER_ALPHAMSB
#define F367TER_CHC_DATARATE
#define F367TER_ALPHA_MSB

/* ALPHALSB */
#define R367TER_ALPHALSB
#define F367TER_ALPHA_LSB

/* PILOT_ACCU */
#define R367TER_PILOT_ACCU
#define F367TER_USE_SCAT4ADDAPT
#define F367TER_PILOT_ACC

/* PILOTMU_ACCU */
#define R367TER_PILOTMU_ACCU
#define F367TER_DISCARD_BAD_SP
#define F367TER_DISCARD_BAD_CP
#define F367TER_PILOT_MU_ACCU

/* FILT_CHANNEL_EST */
#define R367TER_FILT_CHANNEL_EST
#define F367TER_USE_FILT_PILOT
#define F367TER_FILT_CHANNEL

/* ALPHA_NOPISE_FREQ */
#define R367TER_ALPHA_NOPISE_FREQ
#define F367TER_NOISE_FREQ_FILT
#define F367TER_ALPHA_NOISE_FREQ

/* RATIO_PILOT */
#define R367TER_RATIO_PILOT
#define F367TER_RATIO_MEAN_SP
#define F367TER_RATIO_MEAN_CP

/* CHC_CTL */
#define R367TER_CHC_CTL
#define F367TER_TRACK_EN
#define F367TER_NOISE_NORM_EN
#define F367TER_FORCE_CHC_RESET
#define F367TER_SHORT_TIME
#define F367TER_FORCE_STATE_EN
#define F367TER_FORCE_STATE

/* EPQ_ADJUST */
#define R367TER_EPQ_ADJUST
#define F367TER_ADJUST_SCAT_IND
#define F367TER_ONE_SYMBOL
#define F367TER_EPQ_DECAY
#define F367TER_HOLD_SLOPE

/* EPQ_THRES */
#define R367TER_EPQ_THRES
#define F367TER_EPQ_THR

/* OMEGA_CTL */
#define R367TER_OMEGA_CTL
#define F367TER_OMEGA_RST
#define F367TER_FREEZE_OMEGA
#define F367TER_OMEGA_SEL

/* GP_CTL */
#define R367TER_GP_CTL
#define F367TER_CHC_STATE
#define F367TER_FREEZE_GP
#define F367TER_GP_SEL

/* MUMSB */
#define R367TER_MUMSB
#define F367TER_MU_MSB

/* MULSB */
#define R367TER_MULSB
#define F367TER_MU_LSB

/* GPMSB */
#define R367TER_GPMSB
#define F367TER_CSI_THRESHOLD
#define F367TER_GP_MSB

/* GPLSB */
#define R367TER_GPLSB
#define F367TER_GP_LSB

/* OMEGAMSB */
#define R367TER_OMEGAMSB
#define F367TER_OMEGA_MSB

/* OMEGALSB */
#define R367TER_OMEGALSB
#define F367TER_OMEGA_LSB

/* SCAT_NB */
#define R367TER_SCAT_NB
#define F367TER_CHC_TEST
#define F367TER_SCAT_NUMB

/* CHC_DUMMY */
#define R367TER_CHC_DUMMY
#define F367TER_CHC_DUM

/* INC_CTL */
#define R367TER_INC_CTL
#define F367TER_INC_BYPASS
#define F367TER_INC_NDEPTH
#define F367TER_INC_MADEPTH

/* INCTHRES_COR1 */
#define R367TER_INCTHRES_COR1
#define F367TER_INC_THRES_COR1

/* INCTHRES_COR2 */
#define R367TER_INCTHRES_COR2
#define F367TER_INC_THRES_COR2

/* INCTHRES_DET1 */
#define R367TER_INCTHRES_DET1
#define F367TER_INC_THRES_DET1

/* INCTHRES_DET2 */
#define R367TER_INCTHRES_DET2
#define F367TER_INC_THRES_DET2

/* IIR_CELLNB */
#define R367TER_IIR_CELLNB
#define F367TER_NRST_IIR
#define F367TER_IIR_CELL_NB

/* IIRCX_COEFF1_MSB */
#define R367TER_IIRCX_COEFF1_MSB
#define F367TER_IIR_CX_COEFF1_MSB

/* IIRCX_COEFF1_LSB */
#define R367TER_IIRCX_COEFF1_LSB
#define F367TER_IIR_CX_COEFF1_LSB

/* IIRCX_COEFF2_MSB */
#define R367TER_IIRCX_COEFF2_MSB
#define F367TER_IIR_CX_COEFF2_MSB

/* IIRCX_COEFF2_LSB */
#define R367TER_IIRCX_COEFF2_LSB
#define F367TER_IIR_CX_COEFF2_LSB

/* IIRCX_COEFF3_MSB */
#define R367TER_IIRCX_COEFF3_MSB
#define F367TER_IIR_CX_COEFF3_MSB

/* IIRCX_COEFF3_LSB */
#define R367TER_IIRCX_COEFF3_LSB
#define F367TER_IIR_CX_COEFF3_LSB

/* IIRCX_COEFF4_MSB */
#define R367TER_IIRCX_COEFF4_MSB
#define F367TER_IIR_CX_COEFF4_MSB

/* IIRCX_COEFF4_LSB */
#define R367TER_IIRCX_COEFF4_LSB
#define F367TER_IIR_CX_COEFF4_LSB

/* IIRCX_COEFF5_MSB */
#define R367TER_IIRCX_COEFF5_MSB
#define F367TER_IIR_CX_COEFF5_MSB

/* IIRCX_COEFF5_LSB */
#define R367TER_IIRCX_COEFF5_LSB
#define F367TER_IIR_CX_COEFF5_LSB

/* FEPATH_CFG */
#define R367TER_FEPATH_CFG
#define F367TER_DEMUX_SWAP
#define F367TER_DIGAGC_SWAP
#define F367TER_LONGPATH_IF

/* PMC1_FUNC */
#define R367TER_PMC1_FUNC
#define F367TER_SOFT_RSTN
#define F367TER_PMC1_AVERAGE_TIME
#define F367TER_PMC1_WAIT_TIME
#define F367TER_PMC1_2N_SEL

/* PMC1_FOR */
#define R367TER_PMC1_FOR
#define F367TER_PMC1_FORCE
#define F367TER_PMC1_FORCE_VALUE

/* PMC2_FUNC */
#define R367TER_PMC2_FUNC
#define F367TER_PMC2_SOFT_STN
#define F367TER_PMC2_ACCU_TIME
#define F367TER_PMC2_CMDP_MN
#define F367TER_PMC2_SWAP

/* STATUS_ERR_DA */
#define R367TER_STATUS_ERR_DA
#define F367TER_COM_USEGAINTRK
#define F367TER_COM_AGCLOCK
#define F367TER_AUT_AGCLOCK
#define F367TER_MIN_ERR_X_LSB

/* DIG_AGC_R */
#define R367TER_DIG_AGC_R
#define F367TER_COM_SOFT_RSTN
#define F367TER_COM_AGC_ON
#define F367TER_COM_EARLY
#define F367TER_AUT_SOFT_RESETN
#define F367TER_AUT_AGC_ON
#define F367TER_AUT_EARLY
#define F367TER_AUT_ROT_EN
#define F367TER_LOCK_SOFT_RESETN

/* COMAGC_TARMSB */
#define R367TER_COMAGC_TARMSB
#define F367TER_COM_AGC_TARGET_MSB

/* COM_AGC_TAR_ENMODE */
#define R367TER_COM_AGC_TAR_ENMODE
#define F367TER_COM_AGC_TARGET_LSB
#define F367TER_COM_ENMODE

/* COM_AGC_CFG */
#define R367TER_COM_AGC_CFG
#define F367TER_COM_N
#define F367TER_COM_STABMODE
#define F367TER_ERR_SEL

/* COM_AGC_GAIN1 */
#define R367TER_COM_AGC_GAIN1
#define F367TER_COM_GAIN1aCK
#define F367TER_COM_GAIN1TRK

/* AUT_AGC_TARGETMSB */
#define R367TER_AUT_AGC_TARGETMSB
#define F367TER_AUT_AGC_TARGET_MSB

/* LOCK_DET_MSB */
#define R367TER_LOCK_DET_MSB
#define F367TER_LOCK_DETECT_MSB

/* AGCTAR_LOCK_LSBS */
#define R367TER_AGCTAR_LOCK_LSBS
#define F367TER_AUT_AGC_TARGET_LSB
#define F367TER_LOCK_DETECT_LSB

/* AUT_GAIN_EN */
#define R367TER_AUT_GAIN_EN
#define F367TER_AUT_ENMODE
#define F367TER_AUT_GAIN2

/* AUT_CFG */
#define R367TER_AUT_CFG
#define F367TER_AUT_N
#define F367TER_INT_CHOICE
#define F367TER_INT_LOAD

/* LOCKN */
#define R367TER_LOCKN
#define F367TER_LOCK_N
#define F367TER_SEL_IQNTAR
#define F367TER_LOCK_DETECT_CHOICE

/* INT_X_3 */
#define R367TER_INT_X_3
#define F367TER_INT_X3

/* INT_X_2 */
#define R367TER_INT_X_2
#define F367TER_INT_X2

/* INT_X_1 */
#define R367TER_INT_X_1
#define F367TER_INT_X1

/* INT_X_0 */
#define R367TER_INT_X_0
#define F367TER_INT_X0

/* MIN_ERRX_MSB */
#define R367TER_MIN_ERRX_MSB
#define F367TER_MIN_ERR_X_MSB

/* COR_CTL */
#define R367TER_COR_CTL
#define F367TER_CORE_ACTIVE
#define F367TER_HOLD
#define F367TER_CORE_STATE_CTL

/* COR_STAT */
#define R367TER_COR_STAT
#define F367TER_SCATT_LOCKED
#define F367TER_TPS_LOCKED
#define F367TER_SYR_LOCKED_COR
#define F367TER_AGC_LOCKED_STAT
#define F367TER_CORE_STATE_STAT

/* COR_INTEN */
#define R367TER_COR_INTEN
#define F367TER_INTEN
#define F367TER_INTEN_SYR
#define F367TER_INTEN_FFT
#define F367TER_INTEN_AGC
#define F367TER_INTEN_TPS1
#define F367TER_INTEN_TPS2
#define F367TER_INTEN_TPS3

/* COR_INTSTAT */
#define R367TER_COR_INTSTAT
#define F367TER_INTSTAT_SYR
#define F367TER_INTSTAT_FFT
#define F367TER_INTSAT_AGC
#define F367TER_INTSTAT_TPS1
#define F367TER_INTSTAT_TPS2
#define F367TER_INTSTAT_TPS3

/* COR_MODEGUARD */
#define R367TER_COR_MODEGUARD
#define F367TER_FORCE
#define F367TER_MODE
#define F367TER_GUARD

/* AGC_CTL */
#define R367TER_AGC_CTL
#define F367TER_AGC_TIMING_FACTOR
#define F367TER_AGC_LAST
#define F367TER_AGC_GAIN
#define F367TER_AGC_NEG
#define F367TER_AGC_SET

/* AGC_MANUAL1 */
#define R367TER_AGC_MANUAL1
#define F367TER_AGC_VAL_LO

/* AGC_MANUAL2 */
#define R367TER_AGC_MANUAL2
#define F367TER_AGC_VAL_HI

/* AGC_TARG */
#define R367TER_AGC_TARG
#define F367TER_AGC_TARGET

/* AGC_GAIN1 */
#define R367TER_AGC_GAIN1
#define F367TER_AGC_GAIN_LO

/* AGC_GAIN2 */
#define R367TER_AGC_GAIN2
#define F367TER_AGC_LOCKED_GAIN2
#define F367TER_AGC_GAIN_HI

/* RESERVED_1 */
#define R367TER_RESERVED_1
#define F367TER_RESERVED1

/* RESERVED_2 */
#define R367TER_RESERVED_2
#define F367TER_RESERVED2

/* RESERVED_3 */
#define R367TER_RESERVED_3
#define F367TER_RESERVED3

/* CAS_CTL */
#define R367TER_CAS_CTL
#define F367TER_CCS_ENABLE
#define F367TER_ACS_DISABLE
#define F367TER_DAGC_DIS
#define F367TER_DAGC_GAIN
#define F367TER_CCSMU

/* CAS_FREQ */
#define R367TER_CAS_FREQ
#define F367TER_CCS_FREQ

/* CAS_DAGCGAIN */
#define R367TER_CAS_DAGCGAIN
#define F367TER_CAS_DAGC_GAIN

/* SYR_CTL */
#define R367TER_SYR_CTL
#define F367TER_SICTH_ENABLE
#define F367TER_LONG_ECHO
#define F367TER_AUTO_LE_EN
#define F367TER_SYR_BYPASS
#define F367TER_SYR_TR_DIS

/* SYR_STAT */
#define R367TER_SYR_STAT
#define F367TER_SYR_LOCKED_STAT
#define F367TER_SYR_MODE
#define F367TER_SYR_GUARD

/* SYR_NCO1 */
#define R367TER_SYR_NCO1
#define F367TER_SYR_NCO_LO

/* SYR_NCO2 */
#define R367TER_SYR_NCO2
#define F367TER_SYR_NCO_HI

/* SYR_OFFSET1 */
#define R367TER_SYR_OFFSET1
#define F367TER_SYR_OFFSET_LO

/* SYR_OFFSET2 */
#define R367TER_SYR_OFFSET2
#define F367TER_SYR_OFFSET_HI

/* FFT_CTL */
#define R367TER_FFT_CTL
#define F367TER_SHIFT_FFT_TRIG
#define F367TER_FFT_TRIGGER
#define F367TER_FFT_MANUAL
#define F367TER_IFFT_MODE

/* SCR_CTL */
#define R367TER_SCR_CTL
#define F367TER_SYRADJDECAY
#define F367TER_SCR_CPEDIS
#define F367TER_SCR_DIS

/* PPM_CTL1 */
#define R367TER_PPM_CTL1
#define F367TER_PPM_MAXFREQ
#define F367TER_PPM_MAXTIM
#define F367TER_PPM_INVSEL
#define F367TER_PPM_SCATDIS
#define F367TER_PPM_BYP

/* TRL_CTL */
#define R367TER_TRL_CTL
#define F367TER_TRL_NOMRATE_LSB
#define F367TER_TRL_GAIN_FACTOR
#define F367TER_TRL_LOOPGAIN

/* TRL_NOMRATE1 */
#define R367TER_TRL_NOMRATE1
#define F367TER_TRL_NOMRATE_LO

/* TRL_NOMRATE2 */
#define R367TER_TRL_NOMRATE2
#define F367TER_TRL_NOMRATE_HI

/* TRL_TIME1 */
#define R367TER_TRL_TIME1
#define F367TER_TRL_TOFFSET_LO

/* TRL_TIME2 */
#define R367TER_TRL_TIME2
#define F367TER_TRL_TOFFSET_HI

/* CRL_CTL */
#define R367TER_CRL_CTL
#define F367TER_CRL_DIS
#define F367TER_CRL_GAIN_FACTOR
#define F367TER_CRL_LOOPGAIN

/* CRL_FREQ1 */
#define R367TER_CRL_FREQ1
#define F367TER_CRL_FOFFSET_LO

/* CRL_FREQ2 */
#define R367TER_CRL_FREQ2
#define F367TER_CRL_FOFFSET_HI

/* CRL_FREQ3 */
#define R367TER_CRL_FREQ3
#define F367TER_CRL_FOFFSET_VHI

/* TPS_SFRAME_CTL */
#define R367TER_TPS_SFRAME_CTL
#define F367TER_TPS_SFRAME_SYNC

/* CHC_SNR */
#define R367TER_CHC_SNR
#define F367TER_CHCSNR

/* BDI_CTL */
#define R367TER_BDI_CTL
#define F367TER_BDI_LPSEL
#define F367TER_BDI_SERIAL

/* DMP_CTL */
#define R367TER_DMP_CTL
#define F367TER_DMP_SCALING_FACTOR
#define F367TER_DMP_SDDIS

/* TPS_RCVD1 */
#define R367TER_TPS_RCVD1
#define F367TER_TPS_CHANGE
#define F367TER_BCH_OK
#define F367TER_TPS_SYNC
#define F367TER_TPS_FRAME

/* TPS_RCVD2 */
#define R367TER_TPS_RCVD2
#define F367TER_TPS_HIERMODE
#define F367TER_TPS_CONST

/* TPS_RCVD3 */
#define R367TER_TPS_RCVD3
#define F367TER_TPS_LPCODE
#define F367TER_TPS_HPCODE

/* TPS_RCVD4 */
#define R367TER_TPS_RCVD4
#define F367TER_TPS_GUARD
#define F367TER_TPS_MODE

/* TPS_ID_CELL1 */
#define R367TER_TPS_ID_CELL1
#define F367TER_TPS_ID_CELL_LO

/* TPS_ID_CELL2 */
#define R367TER_TPS_ID_CELL2
#define F367TER_TPS_ID_CELL_HI

/* TPS_RCVD5_SET1 */
#define R367TER_TPS_RCVD5_SET1
#define F367TER_TPS_NA
#define F367TER_TPS_SETFRAME

/* TPS_SET2 */
#define R367TER_TPS_SET2
#define F367TER_TPS_SETHIERMODE
#define F367TER_TPS_SETCONST

/* TPS_SET3 */
#define R367TER_TPS_SET3
#define F367TER_TPS_SETLPCODE
#define F367TER_TPS_SETHPCODE

/* TPS_CTL */
#define R367TER_TPS_CTL
#define F367TER_TPS_IMM
#define F367TER_TPS_BCHDIS
#define F367TER_TPS_UPDDIS

/* CTL_FFTOSNUM */
#define R367TER_CTL_FFTOSNUM
#define F367TER_SYMBOL_NUMBER

/* TESTSELECT */
#define R367TER_TESTSELECT
#define F367TER_TEST_SELECT

/* MSC_REV */
#define R367TER_MSC_REV
#define F367TER_REV_NUMBER

/* PIR_CTL */
#define R367TER_PIR_CTL
#define F367TER_FREEZE

/* SNR_CARRIER1 */
#define R367TER_SNR_CARRIER1
#define F367TER_SNR_CARRIER_LO

/* SNR_CARRIER2 */
#define R367TER_SNR_CARRIER2
#define F367TER_MEAN
#define F367TER_SNR_CARRIER_HI

/* PPM_CPAMP */
#define R367TER_PPM_CPAMP
#define F367TER_PPM_CPC

/* TSM_AP0 */
#define R367TER_TSM_AP0
#define F367TER_ADDRESS_BYTE_0

/* TSM_AP1 */
#define R367TER_TSM_AP1
#define F367TER_ADDRESS_BYTE_1

/* TSM_AP2 */
#define R367TER_TSM_AP2
#define F367TER_DATA_BYTE_0

/* TSM_AP3 */
#define R367TER_TSM_AP3
#define F367TER_DATA_BYTE_1

/* TSM_AP4 */
#define R367TER_TSM_AP4
#define F367TER_DATA_BYTE_2

/* TSM_AP5 */
#define R367TER_TSM_AP5
#define F367TER_DATA_BYTE_3

/* TSM_AP6 */
#define R367TER_TSM_AP6
#define F367TER_TSM_AP_6

/* TSM_AP7 */
#define R367TER_TSM_AP7
#define F367TER_MEM_SELECT_BYTE

/* TSTRES */
#define R367TER_TSTRES
#define F367TER_FRES_DISPLAY
#define F367TER_FRES_FIFO_AD
#define F367TER_FRESRS
#define F367TER_FRESACS
#define F367TER_FRESFEC
#define F367TER_FRES_PRIF
#define F367TER_FRESCORE

/* ANACTRL */
#define R367TER_ANACTRL
#define F367TER_BYPASS_XTAL
#define F367TER_BYPASS_PLLXN
#define F367TER_DIS_PAD_OSC
#define F367TER_STDBY_PLLXN

/* TSTBUS */
#define R367TER_TSTBUS
#define F367TER_TS_BYTE_CLK_INV
#define F367TER_CFG_IP
#define F367TER_CFG_TST

/* TSTRATE */
#define R367TER_TSTRATE
#define F367TER_FORCEPHA
#define F367TER_FNEWPHA
#define F367TER_FROT90
#define F367TER_FR

/* CONSTMODE */
#define R367TER_CONSTMODE
#define F367TER_TST_PRIF
#define F367TER_CAR_TYPE
#define F367TER_CONST_MODE

/* CONSTCARR1 */
#define R367TER_CONSTCARR1
#define F367TER_CONST_CARR_LO

/* CONSTCARR2 */
#define R367TER_CONSTCARR2
#define F367TER_CONST_CARR_HI

/* ICONSTEL */
#define R367TER_ICONSTEL
#define F367TER_PICONSTEL

/* QCONSTEL */
#define R367TER_QCONSTEL
#define F367TER_PQCONSTEL

/* TSTBISTRES0 */
#define R367TER_TSTBISTRES0
#define F367TER_BEND_PPM
#define F367TER_BBAD_PPM
#define F367TER_BEND_FFTW
#define F367TER_BBAD_FFTW
#define F367TER_BEND_FFT_BUF
#define F367TER_BBAD_FFT_BUF
#define F367TER_BEND_SYR
#define F367TER_BBAD_SYR

/* TSTBISTRES1 */
#define R367TER_TSTBISTRES1
#define F367TER_BEND_CHC_CP
#define F367TER_BBAD_CHC_CP
#define F367TER_BEND_CHCI
#define F367TER_BBAD_CHCI
#define F367TER_BEND_BDI
#define F367TER_BBAD_BDI
#define F367TER_BEND_SDI
#define F367TER_BBAD_SDI

/* TSTBISTRES2 */
#define R367TER_TSTBISTRES2
#define F367TER_BEND_CHC_INC
#define F367TER_BBAD_CHC_INC
#define F367TER_BEND_CHC_SPP
#define F367TER_BBAD_CHC_SPP
#define F367TER_BEND_CHC_CPP
#define F367TER_BBAD_CHC_CPP
#define F367TER_BEND_CHC_SP
#define F367TER_BBAD_CHC_SP

/* TSTBISTRES3 */
#define R367TER_TSTBISTRES3
#define F367TER_BEND_QAM
#define F367TER_BBAD_QAM
#define F367TER_BEND_SFEC_VIT
#define F367TER_BBAD_SFEC_VIT
#define F367TER_BEND_SFEC_DLINE
#define F367TER_BBAD_SFEC_DLINE
#define F367TER_BEND_SFEC_HW
#define F367TER_BBAD_SFEC_HW

/* RF_AGC1 */
#define R367TER_RF_AGC1
#define F367TER_RF_AGC1_LEVEL_HI

/* RF_AGC2 */
#define R367TER_RF_AGC2
#define F367TER_REF_ADGP
#define F367TER_STDBY_ADCGP
#define F367TER_CHANNEL_SEL
#define F367TER_RF_AGC1_LEVEL_LO

/* ANADIGCTRL */
#define R367TER_ANADIGCTRL
#define F367TER_SEL_CLKDEM
#define F367TER_EN_BUFFER_Q
#define F367TER_EN_BUFFER_I
#define F367TER_ADC_RIS_EGDE
#define F367TER_SGN_ADC
#define F367TER_SEL_AD12_SYNC

/* PLLMDIV */
#define R367TER_PLLMDIV
#define F367TER_PLL_MDIV

/* PLLNDIV */
#define R367TER_PLLNDIV
#define F367TER_PLL_NDIV

/* PLLSETUP */
#define R367TER_PLLSETUP
#define F367TER_PLL_PDIV
#define F367TER_PLL_KDIV

/* DUAL_AD12 */
#define R367TER_DUAL_AD12
#define F367TER_FS20M
#define F367TER_FS50M
#define F367TER_INMODe0
#define F367TER_POFFQ
#define F367TER_POFFI
#define F367TER_INMODE1

/* TSTBIST */
#define R367TER_TSTBIST
#define F367TER_TST_BYP_CLK
#define F367TER_TST_GCLKENA_STD
#define F367TER_TST_GCLKENA
#define F367TER_TST_MEMBIST

/* PAD_COMP_CTRL */
#define R367TER_PAD_COMP_CTRL
#define F367TER_COMPTQ
#define F367TER_COMPEN
#define F367TER_FREEZE2
#define F367TER_SLEEP_INHBT
#define F367TER_CHIP_SLEEP

/* PAD_COMP_WR */
#define R367TER_PAD_COMP_WR
#define F367TER_WR_ASRC

/* PAD_COMP_RD */
#define R367TER_PAD_COMP_RD
#define F367TER_COMPOK
#define F367TER_RD_ASRC

/* SYR_TARGET_FFTADJT_MSB */
#define R367TER_SYR_TARGET_FFTADJT_MSB
#define F367TER_SYR_START
#define F367TER_SYR_TARGET_FFTADJ_HI

/* SYR_TARGET_FFTADJT_LSB */
#define R367TER_SYR_TARGET_FFTADJT_LSB
#define F367TER_SYR_TARGET_FFTADJ_LO

/* SYR_TARGET_CHCADJT_MSB */
#define R367TER_SYR_TARGET_CHCADJT_MSB
#define F367TER_SYR_TARGET_CHCADJ_HI

/* SYR_TARGET_CHCADJT_LSB */
#define R367TER_SYR_TARGET_CHCADJT_LSB
#define F367TER_SYR_TARGET_CHCADJ_LO

/* SYR_FLAG */
#define R367TER_SYR_FLAG
#define F367TER_TRIG_FLG1
#define F367TER_TRIG_FLG0
#define F367TER_FFT_FLG1
#define F367TER_FFT_FLG0
#define F367TER_CHC_FLG1
#define F367TER_CHC_FLG0

/* CRL_TARGET1 */
#define R367TER_CRL_TARGET1
#define F367TER_CRL_START
#define F367TER_CRL_TARGET_VHI

/* CRL_TARGET2 */
#define R367TER_CRL_TARGET2
#define F367TER_CRL_TARGET_HI

/* CRL_TARGET3 */
#define R367TER_CRL_TARGET3
#define F367TER_CRL_TARGET_LO

/* CRL_TARGET4 */
#define R367TER_CRL_TARGET4
#define F367TER_CRL_TARGET_VLO

/* CRL_FLAG */
#define R367TER_CRL_FLAG
#define F367TER_CRL_FLAG1
#define F367TER_CRL_FLAG0

/* TRL_TARGET1 */
#define R367TER_TRL_TARGET1
#define F367TER_TRL_TARGET_HI

/* TRL_TARGET2 */
#define R367TER_TRL_TARGET2
#define F367TER_TRL_TARGET_LO

/* TRL_CHC */
#define R367TER_TRL_CHC
#define F367TER_TRL_START
#define F367TER_CHC_START
#define F367TER_TRL_FLAG1
#define F367TER_TRL_FLAG0

/* CHC_SNR_TARG */
#define R367TER_CHC_SNR_TARG
#define F367TER_CHC_SNR_TARGET

/* TOP_TRACK */
#define R367TER_TOP_TRACK
#define F367TER_TOP_START
#define F367TER_FIRST_FLAG
#define F367TER_TOP_FLAG1
#define F367TER_TOP_FLAG0
#define F367TER_CHC_FLAG1
#define F367TER_CHC_FLAG0

/* TRACKER_FREE1 */
#define R367TER_TRACKER_FREE1
#define F367TER_TRACKER_FREE_1

/* ERROR_CRL1 */
#define R367TER_ERROR_CRL1
#define F367TER_ERROR_CRL_VHI

/* ERROR_CRL2 */
#define R367TER_ERROR_CRL2
#define F367TER_ERROR_CRL_HI

/* ERROR_CRL3 */
#define R367TER_ERROR_CRL3
#define F367TER_ERROR_CRL_LOI

/* ERROR_CRL4 */
#define R367TER_ERROR_CRL4
#define F367TER_ERROR_CRL_VLO

/* DEC_NCO1 */
#define R367TER_DEC_NCO1
#define F367TER_DEC_NCO_VHI

/* DEC_NCO2 */
#define R367TER_DEC_NCO2
#define F367TER_DEC_NCO_HI

/* DEC_NCO3 */
#define R367TER_DEC_NCO3
#define F367TER_DEC_NCO_LO

/* SNR */
#define R367TER_SNR
#define F367TER_SNRATIO

/* SYR_FFTADJ1 */
#define R367TER_SYR_FFTADJ1
#define F367TER_SYR_FFTADJ_HI

/* SYR_FFTADJ2 */
#define R367TER_SYR_FFTADJ2
#define F367TER_SYR_FFTADJ_LO

/* SYR_CHCADJ1 */
#define R367TER_SYR_CHCADJ1
#define F367TER_SYR_CHCADJ_HI

/* SYR_CHCADJ2 */
#define R367TER_SYR_CHCADJ2
#define F367TER_SYR_CHCADJ_LO

/* SYR_OFF */
#define R367TER_SYR_OFF
#define F367TER_SYR_OFFSET

/* PPM_OFFSET1 */
#define R367TER_PPM_OFFSET1
#define F367TER_PPM_OFFSET_HI

/* PPM_OFFSET2 */
#define R367TER_PPM_OFFSET2
#define F367TER_PPM_OFFSET_LO

/* TRACKER_FREE2 */
#define R367TER_TRACKER_FREE2
#define F367TER_TRACKER_FREE_2

/* DEBG_LT10 */
#define R367TER_DEBG_LT10
#define F367TER_DEBUG_LT10

/* DEBG_LT11 */
#define R367TER_DEBG_LT11
#define F367TER_DEBUG_LT11

/* DEBG_LT12 */
#define R367TER_DEBG_LT12
#define F367TER_DEBUG_LT12

/* DEBG_LT13 */
#define R367TER_DEBG_LT13
#define F367TER_DEBUG_LT13

/* DEBG_LT14 */
#define R367TER_DEBG_LT14
#define F367TER_DEBUG_LT14

/* DEBG_LT15 */
#define R367TER_DEBG_LT15
#define F367TER_DEBUG_LT15

/* DEBG_LT16 */
#define R367TER_DEBG_LT16
#define F367TER_DEBUG_LT16

/* DEBG_LT17 */
#define R367TER_DEBG_LT17
#define F367TER_DEBUG_LT17

/* DEBG_LT18 */
#define R367TER_DEBG_LT18
#define F367TER_DEBUG_LT18

/* DEBG_LT19 */
#define R367TER_DEBG_LT19
#define F367TER_DEBUG_LT19

/* DEBG_LT1a */
#define R367TER_DEBG_LT1A
#define F367TER_DEBUG_LT1A

/* DEBG_LT1b */
#define R367TER_DEBG_LT1B
#define F367TER_DEBUG_LT1B

/* DEBG_LT1c */
#define R367TER_DEBG_LT1C
#define F367TER_DEBUG_LT1C

/* DEBG_LT1D */
#define R367TER_DEBG_LT1D
#define F367TER_DEBUG_LT1D

/* DEBG_LT1E */
#define R367TER_DEBG_LT1E
#define F367TER_DEBUG_LT1E

/* DEBG_LT1F */
#define R367TER_DEBG_LT1F
#define F367TER_DEBUG_LT1F

/* RCCFGH */
#define R367TER_RCCFGH
#define F367TER_TSRCFIFO_DVBCI
#define F367TER_TSRCFIFO_SERIAL
#define F367TER_TSRCFIFO_DISABLE
#define F367TER_TSFIFO_2TORC
#define F367TER_TSRCFIFO_HSGNLOUT
#define F367TER_TSRCFIFO_ERRMODE
#define F367TER_RCCFGH_0

/* RCCFGM */
#define R367TER_RCCFGM
#define F367TER_TSRCFIFO_MANSPEED
#define F367TER_TSRCFIFO_PERMDATA
#define F367TER_TSRCFIFO_NONEWSGNL
#define F367TER_RCBYTE_OVERSAMPLING
#define F367TER_TSRCFIFO_INVDATA

/* RCCFGL */
#define R367TER_RCCFGL
#define F367TER_TSRCFIFO_BCLKDEL1cK
#define F367TER_RCCFGL_5
#define F367TER_TSRCFIFO_DUTY50
#define F367TER_TSRCFIFO_NSGNL2dATA
#define F367TER_TSRCFIFO_DISSERMUX
#define F367TER_RCCFGL_1
#define F367TER_TSRCFIFO_STOPCKDIS

/* RCINSDELH */
#define R367TER_RCINSDELH
#define F367TER_TSRCDEL_SYNCBYTE
#define F367TER_TSRCDEL_XXHEADER
#define F367TER_TSRCDEL_BBHEADER
#define F367TER_TSRCDEL_DATAFIELD
#define F367TER_TSRCINSDEL_ISCR
#define F367TER_TSRCINSDEL_NPD
#define F367TER_TSRCINSDEL_RSPARITY
#define F367TER_TSRCINSDEL_CRC8

/* RCINSDELM */
#define R367TER_RCINSDELM
#define F367TER_TSRCINS_BBPADDING
#define F367TER_TSRCINS_BCHFEC
#define F367TER_TSRCINS_LDPCFEC
#define F367TER_TSRCINS_EMODCOD
#define F367TER_TSRCINS_TOKEN
#define F367TER_TSRCINS_XXXERR
#define F367TER_TSRCINS_MATYPE
#define F367TER_TSRCINS_UPL

/* RCINSDELL */
#define R367TER_RCINSDELL
#define F367TER_TSRCINS_DFL
#define F367TER_TSRCINS_SYNCD
#define F367TER_TSRCINS_BLOCLEN
#define F367TER_TSRCINS_SIGPCOUNT
#define F367TER_TSRCINS_FIFO
#define F367TER_TSRCINS_REALPACK
#define F367TER_TSRCINS_TSCONFIG
#define F367TER_TSRCINS_LATENCY

/* RCSTATUS */
#define R367TER_RCSTATUS
#define F367TER_TSRCFIFO_LINEOK
#define F367TER_TSRCFIFO_ERROR
#define F367TER_TSRCFIFO_DATA7
#define F367TER_RCSTATUS_4
#define F367TER_TSRCFIFO_DEMODSEL
#define F367TER_TSRC1FIFOSPEED_STORE
#define F367TER_RCSTATUS_1
#define F367TER_TSRCSERIAL_IMPOSSIBLE

/* RCSPEED */
#define R367TER_RCSPEED
#define F367TER_TSRCFIFO_OUTSPEED

/* RCDEBUGM */
#define R367TER_RCDEBUGM
#define F367TER_SD_UNSYNC
#define F367TER_ULFLOCK_DETECTM
#define F367TER_SUL_SELECTOS
#define F367TER_DILUL_NOSCRBLE
#define F367TER_NUL_SCRB
#define F367TER_UL_SCRB
#define F367TER_SCRAULBAD
#define F367TER_SCRAUL_UNSYNC

/* RCDEBUGL */
#define R367TER_RCDEBUGL
#define F367TER_RS_ERR
#define F367TER_LLFLOCK_DETECTM
#define F367TER_NOT_SUL_SELECTOS
#define F367TER_DILLL_NOSCRBLE
#define F367TER_NLL_SCRB
#define F367TER_LL_SCRB
#define F367TER_SCRALLBAD
#define F367TER_SCRALL_UNSYNC

/* RCOBSCFG */
#define R367TER_RCOBSCFG
#define F367TER_TSRCFIFO_OBSCFG

/* RCOBSM */
#define R367TER_RCOBSM
#define F367TER_TSRCFIFO_OBSDATA_HI

/* RCOBSL */
#define R367TER_RCOBSL
#define F367TER_TSRCFIFO_OBSDATA_LO

/* RCFECSPY */
#define R367TER_RCFECSPY
#define F367TER_SPYRC_ENABLE
#define F367TER_RCNO_SYNCBYTE
#define F367TER_RCSERIAL_MODE
#define F367TER_RCUNUSUAL_PACKET
#define F367TER_BERRCMETER_DATAMODE
#define F367TER_BERRCMETER_LMODE
#define F367TER_BERRCMETER_RESET

/* RCFSPYCFG */
#define R367TER_RCFSPYCFG
#define F367TER_FECSPYRC_INPUT
#define F367TER_RCRST_ON_ERROR
#define F367TER_RCONE_SHOT
#define F367TER_RCI2C_MODE
#define F367TER_SPYRC_HSTERESIS

/* RCFSPYDATA */
#define R367TER_RCFSPYDATA
#define F367TER_SPYRC_STUFFING
#define F367TER_RCNOERR_PKTJITTER
#define F367TER_SPYRC_CNULLPKT
#define F367TER_SPYRC_OUTDATA_MODE

/* RCFSPYOUT */
#define R367TER_RCFSPYOUT
#define F367TER_FSPYRC_DIRECT
#define F367TER_RCFSPYOUT_6
#define F367TER_SPYRC_OUTDATA_BUS
#define F367TER_RCSTUFF_MODE

/* RCFSTATUS */
#define R367TER_RCFSTATUS
#define F367TER_SPYRC_ENDSIM
#define F367TER_RCVALID_SIM
#define F367TER_RCFOUND_SIGNAL
#define F367TER_RCDSS_SYNCBYTE
#define F367TER_RCRESULT_STATE

/* RCFGOODPACK */
#define R367TER_RCFGOODPACK
#define F367TER_RCGOOD_PACKET

/* RCFPACKCNT */
#define R367TER_RCFPACKCNT
#define F367TER_RCPACKET_COUNTER

/* RCFSPYMISC */
#define R367TER_RCFSPYMISC
#define F367TER_RCLABEL_COUNTER

/* RCFBERCPT4 */
#define R367TER_RCFBERCPT4
#define F367TER_FBERRCMETER_CPT_MMMMSB

/* RCFBERCPT3 */
#define R367TER_RCFBERCPT3
#define F367TER_FBERRCMETER_CPT_MMMSB

/* RCFBERCPT2 */
#define R367TER_RCFBERCPT2
#define F367TER_FBERRCMETER_CPT_MMSB

/* RCFBERCPT1 */
#define R367TER_RCFBERCPT1
#define F367TER_FBERRCMETER_CPT_MSB

/* RCFBERCPT0 */
#define R367TER_RCFBERCPT0
#define F367TER_FBERRCMETER_CPT_LSB

/* RCFBERERR2 */
#define R367TER_RCFBERERR2
#define F367TER_FBERRCMETER_ERR_HI

/* RCFBERERR1 */
#define R367TER_RCFBERERR1
#define F367TER_FBERRCMETER_ERR

/* RCFBERERR0 */
#define R367TER_RCFBERERR0
#define F367TER_FBERRCMETER_ERR_LO

/* RCFSTATESM */
#define R367TER_RCFSTATESM
#define F367TER_RCRSTATE_F
#define F367TER_RCRSTATE_E
#define F367TER_RCRSTATE_D
#define F367TER_RCRSTATE_C
#define F367TER_RCRSTATE_B
#define F367TER_RCRSTATE_A
#define F367TER_RCRSTATE_9
#define F367TER_RCRSTATE_8

/* RCFSTATESL */
#define R367TER_RCFSTATESL
#define F367TER_RCRSTATE_7
#define F367TER_RCRSTATE_6
#define F367TER_RCRSTATE_5
#define F367TER_RCRSTATE_4
#define F367TER_RCRSTATE_3
#define F367TER_RCRSTATE_2
#define F367TER_RCRSTATE_1
#define F367TER_RCRSTATE_0

/* RCFSPYBER */
#define R367TER_RCFSPYBER
#define F367TER_RCFSPYBER_7
#define F367TER_SPYRCOBS_XORREAD
#define F367TER_FSPYRCBER_OBSMODE
#define F367TER_FSPYRCBER_SYNCBYT
#define F367TER_FSPYRCBER_UNSYNC
#define F367TER_FSPYRCBER_CTIME

/* RCFSPYDISTM */
#define R367TER_RCFSPYDISTM
#define F367TER_RCPKTTIME_DISTANCE_HI

/* RCFSPYDISTL */
#define R367TER_RCFSPYDISTL
#define F367TER_RCPKTTIME_DISTANCE_LO

/* RCFSPYOBS7 */
#define R367TER_RCFSPYOBS7
#define F367TER_RCSPYOBS_SPYFAIL
#define F367TER_RCSPYOBS_SPYFAIL1
#define F367TER_RCSPYOBS_ERROR
#define F367TER_RCSPYOBS_STROUT
#define F367TER_RCSPYOBS_RESULTSTATE1

/* RCFSPYOBS6 */
#define R367TER_RCFSPYOBS6
#define F367TER_RCSPYOBS_RESULTSTATe0
#define F367TER_RCSPYOBS_RESULTSTATEM1

/* RCFSPYOBS5 */
#define R367TER_RCFSPYOBS5
#define F367TER_RCSPYOBS_BYTEOFPACKET1

/* RCFSPYOBS4 */
#define R367TER_RCFSPYOBS4
#define F367TER_RCSPYOBS_BYTEVALUE1

/* RCFSPYOBS3 */
#define R367TER_RCFSPYOBS3
#define F367TER_RCSPYOBS_DATA1

/* RCFSPYOBS2 */
#define R367TER_RCFSPYOBS2
#define F367TER_RCSPYOBS_DATa0

/* RCFSPYOBS1 */
#define R367TER_RCFSPYOBS1
#define F367TER_RCSPYOBS_DATAM1

/* RCFSPYOBS0 */
#define R367TER_RCFSPYOBS0
#define F367TER_RCSPYOBS_DATAM2

/* TSGENERAL */
#define R367TER_TSGENERAL
#define F367TER_TSGENERAL_7
#define F367TER_TSGENERAL_6
#define F367TER_TSFIFO_BCLK1aLL
#define F367TER_TSGENERAL_4
#define F367TER_MUXSTREAM_OUTMODE
#define F367TER_TSFIFO_PERMPARAL
#define F367TER_RST_REEDSOLO

/* RC1SPEED */
#define R367TER_RC1SPEED
#define F367TER_TSRCFIFO1_OUTSPEED

/* TSGSTATUS */
#define R367TER_TSGSTATUS
#define F367TER_TSGSTATUS_7
#define F367TER_TSGSTATUS_6
#define F367TER_RSMEM_FULL
#define F367TER_RS_MULTCALC
#define F367TER_RSIN_OVERTIME
#define F367TER_TSFIFO3_DEMODSEL
#define F367TER_TSFIFO2_DEMODSEL
#define F367TER_TSFIFO1_DEMODSEL


/* FECM */
#define R367TER_FECM
#define F367TER_DSS_DVB
#define F367TER_DEMOD_BYPASS
#define F367TER_CMP_SLOWMODE
#define F367TER_DSS_SRCH
#define F367TER_FECM_3
#define F367TER_DIFF_MODEVIT
#define F367TER_SYNCVIT
#define F367TER_I2CSYM

/* VTH12 */
#define R367TER_VTH12
#define F367TER_VTH_12

/* VTH23 */
#define R367TER_VTH23
#define F367TER_VTH_23

/* VTH34 */
#define R367TER_VTH34
#define F367TER_VTH_34

/* VTH56 */
#define R367TER_VTH56
#define F367TER_VTH_56

/* VTH67 */
#define R367TER_VTH67
#define F367TER_VTH_67

/* VTH78 */
#define R367TER_VTH78
#define F367TER_VTH_78

/* VITCURPUN */
#define R367TER_VITCURPUN
#define F367TER_VIT_MAPPING
#define F367TER_VIT_CURPUN

/* VERROR */
#define R367TER_VERROR
#define F367TER_REGERR_VIT

/* PRVIT */
#define R367TER_PRVIT
#define F367TER_PRVIT_7
#define F367TER_DIS_VTHLOCK
#define F367TER_E7_8VIT
#define F367TER_E6_7VIT
#define F367TER_E5_6VIT
#define F367TER_E3_4VIT
#define F367TER_E2_3VIT
#define F367TER_E1_2VIT

/* VAVSRVIT */
#define R367TER_VAVSRVIT
#define F367TER_AMVIT
#define F367TER_FROZENVIT
#define F367TER_SNVIT
#define F367TER_TOVVIT
#define F367TER_HYPVIT

/* VSTATUSVIT */
#define R367TER_VSTATUSVIT
#define F367TER_VITERBI_ON
#define F367TER_END_LOOPVIT
#define F367TER_VITERBI_DEPRF
#define F367TER_PRFVIT
#define F367TER_LOCKEDVIT
#define F367TER_VITERBI_DELOCK
#define F367TER_VIT_DEMODSEL
#define F367TER_VITERBI_COMPOUT

/* VTHINUSE */
#define R367TER_VTHINUSE
#define F367TER_VIT_INUSE

/* KDIV12 */
#define R367TER_KDIV12
#define F367TER_KDIV12_MANUAL
#define F367TER_K_DIVIDER_12

/* KDIV23 */
#define R367TER_KDIV23
#define F367TER_KDIV23_MANUAL
#define F367TER_K_DIVIDER_23

/* KDIV34 */
#define R367TER_KDIV34
#define F367TER_KDIV34_MANUAL
#define F367TER_K_DIVIDER_34

/* KDIV56 */
#define R367TER_KDIV56
#define F367TER_KDIV56_MANUAL
#define F367TER_K_DIVIDER_56

/* KDIV67 */
#define R367TER_KDIV67
#define F367TER_KDIV67_MANUAL
#define F367TER_K_DIVIDER_67

/* KDIV78 */
#define R367TER_KDIV78
#define F367TER_KDIV78_MANUAL
#define F367TER_K_DIVIDER_78

/* SIGPOWER */
#define R367TER_SIGPOWER
#define F367TER_SIGPOWER_MANUAL
#define F367TER_SIG_POWER

/* DEMAPVIT */
#define R367TER_DEMAPVIT
#define F367TER_DEMAPVIT_7
#define F367TER_K_DIVIDER_VIT

/* VITSCALE */
#define R367TER_VITSCALE
#define F367TER_NVTH_NOSRANGE
#define F367TER_VERROR_MAXMODE
#define F367TER_KDIV_MODE
#define F367TER_NSLOWSN_LOCKED
#define F367TER_DELOCK_PRFLOSS
#define F367TER_DIS_RSFLOCK
#define F367TER_VITSCALE_0

/* FFEC1PRG */
#define R367TER_FFEC1PRG
#define F367TER_FDSS_DVB
#define F367TER_FDSS_SRCH
#define F367TER_FFECPROG_5
#define F367TER_FFECPROG_4
#define F367TER_FFECPROG_3
#define F367TER_FFECPROG_2
#define F367TER_FTS1_DISABLE
#define F367TER_FTS2_DISABLE

/* FVITCURPUN */
#define R367TER_FVITCURPUN
#define F367TER_FVIT_MAPPING
#define F367TER_FVIT_CURPUN

/* FVERROR */
#define R367TER_FVERROR
#define F367TER_FREGERR_VIT

/* FVSTATUSVIT */
#define R367TER_FVSTATUSVIT
#define F367TER_FVITERBI_ON
#define F367TER_F1END_LOOPVIT
#define F367TER_FVITERBI_DEPRF
#define F367TER_FPRFVIT
#define F367TER_FLOCKEDVIT
#define F367TER_FVITERBI_DELOCK
#define F367TER_FVIT_DEMODSEL
#define F367TER_FVITERBI_COMPOUT

/* DEBUG_LT1 */
#define R367TER_DEBUG_LT1
#define F367TER_DBG_LT1

/* DEBUG_LT2 */
#define R367TER_DEBUG_LT2
#define F367TER_DBG_LT2

/* DEBUG_LT3 */
#define R367TER_DEBUG_LT3
#define F367TER_DBG_LT3

/*	TSTSFMET */
#define R367TER_TSTSFMET
#define F367TER_TSTSFEC_METRIQUES

/*	SELOUT */
#define R367TER_SELOUT
#define F367TER_EN_SYNC
#define F367TER_EN_TBUSDEMAP
#define F367TER_SELOUT_5
#define F367TER_SELOUT_4
#define F367TER_TSTSYNCHRO_MODE

/*	TSYNC */
#define R367TER_TSYNC
#define F367TER_CURPUN_INCMODE
#define F367TER_CERR_TSTMODE
#define F367TER_SHIFTSOF_MODE
#define F367TER_SLOWPHA_MODE
#define F367TER_PXX_BYPALL
#define F367TER_FROTA45_FIRST
#define F367TER_TST_BCHERROR

/*	TSTERR */
#define R367TER_TSTERR
#define F367TER_TST_LONGPKT
#define F367TER_TST_ISSYION
#define F367TER_TST_NPDON
#define F367TER_TSTERR_4
#define F367TER_TRACEBACK_MODE
#define F367TER_TST_RSPARITY
#define F367TER_METRIQUE_MODE

/*	TSFSYNC */
#define R367TER_TSFSYNC
#define F367TER_EN_SFECSYNC
#define F367TER_EN_SFECDEMAP
#define F367TER_SFCERR_TSTMODE
#define F367TER_SFECPXX_BYPALL
#define F367TER_SFECTSTSYNCHRO_MODE

/*	TSTSFERR */
#define R367TER_TSTSFERR
#define F367TER_TSTSTERR_7
#define F367TER_TSTSTERR_6
#define F367TER_TSTSTERR_5
#define F367TER_TSTSTERR_4
#define F367TER_SFECTRACEBACK_MODE
#define F367TER_SFEC_NCONVPROG
#define F367TER_SFECMETRIQUE_MODE

/*	TSTTSSF1 */
#define R367TER_TSTTSSF1
#define F367TER_TSTERSSF
#define F367TER_TSTTSSFEN
#define F367TER_SFEC_OUTMODE
#define F367TER_XLSF_NOFTHRESHOLD
#define F367TER_TSTTSSF_STACKSEL

/*	TSTTSSF2 */
#define R367TER_TSTTSSF2
#define F367TER_DILSF_DBBHEADER
#define F367TER_TSTTSSF_DISBUG
#define F367TER_TSTTSSF_NOBADSTART
#define F367TER_TSTTSSF_SELECT

/*	TSTTSSF3 */
#define R367TER_TSTTSSF3
#define F367TER_TSTTSSF3_7
#define F367TER_TSTTSSF3_6
#define F367TER_TSTTSSF3_5
#define F367TER_TSTTSSF3_4
#define F367TER_TSTTSSF3_3
#define F367TER_TSTTSSF3_2
#define F367TER_TSTTSSF3_1
#define F367TER_DISSF_CLKENABLE

/*	TSTTS1 */
#define R367TER_TSTTS1
#define F367TER_TSTERS
#define F367TER_TSFIFO_DSSSYNCB
#define F367TER_TSTTS_FSPYBEFRS
#define F367TER_NFORCE_SYNCBYTE
#define F367TER_XL_NOFTHRESHOLD
#define F367TER_TSTTS_FRFORCEPKT
#define F367TER_DESCR_NOTAUTO
#define F367TER_TSTTSEN

/*	TSTTS2 */
#define R367TER_TSTTS2
#define F367TER_DIL_DBBHEADER
#define F367TER_TSTTS_NOBADXXX
#define F367TER_TSFIFO_DELSPEEDUP
#define F367TER_TSTTS_SELECT

/*	TSTTS3 */
#define R367TER_TSTTS3
#define F367TER_TSTTS_NOPKTGAIN
#define F367TER_TSTTS_NOPKTENE
#define F367TER_TSTTS_ISOLATION
#define F367TER_TSTTS_DISBUG
#define F367TER_TSTTS_NOBADSTART
#define F367TER_TSTTS_STACKSEL

/*	TSTTS4 */
#define R367TER_TSTTS4
#define F367TER_TSTTS4_7
#define F367TER_TSTTS4_6
#define F367TER_TSTTS4_5
#define F367TER_TSTTS_DISDSTATE
#define F367TER_TSTTS_FASTNOSYNC
#define F367TER_EXT_FECSPYIN
#define F367TER_TSTTS_NODPZERO
#define F367TER_TSTTS_NODIV3

/*	TSTTSRC */
#define R367TER_TSTTSRC
#define F367TER_TSTTSRC_7
#define F367TER_TSRCFIFO_DSSSYNCB
#define F367TER_TSRCFIFO_DPUNACTIVE
#define F367TER_TSRCFIFO_DELSPEEDUP
#define F367TER_TSTTSRC_NODIV3
#define F367TER_TSTTSRC_FRFORCEPKT
#define F367TER_SAT25_SDDORIGINE
#define F367TER_TSTTSRC_INACTIVE

/*	TSTTSRS */
#define R367TER_TSTTSRS
#define F367TER_TSTTSRS_7
#define F367TER_TSTTSRS_6
#define F367TER_TSTTSRS_5
#define F367TER_TSTTSRS_4
#define F367TER_TSTTSRS_3
#define F367TER_TSTTSRS_2
#define F367TER_TSTRS_DISRS2
#define F367TER_TSTRS_DISRS1

/* TSSTATEM */
#define R367TER_TSSTATEM
#define F367TER_TSDIL_ON
#define F367TER_TSSKIPRS_ON
#define F367TER_TSRS_ON
#define F367TER_TSDESCRAMB_ON
#define F367TER_TSFRAME_MODE
#define F367TER_TS_DISABLE
#define F367TER_TSACM_MODE
#define F367TER_TSOUT_NOSYNC

/* TSSTATEL */
#define R367TER_TSSTATEL
#define F367TER_TSNOSYNCBYTE
#define F367TER_TSPARITY_ON
#define F367TER_TSSYNCOUTRS_ON
#define F367TER_TSDVBS2_MODE
#define F367TER_TSISSYI_ON
#define F367TER_TSNPD_ON
#define F367TER_TSCRC8_ON
#define F367TER_TSDSS_PACKET

/* TSCFGH */
#define R367TER_TSCFGH
#define F367TER_TSFIFO_DVBCI
#define F367TER_TSFIFO_SERIAL
#define F367TER_TSFIFO_TEIUPDATE
#define F367TER_TSFIFO_DUTY50
#define F367TER_TSFIFO_HSGNLOUT
#define F367TER_TSFIFO_ERRMODE
#define F367TER_RST_HWARE

/* TSCFGM */
#define R367TER_TSCFGM
#define F367TER_TSFIFO_MANSPEED
#define F367TER_TSFIFO_PERMDATA
#define F367TER_TSFIFO_NONEWSGNL
#define F367TER_TSFIFO_BITSPEED
#define F367TER_NPD_SPECDVBS2
#define F367TER_TSFIFO_STOPCKDIS
#define F367TER_TSFIFO_INVDATA

/* TSCFGL */
#define R367TER_TSCFGL
#define F367TER_TSFIFO_BCLKDEL1cK
#define F367TER_BCHERROR_MODE
#define F367TER_TSFIFO_NSGNL2dATA
#define F367TER_TSFIFO_EMBINDVB
#define F367TER_TSFIFO_DPUNACT
#define F367TER_TSFIFO_NPDOFF

/* TSSYNC */
#define R367TER_TSSYNC
#define F367TER_TSFIFO_PERMUTE
#define F367TER_TSFIFO_FISCR3B
#define F367TER_TSFIFO_SYNCMODE
#define F367TER_TSFIFO_SYNCSEL

/* TSINSDELH */
#define R367TER_TSINSDELH
#define F367TER_TSDEL_SYNCBYTE
#define F367TER_TSDEL_XXHEADER
#define F367TER_TSDEL_BBHEADER
#define F367TER_TSDEL_DATAFIELD
#define F367TER_TSINSDEL_ISCR
#define F367TER_TSINSDEL_NPD
#define F367TER_TSINSDEL_RSPARITY
#define F367TER_TSINSDEL_CRC8

/* TSINSDELM */
#define R367TER_TSINSDELM
#define F367TER_TSINS_BBPADDING
#define F367TER_TSINS_BCHFEC
#define F367TER_TSINS_LDPCFEC
#define F367TER_TSINS_EMODCOD
#define F367TER_TSINS_TOKEN
#define F367TER_TSINS_XXXERR
#define F367TER_TSINS_MATYPE
#define F367TER_TSINS_UPL

/* TSINSDELL */
#define R367TER_TSINSDELL
#define F367TER_TSINS_DFL
#define F367TER_TSINS_SYNCD
#define F367TER_TSINS_BLOCLEN
#define F367TER_TSINS_SIGPCOUNT
#define F367TER_TSINS_FIFO
#define F367TER_TSINS_REALPACK
#define F367TER_TSINS_TSCONFIG
#define F367TER_TSINS_LATENCY

/* TSDIVN */
#define R367TER_TSDIVN
#define F367TER_TSFIFO_LOWSPEED
#define F367TER_BYTE_OVERSAMPLING
#define F367TER_TSMANUAL_PACKETNBR

/* TSDIVPM */
#define R367TER_TSDIVPM
#define F367TER_TSMANUAL_P_HI

/* TSDIVPL */
#define R367TER_TSDIVPL
#define F367TER_TSMANUAL_P_LO

/* TSDIVQM */
#define R367TER_TSDIVQM
#define F367TER_TSMANUAL_Q_HI

/* TSDIVQL */
#define R367TER_TSDIVQL
#define F367TER_TSMANUAL_Q_LO

/* TSDILSTKM */
#define R367TER_TSDILSTKM
#define F367TER_TSFIFO_DILSTK_HI

/* TSDILSTKL */
#define R367TER_TSDILSTKL
#define F367TER_TSFIFO_DILSTK_LO

/* TSSPEED */
#define R367TER_TSSPEED
#define F367TER_TSFIFO_OUTSPEED

/* TSSTATUS */
#define R367TER_TSSTATUS
#define F367TER_TSFIFO_LINEOK
#define F367TER_TSFIFO_ERROR
#define F367TER_TSFIFO_DATA7
#define F367TER_TSFIFO_NOSYNC
#define F367TER_ISCR_INITIALIZED
#define F367TER_ISCR_UPDATED
#define F367TER_SOFFIFO_UNREGUL
#define F367TER_DIL_READY

/* TSSTATUS2 */
#define R367TER_TSSTATUS2
#define F367TER_TSFIFO_DEMODSEL
#define F367TER_TSFIFOSPEED_STORE
#define F367TER_DILXX_RESET
#define F367TER_TSSERIAL_IMPOSSIBLE
#define F367TER_TSFIFO_UNDERSPEED
#define F367TER_BITSPEED_EVENT
#define F367TER_UL_SCRAMBDETECT
#define F367TER_ULDTV67_FALSELOCK

/* TSBITRATEM */
#define R367TER_TSBITRATEM
#define F367TER_TSFIFO_BITRATE_HI

/* TSBITRATEL */
#define R367TER_TSBITRATEL
#define F367TER_TSFIFO_BITRATE_LO

/* TSPACKLENM */
#define R367TER_TSPACKLENM
#define F367TER_TSFIFO_PACKCPT
#define F367TER_DIL_RPLEN_HI

/* TSPACKLENL */
#define R367TER_TSPACKLENL
#define F367TER_DIL_RPLEN_LO

/* TSBLOCLENM */
#define R367TER_TSBLOCLENM
#define F367TER_TSFIFO_PFLEN_HI

/* TSBLOCLENL */
#define R367TER_TSBLOCLENL
#define F367TER_TSFIFO_PFLEN_LO

/* TSDLYH */
#define R367TER_TSDLYH
#define F367TER_SOFFIFO_TSTIMEVALID
#define F367TER_SOFFIFO_SPEEDUP
#define F367TER_SOFFIFO_STOP
#define F367TER_SOFFIFO_REGULATED
#define F367TER_SOFFIFO_REALSBOFF_HI

/* TSDLYM */
#define R367TER_TSDLYM
#define F367TER_SOFFIFO_REALSBOFF_MED

/* TSDLYL */
#define R367TER_TSDLYL
#define F367TER_SOFFIFO_REALSBOFF_LO

/* TSNPDAV */
#define R367TER_TSNPDAV
#define F367TER_TSNPD_AVERAGE

/* TSBUFSTATH */
#define R367TER_TSBUFSTATH
#define F367TER_TSISCR_3BYTES
#define F367TER_TSISCR_NEWDATA
#define F367TER_TSISCR_BUFSTAT_HI

/* TSBUFSTATM */
#define R367TER_TSBUFSTATM
#define F367TER_TSISCR_BUFSTAT_MED

/* TSBUFSTATL */
#define R367TER_TSBUFSTATL
#define F367TER_TSISCR_BUFSTAT_LO

/* TSDEBUGM */
#define R367TER_TSDEBUGM
#define F367TER_TSFIFO_ILLPACKET
#define F367TER_DIL_NOSYNC
#define F367TER_DIL_ISCR
#define F367TER_DILOUT_BSYNCB
#define F367TER_TSFIFO_EMPTYPKT
#define F367TER_TSFIFO_EMPTYRD
#define F367TER_SOFFIFO_STOPM
#define F367TER_SOFFIFO_SPEEDUPM

/* TSDEBUGL */
#define R367TER_TSDEBUGL
#define F367TER_TSFIFO_PACKLENFAIL
#define F367TER_TSFIFO_SYNCBFAIL
#define F367TER_TSFIFO_VITLIBRE
#define F367TER_TSFIFO_BOOSTSPEEDM
#define F367TER_TSFIFO_UNDERSPEEDM
#define F367TER_TSFIFO_ERROR_EVNT
#define F367TER_TSFIFO_FULL
#define F367TER_TSFIFO_OVERFLOWM

/* TSDLYSETH */
#define R367TER_TSDLYSETH
#define F367TER_SOFFIFO_OFFSET
#define F367TER_SOFFIFO_SYMBOFFSET_HI

/* TSDLYSETM */
#define R367TER_TSDLYSETM
#define F367TER_SOFFIFO_SYMBOFFSET_MED

/* TSDLYSETL */
#define R367TER_TSDLYSETL
#define F367TER_SOFFIFO_SYMBOFFSET_LO

/* TSOBSCFG */
#define R367TER_TSOBSCFG
#define F367TER_TSFIFO_OBSCFG

/* TSOBSM */
#define R367TER_TSOBSM
#define F367TER_TSFIFO_OBSDATA_HI

/* TSOBSL */
#define R367TER_TSOBSL
#define F367TER_TSFIFO_OBSDATA_LO

/* ERRCTRL1 */
#define R367TER_ERRCTRL1
#define F367TER_ERR_SRC1
#define F367TER_ERRCTRL1_3
#define F367TER_NUM_EVT1

/* ERRCNT1H */
#define R367TER_ERRCNT1H
#define F367TER_ERRCNT1_OLDVALUE
#define F367TER_ERR_CNT1

/* ERRCNT1M */
#define R367TER_ERRCNT1M
#define F367TER_ERR_CNT1_HI

/* ERRCNT1L */
#define R367TER_ERRCNT1L
#define F367TER_ERR_CNT1_LO

/* ERRCTRL2 */
#define R367TER_ERRCTRL2
#define F367TER_ERR_SRC2
#define F367TER_ERRCTRL2_3
#define F367TER_NUM_EVT2

/* ERRCNT2H */
#define R367TER_ERRCNT2H
#define F367TER_ERRCNT2_OLDVALUE
#define F367TER_ERR_CNT2_HI

/* ERRCNT2M */
#define R367TER_ERRCNT2M
#define F367TER_ERR_CNT2_MED

/* ERRCNT2L */
#define R367TER_ERRCNT2L
#define F367TER_ERR_CNT2_LO

/* FECSPY */
#define R367TER_FECSPY
#define F367TER_SPY_ENABLE
#define F367TER_NO_SYNCBYTE
#define F367TER_SERIAL_MODE
#define F367TER_UNUSUAL_PACKET
#define F367TER_BERMETER_DATAMODE
#define F367TER_BERMETER_LMODE
#define F367TER_BERMETER_RESET

/* FSPYCFG */
#define R367TER_FSPYCFG
#define F367TER_FECSPY_INPUT
#define F367TER_RST_ON_ERROR
#define F367TER_ONE_SHOT
#define F367TER_I2C_MOD
#define F367TER_SPY_HYSTERESIS

/* FSPYDATA */
#define R367TER_FSPYDATA
#define F367TER_SPY_STUFFING
#define F367TER_NOERROR_PKTJITTER
#define F367TER_SPY_CNULLPKT
#define F367TER_SPY_OUTDATA_MODE

/* FSPYOUT */
#define R367TER_FSPYOUT
#define F367TER_FSPY_DIRECT
#define F367TER_FSPYOUT_6
#define F367TER_SPY_OUTDATA_BUS
#define F367TER_STUFF_MODE

/* FSTATUS */
#define R367TER_FSTATUS
#define F367TER_SPY_ENDSIM
#define F367TER_VALID_SIM
#define F367TER_FOUND_SIGNAL
#define F367TER_DSS_SYNCBYTE
#define F367TER_RESULT_STATE

/* FGOODPACK */
#define R367TER_FGOODPACK
#define F367TER_FGOOD_PACKET

/* FPACKCNT */
#define R367TER_FPACKCNT
#define F367TER_FPACKET_COUNTER

/* FSPYMISC */
#define R367TER_FSPYMISC
#define F367TER_FLABEL_COUNTER

/* FBERCPT4 */
#define R367TER_FBERCPT4
#define F367TER_FBERMETER_CPT5

/* FBERCPT3 */
#define R367TER_FBERCPT3
#define F367TER_FBERMETER_CPT4

/* FBERCPT2 */
#define R367TER_FBERCPT2
#define F367TER_FBERMETER_CPT3

/* FBERCPT1 */
#define R367TER_FBERCPT1
#define F367TER_FBERMETER_CPT2

/* FBERCPT0 */
#define R367TER_FBERCPT0
#define F367TER_FBERMETER_CPT1

/* FBERERR2 */
#define R367TER_FBERERR2
#define F367TER_FBERMETER_ERR_HI

/* FBERERR1 */
#define R367TER_FBERERR1
#define F367TER_FBERMETER_ERR_MED

/* FBERERR0 */
#define R367TER_FBERERR0
#define F367TER_FBERMETER_ERR_LO

/* FSTATESM */
#define R367TER_FSTATESM
#define F367TER_RSTATE_F
#define F367TER_RSTATE_E
#define F367TER_RSTATE_D
#define F367TER_RSTATE_C
#define F367TER_RSTATE_B
#define F367TER_RSTATE_A
#define F367TER_RSTATE_9
#define F367TER_RSTATE_8

/* FSTATESL */
#define R367TER_FSTATESL
#define F367TER_RSTATE_7
#define F367TER_RSTATE_6
#define F367TER_RSTATE_5
#define F367TER_RSTATE_4
#define F367TER_RSTATE_3
#define F367TER_RSTATE_2
#define F367TER_RSTATE_1
#define F367TER_RSTATE_0

/* FSPYBER */
#define R367TER_FSPYBER
#define F367TER_FSPYBER_7
#define F367TER_FSPYOBS_XORREAD
#define F367TER_FSPYBER_OBSMODE
#define F367TER_FSPYBER_SYNCBYTE
#define F367TER_FSPYBER_UNSYNC
#define F367TER_FSPYBER_CTIME

/* FSPYDISTM */
#define R367TER_FSPYDISTM
#define F367TER_PKTTIME_DISTANCE_HI

/* FSPYDISTL */
#define R367TER_FSPYDISTL
#define F367TER_PKTTIME_DISTANCE_LO

/* FSPYOBS7 */
#define R367TER_FSPYOBS7
#define F367TER_FSPYOBS_SPYFAIL
#define F367TER_FSPYOBS_SPYFAIL1
#define F367TER_FSPYOBS_ERROR
#define F367TER_FSPYOBS_STROUT
#define F367TER_FSPYOBS_RESULTSTATE1

/* FSPYOBS6 */
#define R367TER_FSPYOBS6
#define F367TER_FSPYOBS_RESULTSTATe0
#define F367TER_FSPYOBS_RESULTSTATEM1

/* FSPYOBS5 */
#define R367TER_FSPYOBS5
#define F367TER_FSPYOBS_BYTEOFPACKET1

/* FSPYOBS4 */
#define R367TER_FSPYOBS4
#define F367TER_FSPYOBS_BYTEVALUE1

/* FSPYOBS3 */
#define R367TER_FSPYOBS3
#define F367TER_FSPYOBS_DATA1

/* FSPYOBS2 */
#define R367TER_FSPYOBS2
#define F367TER_FSPYOBS_DATa0

/* FSPYOBS1 */
#define R367TER_FSPYOBS1
#define F367TER_FSPYOBS_DATAM1

/* FSPYOBS0 */
#define R367TER_FSPYOBS0
#define F367TER_FSPYOBS_DATAM2

/* SFDEMAP */
#define R367TER_SFDEMAP
#define F367TER_SFDEMAP_7
#define F367TER_SFEC_K_DIVIDER_VIT

/* SFERROR */
#define R367TER_SFERROR
#define F367TER_SFEC_REGERR_VIT

/* SFAVSR */
#define R367TER_SFAVSR
#define F367TER_SFEC_SUMERRORS
#define F367TER_SERROR_MAXMODE
#define F367TER_SN_SFEC
#define F367TER_KDIV_MODE_SFEC
#define F367TER_SFAVSR_1
#define F367TER_SFAVSR_0

/* SFECSTATUS */
#define R367TER_SFECSTATUS
#define F367TER_SFEC_ON
#define F367TER_SFSTATUS_6
#define F367TER_SFSTATUS_5
#define F367TER_SFSTATUS_4
#define F367TER_LOCKEDSFEC
#define F367TER_SFEC_DELOCK
#define F367TER_SFEC_DEMODSEL1
#define F367TER_SFEC_OVFON

/* SFKDIV12 */
#define R367TER_SFKDIV12
#define F367TER_SFECKDIV12_MAN
#define F367TER_SFEC_K_DIVIDER_12

/* SFKDIV23 */
#define R367TER_SFKDIV23
#define F367TER_SFECKDIV23_MAN
#define F367TER_SFEC_K_DIVIDER_23

/* SFKDIV34 */
#define R367TER_SFKDIV34
#define F367TER_SFECKDIV34_MAN
#define F367TER_SFEC_K_DIVIDER_34

/* SFKDIV56 */
#define R367TER_SFKDIV56
#define F367TER_SFECKDIV56_MAN
#define F367TER_SFEC_K_DIVIDER_56

/* SFKDIV67 */
#define R367TER_SFKDIV67
#define F367TER_SFECKDIV67_MAN
#define F367TER_SFEC_K_DIVIDER_67

/* SFKDIV78 */
#define R367TER_SFKDIV78
#define F367TER_SFECKDIV78_MAN
#define F367TER_SFEC_K_DIVIDER_78

/* SFDILSTKM */
#define R367TER_SFDILSTKM
#define F367TER_SFEC_PACKCPT
#define F367TER_SFEC_DILSTK_HI

/* SFDILSTKL */
#define R367TER_SFDILSTKL
#define F367TER_SFEC_DILSTK_LO

/* SFSTATUS */
#define R367TER_SFSTATUS
#define F367TER_SFEC_LINEOK
#define F367TER_SFEC_ERROR
#define F367TER_SFEC_DATA7
#define F367TER_SFEC_OVERFLOW
#define F367TER_SFEC_DEMODSEL2
#define F367TER_SFEC_NOSYNC
#define F367TER_SFEC_UNREGULA
#define F367TER_SFEC_READY

/* SFDLYH */
#define R367TER_SFDLYH
#define F367TER_SFEC_TSTIMEVALID
#define F367TER_SFEC_SPEEDUP
#define F367TER_SFEC_STOP
#define F367TER_SFEC_REGULATED
#define F367TER_SFEC_REALSYMBOFFSET

/* SFDLYM */
#define R367TER_SFDLYM
#define F367TER_SFEC_REALSYMBOFFSET_HI

/* SFDLYL */
#define R367TER_SFDLYL
#define F367TER_SFEC_REALSYMBOFFSET_LO

/* SFDLYSETH */
#define R367TER_SFDLYSETH
#define F367TER_SFEC_OFFSET
#define F367TER_SFECDLYSETH_4
#define F367TER_RST_SFEC
#define F367TER_SFECDLYSETH_2
#define F367TER_SFEC_DISABLE
#define F367TER_SFEC_UNREGUL

/* SFDLYSETM */
#define R367TER_SFDLYSETM
#define F367TER_SFECDLYSETM_7
#define F367TER_SFEC_SYMBOFFSET_HI

/* SFDLYSETL */
#define R367TER_SFDLYSETL
#define F367TER_SFEC_SYMBOFFSET_LO

/* SFOBSCFG */
#define R367TER_SFOBSCFG
#define F367TER_SFEC_OBSCFG

/* SFOBSM */
#define R367TER_SFOBSM
#define F367TER_SFEC_OBSDATA_HI

/* SFOBSL */
#define R367TER_SFOBSL
#define F367TER_SFEC_OBSDATA_LO

/* SFECINFO */
#define R367TER_SFECINFO
#define F367TER_SFECINFO_7
#define F367TER_SFEC_SYNCDLSB
#define F367TER_SFCE_S1cPHASE

/* SFERRCTRL */
#define R367TER_SFERRCTRL
#define F367TER_SFEC_ERR_SOURCE
#define F367TER_SFERRCTRL_3
#define F367TER_SFEC_NUM_EVENT

/* SFERRCNTH */
#define R367TER_SFERRCNTH
#define F367TER_SFERRC_OLDVALUE
#define F367TER_SFEC_ERR_CNT

/* SFERRCNTM */
#define R367TER_SFERRCNTM
#define F367TER_SFEC_ERR_CNT_HI

/* SFERRCNTL */
#define R367TER_SFERRCNTL
#define F367TER_SFEC_ERR_CNT_LO

/* SYMBRATEM */
#define R367TER_SYMBRATEM
#define F367TER_DEFGEN_SYMBRATE_HI

/* SYMBRATEL */
#define R367TER_SYMBRATEL
#define F367TER_DEFGEN_SYMBRATE_LO

/* SYMBSTATUS */
#define R367TER_SYMBSTATUS
#define F367TER_SYMBDLINE2_OFF
#define F367TER_SDDL_REINIT1
#define F367TER_SDD_REINIT1
#define F367TER_TOKENID_ERROR
#define F367TER_SYMBRATE_OVERFLOW
#define F367TER_SYMBRATE_UNDERFLOW
#define F367TER_TOKENID_RSTEVENT
#define F367TER_TOKENID_RESET1

/* SYMBCFG */
#define R367TER_SYMBCFG
#define F367TER_SYMBCFG_7
#define F367TER_SYMBCFG_6
#define F367TER_SYMBCFG_5
#define F367TER_SYMBCFG_4
#define F367TER_SYMRATE_FSPEED
#define F367TER_SYMRATE_SSPEED

/* SYMBFIFOM */
#define R367TER_SYMBFIFOM
#define F367TER_SYMBFIFOM_7
#define F367TER_SYMBFIFOM_6
#define F367TER_DEFGEN_SYMFIFO_HI

/* SYMBFIFOL */
#define R367TER_SYMBFIFOL
#define F367TER_DEFGEN_SYMFIFO_LO

/* SYMBOFFSM */
#define R367TER_SYMBOFFSM
#define F367TER_TOKENID_RESET2
#define F367TER_SDDL_REINIT2
#define F367TER_SDD_REINIT2
#define F367TER_SYMBOFFSM_4
#define F367TER_SYMBOFFSM_3
#define F367TER_DEFGEN_SYMBOFFSET_HI

/* SYMBOFFSL */
#define R367TER_SYMBOFFSL
#define F367TER_DEFGEN_SYMBOFFSET_LO

/* DEBUG_LT4 */
#define R367TER_DEBUG_LT4
#define F367TER_F_DEBUG_LT4

/* DEBUG_LT5 */
#define R367TER_DEBUG_LT5
#define F367TER_F_DEBUG_LT5

/* DEBUG_LT6 */
#define R367TER_DEBUG_LT6
#define F367TER_F_DEBUG_LT6

/* DEBUG_LT7 */
#define R367TER_DEBUG_LT7
#define F367TER_F_DEBUG_LT7

/* DEBUG_LT8 */
#define R367TER_DEBUG_LT8
#define F367TER_F_DEBUG_LT8

/* DEBUG_LT9 */
#define R367TER_DEBUG_LT9
#define F367TER_F_DEBUG_LT9

/* ID */
#define R367CAB_ID
#define F367CAB_IDENTIFICATIONREGISTER

/* I2CRPT */
#define R367CAB_I2CRPT
#define F367CAB_I2CT_ON
#define F367CAB_ENARPT_LEVEL
#define F367CAB_SCLT_DELAY
#define F367CAB_SCLT_NOD
#define F367CAB_STOP_ENABLE
#define F367CAB_SDAT_NOD

/* TOPCTRL */
#define R367CAB_TOPCTRL
#define F367CAB_STDBY
#define F367CAB_STDBY_CORE
#define F367CAB_QAM_COFDM
#define F367CAB_TS_DIS
#define F367CAB_DIR_CLK_216

/* IOCFG0 */
#define R367CAB_IOCFG0
#define F367CAB_OP0_SD
#define F367CAB_OP0_VAL
#define F367CAB_OP0_OD
#define F367CAB_OP0_INV
#define F367CAB_OP0_DACVALUE_HI

/* DAc0R */
#define R367CAB_DAC0R
#define F367CAB_OP0_DACVALUE_LO

/* IOCFG1 */
#define R367CAB_IOCFG1
#define F367CAB_IP0
#define F367CAB_OP1_OD
#define F367CAB_OP1_INV
#define F367CAB_OP1_DACVALUE_HI

/* DAC1R */
#define R367CAB_DAC1R
#define F367CAB_OP1_DACVALUE_LO

/* IOCFG2 */
#define R367CAB_IOCFG2
#define F367CAB_OP2_LOCK_CONF
#define F367CAB_OP2_OD
#define F367CAB_OP2_VAL
#define F367CAB_OP1_LOCK_CONF

/* SDFR */
#define R367CAB_SDFR
#define F367CAB_OP0_FREQ
#define F367CAB_OP1_FREQ

/* AUX_CLK */
#define R367CAB_AUX_CLK
#define F367CAB_AUXFEC_CTL
#define F367CAB_DIS_CKX4
#define F367CAB_CKSEL
#define F367CAB_CKDIV_PROG
#define F367CAB_AUXCLK_ENA

/* FREESYS1 */
#define R367CAB_FREESYS1
#define F367CAB_FREESYS_1

/* FREESYS2 */
#define R367CAB_FREESYS2
#define F367CAB_FREESYS_2

/* FREESYS3 */
#define R367CAB_FREESYS3
#define F367CAB_FREESYS_3

/* GPIO_CFG */
#define R367CAB_GPIO_CFG
#define F367CAB_GPIO7_OD
#define F367CAB_GPIO7_CFG
#define F367CAB_GPIO6_OD
#define F367CAB_GPIO6_CFG
#define F367CAB_GPIO5_OD
#define F367CAB_GPIO5_CFG
#define F367CAB_GPIO4_OD
#define F367CAB_GPIO4_CFG

/* GPIO_CMD */
#define R367CAB_GPIO_CMD
#define F367CAB_GPIO7_VAL
#define F367CAB_GPIO6_VAL
#define F367CAB_GPIO5_VAL
#define F367CAB_GPIO4_VAL

/* TSTRES */
#define R367CAB_TSTRES
#define F367CAB_FRES_DISPLAY
#define F367CAB_FRES_FIFO_AD
#define F367CAB_FRESRS
#define F367CAB_FRESACS
#define F367CAB_FRESFEC
#define F367CAB_FRES_PRIF
#define F367CAB_FRESCORE

/* ANACTRL */
#define R367CAB_ANACTRL
#define F367CAB_BYPASS_XTAL
#define F367CAB_BYPASS_PLLXN
#define F367CAB_DIS_PAD_OSC
#define F367CAB_STDBY_PLLXN

/* TSTBUS */
#define R367CAB_TSTBUS
#define F367CAB_TS_BYTE_CLK_INV
#define F367CAB_CFG_IP
#define F367CAB_CFG_TST

/* RF_AGC1 */
#define R367CAB_RF_AGC1
#define F367CAB_RF_AGC1_LEVEL_HI

/* RF_AGC2 */
#define R367CAB_RF_AGC2
#define F367CAB_REF_ADGP
#define F367CAB_STDBY_ADCGP
#define F367CAB_RF_AGC1_LEVEL_LO

/* ANADIGCTRL */
#define R367CAB_ANADIGCTRL
#define F367CAB_SEL_CLKDEM
#define F367CAB_EN_BUFFER_Q
#define F367CAB_EN_BUFFER_I
#define F367CAB_ADC_RIS_EGDE
#define F367CAB_SGN_ADC
#define F367CAB_SEL_AD12_SYNC

/* PLLMDIV */
#define R367CAB_PLLMDIV
#define F367CAB_PLL_MDIV

/* PLLNDIV */
#define R367CAB_PLLNDIV
#define F367CAB_PLL_NDIV

/* PLLSETUP */
#define R367CAB_PLLSETUP
#define F367CAB_PLL_PDIV
#define F367CAB_PLL_KDIV

/* DUAL_AD12 */
#define R367CAB_DUAL_AD12
#define F367CAB_FS20M
#define F367CAB_FS50M
#define F367CAB_INMODe0
#define F367CAB_POFFQ
#define F367CAB_POFFI
#define F367CAB_INMODE1

/* TSTBIST */
#define R367CAB_TSTBIST
#define F367CAB_TST_BYP_CLK
#define F367CAB_TST_GCLKENA_STD
#define F367CAB_TST_GCLKENA
#define F367CAB_TST_MEMBIST

/* CTRL_1 */
#define R367CAB_CTRL_1
#define F367CAB_SOFT_RST
#define F367CAB_EQU_RST
#define F367CAB_CRL_RST
#define F367CAB_TRL_RST
#define F367CAB_AGC_RST

/* CTRL_2 */
#define R367CAB_CTRL_2
#define F367CAB_DEINT_RST
#define F367CAB_RS_RST

/* IT_STATUS1 */
#define R367CAB_IT_STATUS1
#define F367CAB_SWEEP_OUT
#define F367CAB_FSM_CRL
#define F367CAB_CRL_LOCK
#define F367CAB_MFSM
#define F367CAB_TRL_LOCK
#define F367CAB_TRL_AGC_LIMIT
#define F367CAB_ADJ_AGC_LOCK
#define F367CAB_AGC_QAM_LOCK

/* IT_STATUS2 */
#define R367CAB_IT_STATUS2
#define F367CAB_TSMF_CNT
#define F367CAB_TSMF_EOF
#define F367CAB_TSMF_RDY
#define F367CAB_FEC_NOCORR
#define F367CAB_SYNCSTATE
#define F367CAB_DEINT_LOCK
#define F367CAB_FADDING_FRZ
#define F367CAB_TAPMON_ALARM

/* IT_EN1 */
#define R367CAB_IT_EN1
#define F367CAB_SWEEP_OUTE
#define F367CAB_FSM_CRLE
#define F367CAB_CRL_LOCKE
#define F367CAB_MFSME
#define F367CAB_TRL_LOCKE
#define F367CAB_TRL_AGC_LIMITE
#define F367CAB_ADJ_AGC_LOCKE
#define F367CAB_AGC_LOCKE

/* IT_EN2 */
#define R367CAB_IT_EN2
#define F367CAB_TSMF_CNTE
#define F367CAB_TSMF_EOFE
#define F367CAB_TSMF_RDYE
#define F367CAB_FEC_NOCORRE
#define F367CAB_SYNCSTATEE
#define F367CAB_DEINT_LOCKE
#define F367CAB_FADDING_FRZE
#define F367CAB_TAPMON_ALARME

/* CTRL_STATUS */
#define R367CAB_CTRL_STATUS
#define F367CAB_QAMFEC_LOCK
#define F367CAB_TSMF_LOCK
#define F367CAB_TSMF_ERROR

/* TEST_CTL */
#define R367CAB_TEST_CTL
#define F367CAB_TST_BLK_SEL
#define F367CAB_TST_BUS_SEL

/* AGC_CTL */
#define R367CAB_AGC_CTL
#define F367CAB_AGC_LCK_TH
#define F367CAB_AGC_ACCUMRSTSEL

/* AGC_IF_CFG */
#define R367CAB_AGC_IF_CFG
#define F367CAB_AGC_IF_BWSEL
#define F367CAB_AGC_IF_FREEZE

/* AGC_RF_CFG */
#define R367CAB_AGC_RF_CFG
#define F367CAB_AGC_RF_BWSEL
#define F367CAB_AGC_RF_FREEZE

/* AGC_PWM_CFG */
#define R367CAB_AGC_PWM_CFG
#define F367CAB_AGC_RF_PWM_TST
#define F367CAB_AGC_RF_PWM_INV
#define F367CAB_AGC_IF_PWM_TST
#define F367CAB_AGC_IF_PWM_INV
#define F367CAB_AGC_PWM_CLKDIV

/* AGC_PWR_REF_L */
#define R367CAB_AGC_PWR_REF_L
#define F367CAB_AGC_PWRREF_LO

/* AGC_PWR_REF_H */
#define R367CAB_AGC_PWR_REF_H
#define F367CAB_AGC_PWRREF_HI

/* AGC_RF_TH_L */
#define R367CAB_AGC_RF_TH_L
#define F367CAB_AGC_RF_TH_LO

/* AGC_RF_TH_H */
#define R367CAB_AGC_RF_TH_H
#define F367CAB_AGC_RF_TH_HI

/* AGC_IF_LTH_L */
#define R367CAB_AGC_IF_LTH_L
#define F367CAB_AGC_IF_THLO_LO

/* AGC_IF_LTH_H */
#define R367CAB_AGC_IF_LTH_H
#define F367CAB_AGC_IF_THLO_HI

/* AGC_IF_HTH_L */
#define R367CAB_AGC_IF_HTH_L
#define F367CAB_AGC_IF_THHI_LO

/* AGC_IF_HTH_H */
#define R367CAB_AGC_IF_HTH_H
#define F367CAB_AGC_IF_THHI_HI

/* AGC_PWR_RD_L */
#define R367CAB_AGC_PWR_RD_L
#define F367CAB_AGC_PWR_WORD_LO

/* AGC_PWR_RD_M */
#define R367CAB_AGC_PWR_RD_M
#define F367CAB_AGC_PWR_WORD_ME

/* AGC_PWR_RD_H */
#define R367CAB_AGC_PWR_RD_H
#define F367CAB_AGC_PWR_WORD_HI

/* AGC_PWM_IFCMD_L */
#define R367CAB_AGC_PWM_IFCMD_L
#define F367CAB_AGC_IF_PWMCMD_LO

/* AGC_PWM_IFCMD_H */
#define R367CAB_AGC_PWM_IFCMD_H
#define F367CAB_AGC_IF_PWMCMD_HI

/* AGC_PWM_RFCMD_L */
#define R367CAB_AGC_PWM_RFCMD_L
#define F367CAB_AGC_RF_PWMCMD_LO

/* AGC_PWM_RFCMD_H */
#define R367CAB_AGC_PWM_RFCMD_H
#define F367CAB_AGC_RF_PWMCMD_HI

/* IQDEM_CFG */
#define R367CAB_IQDEM_CFG
#define F367CAB_IQDEM_CLK_SEL
#define F367CAB_IQDEM_INVIQ
#define F367CAB_IQDEM_A2dTYPE

/* MIX_NCO_LL */
#define R367CAB_MIX_NCO_LL
#define F367CAB_MIX_NCO_INC_LL

/* MIX_NCO_HL */
#define R367CAB_MIX_NCO_HL
#define F367CAB_MIX_NCO_INC_HL

/* MIX_NCO_HH */
#define R367CAB_MIX_NCO_HH
#define F367CAB_MIX_NCO_INVCNST
#define F367CAB_MIX_NCO_INC_HH

/* SRC_NCO_LL */
#define R367CAB_SRC_NCO_LL
#define F367CAB_SRC_NCO_INC_LL

/* SRC_NCO_LH */
#define R367CAB_SRC_NCO_LH
#define F367CAB_SRC_NCO_INC_LH

/* SRC_NCO_HL */
#define R367CAB_SRC_NCO_HL
#define F367CAB_SRC_NCO_INC_HL

/* SRC_NCO_HH */
#define R367CAB_SRC_NCO_HH
#define F367CAB_SRC_NCO_INC_HH

/* IQDEM_GAIN_SRC_L */
#define R367CAB_IQDEM_GAIN_SRC_L
#define F367CAB_GAIN_SRC_LO

/* IQDEM_GAIN_SRC_H */
#define R367CAB_IQDEM_GAIN_SRC_H
#define F367CAB_GAIN_SRC_HI

/* IQDEM_DCRM_CFG_LL */
#define R367CAB_IQDEM_DCRM_CFG_LL
#define F367CAB_DCRM0_DCIN_L

/* IQDEM_DCRM_CFG_LH */
#define R367CAB_IQDEM_DCRM_CFG_LH
#define F367CAB_DCRM1_I_DCIN_L
#define F367CAB_DCRM0_DCIN_H

/* IQDEM_DCRM_CFG_HL */
#define R367CAB_IQDEM_DCRM_CFG_HL
#define F367CAB_DCRM1_Q_DCIN_L
#define F367CAB_DCRM1_I_DCIN_H

/* IQDEM_DCRM_CFG_HH */
#define R367CAB_IQDEM_DCRM_CFG_HH
#define F367CAB_DCRM1_FRZ
#define F367CAB_DCRM0_FRZ
#define F367CAB_DCRM1_Q_DCIN_H

/* IQDEM_ADJ_COEFf0 */
#define R367CAB_IQDEM_ADJ_COEFF0
#define F367CAB_ADJIIR_COEFF10_L

/* IQDEM_ADJ_COEFF1 */
#define R367CAB_IQDEM_ADJ_COEFF1
#define F367CAB_ADJIIR_COEFF11_L
#define F367CAB_ADJIIR_COEFF10_H

/* IQDEM_ADJ_COEFF2 */
#define R367CAB_IQDEM_ADJ_COEFF2
#define F367CAB_ADJIIR_COEFF12_L
#define F367CAB_ADJIIR_COEFF11_H

/* IQDEM_ADJ_COEFF3 */
#define R367CAB_IQDEM_ADJ_COEFF3
#define F367CAB_ADJIIR_COEFF20_L
#define F367CAB_ADJIIR_COEFF12_H

/* IQDEM_ADJ_COEFF4 */
#define R367CAB_IQDEM_ADJ_COEFF4
#define F367CAB_ADJIIR_COEFF20_H

/* IQDEM_ADJ_COEFF5 */
#define R367CAB_IQDEM_ADJ_COEFF5
#define F367CAB_ADJIIR_COEFF21_L

/* IQDEM_ADJ_COEFF6 */
#define R367CAB_IQDEM_ADJ_COEFF6
#define F367CAB_ADJIIR_COEFF22_L
#define F367CAB_ADJIIR_COEFF21_H

/* IQDEM_ADJ_COEFF7 */
#define R367CAB_IQDEM_ADJ_COEFF7
#define F367CAB_ADJIIR_COEFF22_H

/* IQDEM_ADJ_EN */
#define R367CAB_IQDEM_ADJ_EN
#define F367CAB_ALLPASSFILT_EN
#define F367CAB_ADJ_AGC_EN
#define F367CAB_ADJ_COEFF_FRZ
#define F367CAB_ADJ_EN

/* IQDEM_ADJ_AGC_REF */
#define R367CAB_IQDEM_ADJ_AGC_REF
#define F367CAB_ADJ_AGC_REF

/* ALLPASSFILT1 */
#define R367CAB_ALLPASSFILT1
#define F367CAB_ALLPASSFILT_COEFF1_LO

/* ALLPASSFILT2 */
#define R367CAB_ALLPASSFILT2
#define F367CAB_ALLPASSFILT_COEFF1_ME

/* ALLPASSFILT3 */
#define R367CAB_ALLPASSFILT3
#define F367CAB_ALLPASSFILT_COEFF2_LO
#define F367CAB_ALLPASSFILT_COEFF1_HI

/* ALLPASSFILT4 */
#define R367CAB_ALLPASSFILT4
#define F367CAB_ALLPASSFILT_COEFF2_MEL

/* ALLPASSFILT5 */
#define R367CAB_ALLPASSFILT5
#define F367CAB_ALLPASSFILT_COEFF2_MEH

/* ALLPASSFILT6 */
#define R367CAB_ALLPASSFILT6
#define F367CAB_ALLPASSFILT_COEFF3_LO
#define F367CAB_ALLPASSFILT_COEFF2_HI

/* ALLPASSFILT7 */
#define R367CAB_ALLPASSFILT7
#define F367CAB_ALLPASSFILT_COEFF3_MEL

/* ALLPASSFILT8 */
#define R367CAB_ALLPASSFILT8
#define F367CAB_ALLPASSFILT_COEFF3_MEH

/* ALLPASSFILT9 */
#define R367CAB_ALLPASSFILT9
#define F367CAB_ALLPASSFILT_COEFF4_LO
#define F367CAB_ALLPASSFILT_COEFF3_HI

/* ALLPASSFILT10 */
#define R367CAB_ALLPASSFILT10
#define F367CAB_ALLPASSFILT_COEFF4_ME

/* ALLPASSFILT11 */
#define R367CAB_ALLPASSFILT11
#define F367CAB_ALLPASSFILT_COEFF4_HI

/* TRL_AGC_CFG */
#define R367CAB_TRL_AGC_CFG
#define F367CAB_TRL_AGC_FREEZE
#define F367CAB_TRL_AGC_REF

/* TRL_LPF_CFG */
#define R367CAB_TRL_LPF_CFG
#define F367CAB_NYQPOINT_INV
#define F367CAB_TRL_SHIFT
#define F367CAB_NYQ_COEFF_SEL
#define F367CAB_TRL_LPF_FREEZE
#define F367CAB_TRL_LPF_CRT

/* TRL_LPF_ACQ_GAIN */
#define R367CAB_TRL_LPF_ACQ_GAIN
#define F367CAB_TRL_GDIR_ACQ
#define F367CAB_TRL_GINT_ACQ

/* TRL_LPF_TRK_GAIN */
#define R367CAB_TRL_LPF_TRK_GAIN
#define F367CAB_TRL_GDIR_TRK
#define F367CAB_TRL_GINT_TRK

/* TRL_LPF_OUT_GAIN */
#define R367CAB_TRL_LPF_OUT_GAIN
#define F367CAB_TRL_GAIN_OUT

/* TRL_LOCKDET_LTH */
#define R367CAB_TRL_LOCKDET_LTH
#define F367CAB_TRL_LCK_THLO

/* TRL_LOCKDET_HTH */
#define R367CAB_TRL_LOCKDET_HTH
#define F367CAB_TRL_LCK_THHI

/* TRL_LOCKDET_TRGVAL */
#define R367CAB_TRL_LOCKDET_TRGVAL
#define F367CAB_TRL_LCK_TRG

/* IQ_QAM */
#define R367CAB_IQ_QAM
#define F367CAB_IQ_INPUT
#define F367CAB_DETECT_MODE

/* FSM_STATE */
#define R367CAB_FSM_STATE
#define F367CAB_CRL_DFE
#define F367CAB_DFE_START
#define F367CAB_CTRLG_START
#define F367CAB_FSM_FORCESTATE

/* FSM_CTL */
#define R367CAB_FSM_CTL
#define F367CAB_FEC2_EN
#define F367CAB_SIT_EN
#define F367CAB_TRL_AHEAD
#define F367CAB_TRL2_EN
#define F367CAB_FSM_EQA1_EN
#define F367CAB_FSM_BKP_DIS
#define F367CAB_FSM_FORCE_EN

/* FSM_STS */
#define R367CAB_FSM_STS
#define F367CAB_FSM_STATUS

/* FSM_SNR0_HTH */
#define R367CAB_FSM_SNR0_HTH
#define F367CAB_SNR0_HTH

/* FSM_SNR1_HTH */
#define R367CAB_FSM_SNR1_HTH
#define F367CAB_SNR1_HTH

/* FSM_SNR2_HTH */
#define R367CAB_FSM_SNR2_HTH
#define F367CAB_SNR2_HTH

/* FSM_SNR0_LTH */
#define R367CAB_FSM_SNR0_LTH
#define F367CAB_SNR0_LTH

/* FSM_SNR1_LTH */
#define R367CAB_FSM_SNR1_LTH
#define F367CAB_SNR1_LTH

/* FSM_EQA1_HTH */
#define R367CAB_FSM_EQA1_HTH
#define F367CAB_SNR3_HTH_LO
#define F367CAB_EQA1_HTH

/* FSM_TEMPO */
#define R367CAB_FSM_TEMPO
#define F367CAB_SIT
#define F367CAB_WST
#define F367CAB_ELT
#define F367CAB_SNR3_HTH_HI

/* FSM_CONFIG */
#define R367CAB_FSM_CONFIG
#define F367CAB_FEC2_DFEOFF
#define F367CAB_PRIT_STATE
#define F367CAB_MODMAP_STATE

/* EQU_I_TESTTAP_L */
#define R367CAB_EQU_I_TESTTAP_L
#define F367CAB_I_TEST_TAP_L

/* EQU_I_TESTTAP_M */
#define R367CAB_EQU_I_TESTTAP_M
#define F367CAB_I_TEST_TAP_M

/* EQU_I_TESTTAP_H */
#define R367CAB_EQU_I_TESTTAP_H
#define F367CAB_I_TEST_TAP_H

/* EQU_TESTAP_CFG */
#define R367CAB_EQU_TESTAP_CFG
#define F367CAB_TEST_FFE_DFE_SEL
#define F367CAB_TEST_TAP_SELECT

/* EQU_Q_TESTTAP_L */
#define R367CAB_EQU_Q_TESTTAP_L
#define F367CAB_Q_TEST_TAP_L

/* EQU_Q_TESTTAP_M */
#define R367CAB_EQU_Q_TESTTAP_M
#define F367CAB_Q_TEST_TAP_M

/* EQU_Q_TESTTAP_H */
#define R367CAB_EQU_Q_TESTTAP_H
#define F367CAB_Q_TEST_TAP_H

/* EQU_TAP_CTRL */
#define R367CAB_EQU_TAP_CTRL
#define F367CAB_MTAP_FRZ
#define F367CAB_PRE_FREEZE
#define F367CAB_DFE_TAPMON_EN
#define F367CAB_FFE_TAPMON_EN
#define F367CAB_MTAP_ONLY

/* EQU_CTR_CRL_CONTROL_L */
#define R367CAB_EQU_CTR_CRL_CONTROL_L
#define F367CAB_EQU_CTR_CRL_CONTROL_LO

/* EQU_CTR_CRL_CONTROL_H */
#define R367CAB_EQU_CTR_CRL_CONTROL_H
#define F367CAB_EQU_CTR_CRL_CONTROL_HI

/* EQU_CTR_HIPOW_L */
#define R367CAB_EQU_CTR_HIPOW_L
#define F367CAB_CTR_HIPOW_L

/* EQU_CTR_HIPOW_H */
#define R367CAB_EQU_CTR_HIPOW_H
#define F367CAB_CTR_HIPOW_H

/* EQU_I_EQU_LO */
#define R367CAB_EQU_I_EQU_LO
#define F367CAB_EQU_I_EQU_L

/* EQU_I_EQU_HI */
#define R367CAB_EQU_I_EQU_HI
#define F367CAB_EQU_I_EQU_H

/* EQU_Q_EQU_LO */
#define R367CAB_EQU_Q_EQU_LO
#define F367CAB_EQU_Q_EQU_L

/* EQU_Q_EQU_HI */
#define R367CAB_EQU_Q_EQU_HI
#define F367CAB_EQU_Q_EQU_H

/* EQU_MAPPER */
#define R367CAB_EQU_MAPPER
#define F367CAB_QUAD_AUTO
#define F367CAB_QUAD_INV
#define F367CAB_QAM_MODE

/* EQU_SWEEP_RATE */
#define R367CAB_EQU_SWEEP_RATE
#define F367CAB_SNR_PER
#define F367CAB_SWEEP_RATE

/* EQU_SNR_LO */
#define R367CAB_EQU_SNR_LO
#define F367CAB_SNR_LO

/* EQU_SNR_HI */
#define R367CAB_EQU_SNR_HI
#define F367CAB_SNR_HI

/* EQU_GAMMA_LO */
#define R367CAB_EQU_GAMMA_LO
#define F367CAB_GAMMA_LO

/* EQU_GAMMA_HI */
#define R367CAB_EQU_GAMMA_HI
#define F367CAB_GAMMA_ME

/* EQU_ERR_GAIN */
#define R367CAB_EQU_ERR_GAIN
#define F367CAB_EQA1MU
#define F367CAB_CRL2MU
#define F367CAB_GAMMA_HI

/* EQU_RADIUS */
#define R367CAB_EQU_RADIUS
#define F367CAB_RADIUS

/* EQU_FFE_MAINTAP */
#define R367CAB_EQU_FFE_MAINTAP
#define F367CAB_FFE_MAINTAP_INIT

/* EQU_FFE_LEAKAGE */
#define R367CAB_EQU_FFE_LEAKAGE
#define F367CAB_LEAK_PER
#define F367CAB_EQU_OUTSEL
#define F367CAB_PNT2dFE

/* EQU_FFE_MAINTAP_POS */
#define R367CAB_EQU_FFE_MAINTAP_POS
#define F367CAB_FFE_LEAK_EN
#define F367CAB_DFE_LEAK_EN
#define F367CAB_FFE_MAINTAP_POS

/* EQU_GAIN_WIDE */
#define R367CAB_EQU_GAIN_WIDE
#define F367CAB_DFE_GAIN_WIDE
#define F367CAB_FFE_GAIN_WIDE

/* EQU_GAIN_NARROW */
#define R367CAB_EQU_GAIN_NARROW
#define F367CAB_DFE_GAIN_NARROW
#define F367CAB_FFE_GAIN_NARROW

/* EQU_CTR_LPF_GAIN */
#define R367CAB_EQU_CTR_LPF_GAIN
#define F367CAB_CTR_GTO
#define F367CAB_CTR_GDIR
#define F367CAB_SWEEP_EN
#define F367CAB_CTR_GINT

/* EQU_CRL_LPF_GAIN */
#define R367CAB_EQU_CRL_LPF_GAIN
#define F367CAB_CRL_GTO
#define F367CAB_CRL_GDIR
#define F367CAB_SWEEP_DIR
#define F367CAB_CRL_GINT

/* EQU_GLOBAL_GAIN */
#define R367CAB_EQU_GLOBAL_GAIN
#define F367CAB_CRL_GAIN
#define F367CAB_CTR_INC_GAIN
#define F367CAB_CTR_FRAC

/* EQU_CRL_LD_SEN */
#define R367CAB_EQU_CRL_LD_SEN
#define F367CAB_CTR_BADPOINT_EN
#define F367CAB_CTR_GAIN
#define F367CAB_LIMANEN
#define F367CAB_CRL_LD_SEN

/* EQU_CRL_LD_VAL */
#define R367CAB_EQU_CRL_LD_VAL
#define F367CAB_CRL_BISTH_LIMIT
#define F367CAB_CARE_EN
#define F367CAB_CRL_LD_PER
#define F367CAB_CRL_LD_WST
#define F367CAB_CRL_LD_TFS

/* EQU_CRL_TFR */
#define R367CAB_EQU_CRL_TFR
#define F367CAB_CRL_LD_TFR

/* EQU_CRL_BISTH_LO */
#define R367CAB_EQU_CRL_BISTH_LO
#define F367CAB_CRL_BISTH_LO

/* EQU_CRL_BISTH_HI */
#define R367CAB_EQU_CRL_BISTH_HI
#define F367CAB_CRL_BISTH_HI

/* EQU_SWEEP_RANGE_LO */
#define R367CAB_EQU_SWEEP_RANGE_LO
#define F367CAB_SWEEP_RANGE_LO

/* EQU_SWEEP_RANGE_HI */
#define R367CAB_EQU_SWEEP_RANGE_HI
#define F367CAB_SWEEP_RANGE_HI

/* EQU_CRL_LIMITER */
#define R367CAB_EQU_CRL_LIMITER
#define F367CAB_BISECTOR_EN
#define F367CAB_PHEST128_EN
#define F367CAB_CRL_LIM

/* EQU_MODULUS_MAP */
#define R367CAB_EQU_MODULUS_MAP
#define F367CAB_PNT_DEPTH
#define F367CAB_MODULUS_CMP

/* EQU_PNT_GAIN */
#define R367CAB_EQU_PNT_GAIN
#define F367CAB_PNT_EN
#define F367CAB_MODULUSMAP_EN
#define F367CAB_PNT_GAIN

/* FEC_AC_CTR_0 */
#define R367CAB_FEC_AC_CTR_0
#define F367CAB_BE_BYPASS
#define F367CAB_REFRESH47
#define F367CAB_CT_NBST
#define F367CAB_TEI_ENA
#define F367CAB_DS_ENA
#define F367CAB_TSMF_EN

/* FEC_AC_CTR_1 */
#define R367CAB_FEC_AC_CTR_1
#define F367CAB_DEINT_DEPTH

/* FEC_AC_CTR_2 */
#define R367CAB_FEC_AC_CTR_2
#define F367CAB_DEINT_M
#define F367CAB_DIS_UNLOCK
#define F367CAB_DESCR_MODE

/* FEC_AC_CTR_3 */
#define R367CAB_FEC_AC_CTR_3
#define F367CAB_DI_UNLOCK
#define F367CAB_DI_FREEZE
#define F367CAB_MISMATCH
#define F367CAB_ACQ_MODE
#define F367CAB_TRK_MODE

/* FEC_STATUS */
#define R367CAB_FEC_STATUS
#define F367CAB_DEINT_SMCNTR
#define F367CAB_DEINT_SYNCSTATE
#define F367CAB_DEINT_SYNLOST
#define F367CAB_DESCR_SYNCSTATE

/* RS_COUNTER_0 */
#define R367CAB_RS_COUNTER_0
#define F367CAB_BK_CT_L

/* RS_COUNTER_1 */
#define R367CAB_RS_COUNTER_1
#define F367CAB_BK_CT_H

/* RS_COUNTER_2 */
#define R367CAB_RS_COUNTER_2
#define F367CAB_CORR_CT_L

/* RS_COUNTER_3 */
#define R367CAB_RS_COUNTER_3
#define F367CAB_CORR_CT_H

/* RS_COUNTER_4 */
#define R367CAB_RS_COUNTER_4
#define F367CAB_UNCORR_CT_L

/* RS_COUNTER_5 */
#define R367CAB_RS_COUNTER_5
#define F367CAB_UNCORR_CT_H

/* BERT_0 */
#define R367CAB_BERT_0
#define F367CAB_RS_NOCORR
#define F367CAB_CT_HOLD
#define F367CAB_CT_CLEAR

/* BERT_1 */
#define R367CAB_BERT_1
#define F367CAB_BERT_ON
#define F367CAB_BERT_ERR_SRC
#define F367CAB_BERT_ERR_MODE
#define F367CAB_BERT_NBYTE

/* BERT_2 */
#define R367CAB_BERT_2
#define F367CAB_BERT_ERRCOUNT_L

/* BERT_3 */
#define R367CAB_BERT_3
#define F367CAB_BERT_ERRCOUNT_H

/* OUTFORMAT_0 */
#define R367CAB_OUTFORMAT_0
#define F367CAB_CLK_POLARITY
#define F367CAB_FEC_TYPE
#define F367CAB_SYNC_STRIP
#define F367CAB_TS_SWAP
#define F367CAB_OUTFORMAT

/* OUTFORMAT_1 */
#define R367CAB_OUTFORMAT_1
#define F367CAB_CI_DIVRANGE

/* SMOOTHER_2 */
#define R367CAB_SMOOTHER_2
#define F367CAB_FIFO_BYPASS

/* TSMF_CTRL_0 */
#define R367CAB_TSMF_CTRL_0
#define F367CAB_TS_NUMBER
#define F367CAB_SEL_MODE

/* TSMF_CTRL_1 */
#define R367CAB_TSMF_CTRL_1
#define F367CAB_CHECK_ERROR_BIT
#define F367CAB_CHCK_F_SYNC
#define F367CAB_H_MODE
#define F367CAB_D_V_MODE
#define F367CAB_MODE

/* TSMF_CTRL_3 */
#define R367CAB_TSMF_CTRL_3
#define F367CAB_SYNC_IN_COUNT
#define F367CAB_SYNC_OUT_COUNT

/* TS_ON_ID_0 */
#define R367CAB_TS_ON_ID_0
#define F367CAB_TS_ID_L

/* TS_ON_ID_1 */
#define R367CAB_TS_ON_ID_1
#define F367CAB_TS_ID_H

/* TS_ON_ID_2 */
#define R367CAB_TS_ON_ID_2
#define F367CAB_ON_ID_L

/* TS_ON_ID_3 */
#define R367CAB_TS_ON_ID_3
#define F367CAB_ON_ID_H

/* RE_STATUS_0 */
#define R367CAB_RE_STATUS_0
#define F367CAB_RECEIVE_STATUS_L

/* RE_STATUS_1 */
#define R367CAB_RE_STATUS_1
#define F367CAB_RECEIVE_STATUS_LH

/* RE_STATUS_2 */
#define R367CAB_RE_STATUS_2
#define F367CAB_RECEIVE_STATUS_HL

/* RE_STATUS_3 */
#define R367CAB_RE_STATUS_3
#define F367CAB_RECEIVE_STATUS_HH

/* TS_STATUS_0 */
#define R367CAB_TS_STATUS_0
#define F367CAB_TS_STATUS_L

/* TS_STATUS_1 */
#define R367CAB_TS_STATUS_1
#define F367CAB_TS_STATUS_H

/* TS_STATUS_2 */
#define R367CAB_TS_STATUS_2
#define F367CAB_ERROR
#define F367CAB_EMERGENCY
#define F367CAB_CRE_TS
#define F367CAB_VER
#define F367CAB_M_LOCK

/* TS_STATUS_3 */
#define R367CAB_TS_STATUS_3
#define F367CAB_UPDATE_READY
#define F367CAB_END_FRAME_HEADER
#define F367CAB_CONTCNT
#define F367CAB_TS_IDENTIFIER_SEL

/* T_O_ID_0 */
#define R367CAB_T_O_ID_0
#define F367CAB_ON_ID_I_L

/* T_O_ID_1 */
#define R367CAB_T_O_ID_1
#define F367CAB_ON_ID_I_H

/* T_O_ID_2 */
#define R367CAB_T_O_ID_2
#define F367CAB_TS_ID_I_L

/* T_O_ID_3 */
#define R367CAB_T_O_ID_3
#define F367CAB_TS_ID_I_H

#endif