linux/drivers/media/rc/ene_ir.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
 *
 * Copyright (C) 2010 Maxim Levitsky <[email protected]>
 */
#include <linux/spinlock.h>


/* hardware address */
#define ENE_STATUS
#define ENE_ADDR_HI
#define ENE_ADDR_LO
#define ENE_IO
#define ENE_IO_SIZE

/* 8 bytes of samples, divided in 2 packets*/
#define ENE_FW_SAMPLE_BUFFER
#define ENE_FW_SAMPLE_SPACE
#define ENE_FW_PACKET_SIZE

/* first firmware flag register */
#define ENE_FW1
#define ENE_FW1_ENABLE
#define ENE_FW1_TXIRQ
#define ENE_FW1_HAS_EXTRA_BUF
#define ENE_FW1_EXTRA_BUF_HND
#define ENE_FW1_LED_ON

#define ENE_FW1_WPATTERN
#define ENE_FW1_WAKE
#define ENE_FW1_IRQ

/* second firmware flag register */
#define ENE_FW2
#define ENE_FW2_BUF_WPTR
#define ENE_FW2_RXIRQ
#define ENE_FW2_GP0A
#define ENE_FW2_EMMITER1_CONN
#define ENE_FW2_EMMITER2_CONN

#define ENE_FW2_FAN_INPUT
#define ENE_FW2_LEARNING

/* firmware RX pointer for new style buffer */
#define ENE_FW_RX_POINTER

/* high parts of samples for fan input (8 samples)*/
#define ENE_FW_SMPL_BUF_FAN
#define ENE_FW_SMPL_BUF_FAN_PLS
#define ENE_FW_SMPL_BUF_FAN_MSK
#define ENE_FW_SAMPLE_PERIOD_FAN

/* transmitter ports */
#define ENE_GPIOFS1
#define ENE_GPIOFS1_GPIO0D
#define ENE_GPIOFS8
#define ENE_GPIOFS8_GPIO41

/* IRQ registers block (for revision B) */
#define ENEB_IRQ
#define ENEB_IRQ_UNK1
#define ENEB_IRQ_STATUS
#define ENEB_IRQ_STATUS_IR

/* fan as input settings */
#define ENE_FAN_AS_IN1
#define ENE_FAN_AS_IN1_EN
#define ENE_FAN_AS_IN2
#define ENE_FAN_AS_IN2_EN

/* IRQ registers block (for revision C,D) */
#define ENE_IRQ
#define ENE_IRQ_MASK
#define ENE_IRQ_UNK_EN
#define ENE_IRQ_STATUS

/* CIR Config register #1 */
#define ENE_CIRCFG
#define ENE_CIRCFG_RX_EN
#define ENE_CIRCFG_RX_IRQ
#define ENE_CIRCFG_REV_POL
#define ENE_CIRCFG_CARR_DEMOD

#define ENE_CIRCFG_TX_EN
#define ENE_CIRCFG_TX_IRQ
#define ENE_CIRCFG_TX_POL_REV
#define ENE_CIRCFG_TX_CARR

/* CIR config register #2 */
#define ENE_CIRCFG2
#define ENE_CIRCFG2_RLC
#define ENE_CIRCFG2_RC5
#define ENE_CIRCFG2_RC6
#define ENE_CIRCFG2_NEC
#define ENE_CIRCFG2_CARR_DETECT
#define ENE_CIRCFG2_GPIO0A
#define ENE_CIRCFG2_FAST_SAMPL1
#define ENE_CIRCFG2_FAST_SAMPL2

/* Knobs for protocol decoding - will document when/if will use them */
#define ENE_CIRPF
#define ENE_CIRHIGH
#define ENE_CIRBIT
#define ENE_CIRSTART
#define ENE_CIRSTART2

/* Actual register which contains RLC RX data - read by firmware */
#define ENE_CIRDAT_IN


/* RLC configuration - sample period (1us resolution) + idle mode */
#define ENE_CIRRLC_CFG
#define ENE_CIRRLC_CFG_OVERFLOW
#define ENE_DEFAULT_SAMPLE_PERIOD

/* Two byte RLC TX buffer */
#define ENE_CIRRLC_OUT0
#define ENE_CIRRLC_OUT1
#define ENE_CIRRLC_OUT_PULSE
#define ENE_CIRRLC_OUT_MASK


/* Carrier detect setting
 * Low nibble  - number of carrier pulses to average
 * High nibble - number of initial carrier pulses to discard
 */
#define ENE_CIRCAR_PULS

/* detected RX carrier period (resolution: 500 ns) */
#define ENE_CIRCAR_PRD
#define ENE_CIRCAR_PRD_VALID

/* detected RX carrier pulse width (resolution: 500 ns) */
#define ENE_CIRCAR_HPRD

/* TX period (resolution: 500 ns, minimum 2)*/
#define ENE_CIRMOD_PRD
#define ENE_CIRMOD_PRD_POL

#define ENE_CIRMOD_PRD_MAX
#define ENE_CIRMOD_PRD_MIN

/* TX pulse width (resolution: 500 ns)*/
#define ENE_CIRMOD_HPRD

/* Hardware versions */
#define ENE_ECHV
#define ENE_PLLFRH
#define ENE_PLLFRL
#define ENE_DEFAULT_PLL_FREQ

#define ENE_ECSTS
#define ENE_ECSTS_RSRVD

#define ENE_ECVER_MAJOR
#define ENE_ECVER_MINOR
#define ENE_HW_VER_OLD

/******************************************************************************/

#define ENE_DRIVER_NAME

#define ENE_IRQ_RX
#define ENE_IRQ_TX

#define ENE_HW_B
#define ENE_HW_C
#define ENE_HW_D

#define __dbg(level, format, ...)

#define dbg(format, ...)
#define dbg_verbose(format, ...)
#define dbg_regs(format, ...)

struct ene_device {};

static int ene_irq_status(struct ene_device *dev);
static void ene_rx_read_hw_pointer(struct ene_device *dev);