/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR * * Copyright (C) 2011 Jarod Wilson <[email protected]> * * Special thanks to Fintek for providing hardware and spec sheets. * This driver is based upon the nuvoton, ite and ene drivers for * similar hardware. */ #include <linux/spinlock.h> #include <linux/ioctl.h> /* platform driver name to register */ #define FINTEK_DRIVER_NAME … #define FINTEK_DESCRIPTION … #define VENDOR_ID_FINTEK … /* debugging module parameter */ static int debug; #define fit_pr(level, text, ...) … #define fit_dbg(text, ...) … #define fit_dbg_verbose(text, ...) … #define fit_dbg_wake(text, ...) … #define TX_BUF_LEN … #define RX_BUF_LEN … struct fintek_dev { … }; /* buffer packet constants, largely identical to mceusb.c */ #define BUF_PULSE_BIT … #define BUF_LEN_MASK … #define BUF_SAMPLE_MASK … #define BUF_COMMAND_HEADER … #define BUF_COMMAND_MASK … #define BUF_COMMAND_NULL … #define BUF_HW_CMD_HEADER … #define BUF_CMD_G_REVISION … #define BUF_CMD_S_CARRIER … #define BUF_CMD_S_TIMEOUT … #define BUF_CMD_SIG_END … #define BUF_CMD_S_TXMASK … #define BUF_CMD_S_RXSENSOR … #define BUF_RSP_PULSE_COUNT … #define CIR_SAMPLE_PERIOD … /* * Configuration Register: * Index Port * Data Port */ #define CR_INDEX_PORT … #define CR_DATA_PORT … /* Possible alternate values, depends on how the chip is wired */ #define CR_INDEX_PORT2 … #define CR_DATA_PORT2 … /* * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is * active. 1 = 0x4e, 0 = 0x2e */ #define PORT_SEL_PORT_4E_EN … /* Extended Function Mode enable/disable magic values */ #define CONFIG_REG_ENABLE … #define CONFIG_REG_DISABLE … /* Chip IDs found in CR_CHIP_ID_{HI,LO} */ #define CHIP_ID_HIGH_F71809U … #define CHIP_ID_LOW_F71809U … /* * Global control regs we need to care about: * Global Control def. * Register name addr val. */ #define GCR_SOFTWARE_RESET … #define GCR_LOGICAL_DEV_NO … #define GCR_CHIP_ID_HI … #define GCR_CHIP_ID_LO … #define GCR_VENDOR_ID_HI … #define GCR_VENDOR_ID_LO … #define GCR_CONFIG_PORT_SEL … #define GCR_KBMOUSE_WAKEUP … #define LOGICAL_DEV_DISABLE … #define LOGICAL_DEV_ENABLE … /* Logical device number of the CIR function */ #define LOGICAL_DEV_CIR_REV1 … #define LOGICAL_DEV_CIR_REV2 … /* CIR Logical Device (LDN 0x08) config registers */ #define CIR_CR_COMMAND_INDEX … #define CIR_CR_IRCS … #define CIR_CR_COMMAND_DATA … #define CIR_CR_CLASS … #define CIR_CR_DEV_EN … #define CIR_CR_BASE_ADDR_HI … #define CIR_CR_BASE_ADDR_LO … #define CIR_CR_IRQ_SEL … #define CIR_CR_PSOUT_STATUS … #define CIR_CR_WAKE_KEY3_ADDR … #define CIR_CR_WAKE_KEY3_CODE … #define CIR_CR_WAKE_KEY3_DC … #define CIR_CR_WAKE_CONTROL … #define CIR_CR_WAKE_KEY12_ADDR … #define CIR_CR_WAKE_KEY4_ADDR … #define CIR_CR_WAKE_KEY5_ADDR … #define CLASS_RX_ONLY … #define CLASS_RX_2TX … #define CLASS_RX_1TX … /* CIR device registers */ #define CIR_STATUS … #define CIR_RX_DATA … #define CIR_TX_CONTROL … #define CIR_TX_DATA … #define CIR_CONTROL … /* Bits to enable CIR wake */ #define LOGICAL_DEV_ACPI … #define LDEV_ACPI_WAKE_EN_REG … #define ACPI_WAKE_EN_CIR_BIT … #define LDEV_ACPI_PME_EN_REG … #define LDEV_ACPI_PME_CLR_REG … #define ACPI_PME_CIR_BIT … #define LDEV_ACPI_STATE_REG … #define ACPI_STATE_CIR_BIT … /* * CIR status register (0x00): * 7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable) * 3 - TX_FINISH (1 when TX finished, write 1 to clear) * 2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear) * 1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear) * 0 - RX_RECEIVE (1 on RX receive, write 1 to clear) */ #define CIR_STATUS_IRQ_EN … #define CIR_STATUS_TX_FINISH … #define CIR_STATUS_TX_UNDERRUN … #define CIR_STATUS_RX_TIMEOUT … #define CIR_STATUS_RX_RECEIVE … #define CIR_STATUS_IRQ_MASK … /* * CIR TX control register (0x02): * 7 - TX_START (1 to indicate TX start, auto-cleared when done) * 6 - TX_END (1 to indicate TX data written to TX fifo) */ #define CIR_TX_CONTROL_TX_START … #define CIR_TX_CONTROL_TX_END …
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