/* SPDX-License-Identifier: GPL-2.0-or-later */ /* * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR * * Copyright (C) 2010 Jarod Wilson <[email protected]> * Copyright (C) 2009 Nuvoton PS Team * * Special thanks to Nuvoton for providing hardware, spec sheets and * sample code upon which portions of this driver are based. Indirect * thanks also to Maxim Levitsky, whose ene_ir driver this driver is * modeled after. */ #include <linux/spinlock.h> #include <linux/ioctl.h> /* platform driver name to register */ #define NVT_DRIVER_NAME … /* debugging module parameter */ static int debug; #define nvt_dbg(text, ...) … #define nvt_dbg_verbose(text, ...) … #define nvt_dbg_wake(text, ...) … #define RX_BUF_LEN … #define SIO_ID_MASK … enum nvt_chip_ver { … }; struct nvt_chip { … }; struct nvt_dev { … }; /* buffer packet constants */ #define BUF_PULSE_BIT … #define BUF_LEN_MASK … #define BUF_REPEAT_BYTE … #define BUF_REPEAT_MASK … /* CIR settings */ /* total length of CIR and CIR WAKE */ #define CIR_IOREG_LENGTH … /* RX limit length, 8 high bits for SLCH, 8 low bits for SLCL */ #define CIR_RX_LIMIT_COUNT … /* CIR Regs */ #define CIR_IRCON … #define CIR_IRSTS … #define CIR_IREN … #define CIR_RXFCONT … #define CIR_CP … #define CIR_CC … #define CIR_SLCH … #define CIR_SLCL … #define CIR_FIFOCON … #define CIR_IRFIFOSTS … #define CIR_SRXFIFO … #define CIR_TXFCONT … #define CIR_STXFIFO … #define CIR_FCCH … #define CIR_FCCL … #define CIR_IRFSM … /* CIR IRCON settings */ #define CIR_IRCON_RECV … #define CIR_IRCON_WIREN … #define CIR_IRCON_TXEN … #define CIR_IRCON_RXEN … #define CIR_IRCON_WRXINV … #define CIR_IRCON_RXINV … #define CIR_IRCON_SAMPLE_PERIOD_SEL_1 … #define CIR_IRCON_SAMPLE_PERIOD_SEL_25 … #define CIR_IRCON_SAMPLE_PERIOD_SEL_50 … #define CIR_IRCON_SAMPLE_PERIOD_SEL_100 … /* FIXME: make this a runtime option */ /* select sample period as 50us */ #define CIR_IRCON_SAMPLE_PERIOD_SEL … /* CIR IRSTS settings */ #define CIR_IRSTS_RDR … #define CIR_IRSTS_RTR … #define CIR_IRSTS_PE … #define CIR_IRSTS_RFO … #define CIR_IRSTS_TE … #define CIR_IRSTS_TTR … #define CIR_IRSTS_TFU … #define CIR_IRSTS_GH … /* CIR IREN settings */ #define CIR_IREN_RDR … #define CIR_IREN_RTR … #define CIR_IREN_PE … #define CIR_IREN_RFO … #define CIR_IREN_TE … #define CIR_IREN_TTR … #define CIR_IREN_TFU … #define CIR_IREN_GH … /* CIR FIFOCON settings */ #define CIR_FIFOCON_TXFIFOCLR … #define CIR_FIFOCON_TX_TRIGGER_LEV_31 … #define CIR_FIFOCON_TX_TRIGGER_LEV_24 … #define CIR_FIFOCON_TX_TRIGGER_LEV_16 … #define CIR_FIFOCON_TX_TRIGGER_LEV_8 … /* FIXME: make this a runtime option */ /* select TX trigger level as 16 */ #define CIR_FIFOCON_TX_TRIGGER_LEV … #define CIR_FIFOCON_RXFIFOCLR … #define CIR_FIFOCON_RX_TRIGGER_LEV_1 … #define CIR_FIFOCON_RX_TRIGGER_LEV_8 … #define CIR_FIFOCON_RX_TRIGGER_LEV_16 … #define CIR_FIFOCON_RX_TRIGGER_LEV_24 … /* FIXME: make this a runtime option */ /* select RX trigger level as 24 */ #define CIR_FIFOCON_RX_TRIGGER_LEV … /* CIR IRFIFOSTS settings */ #define CIR_IRFIFOSTS_IR_PENDING … #define CIR_IRFIFOSTS_RX_GS … #define CIR_IRFIFOSTS_RX_FTA … #define CIR_IRFIFOSTS_RX_EMPTY … #define CIR_IRFIFOSTS_RX_FULL … #define CIR_IRFIFOSTS_TX_FTA … #define CIR_IRFIFOSTS_TX_EMPTY … #define CIR_IRFIFOSTS_TX_FULL … /* CIR WAKE UP Regs */ #define CIR_WAKE_IRCON … #define CIR_WAKE_IRSTS … #define CIR_WAKE_IREN … #define CIR_WAKE_FIFO_CMP_DEEP … #define CIR_WAKE_FIFO_CMP_TOL … #define CIR_WAKE_FIFO_COUNT … #define CIR_WAKE_SLCH … #define CIR_WAKE_SLCL … #define CIR_WAKE_FIFOCON … #define CIR_WAKE_SRXFSTS … #define CIR_WAKE_SAMPLE_RX_FIFO … #define CIR_WAKE_WR_FIFO_DATA … #define CIR_WAKE_RD_FIFO_ONLY … #define CIR_WAKE_RD_FIFO_ONLY_IDX … #define CIR_WAKE_FIFO_IGNORE … #define CIR_WAKE_IRFSM … /* CIR WAKE UP IRCON settings */ #define CIR_WAKE_IRCON_DEC_RST … #define CIR_WAKE_IRCON_MODE1 … #define CIR_WAKE_IRCON_MODE0 … #define CIR_WAKE_IRCON_RXEN … #define CIR_WAKE_IRCON_R … #define CIR_WAKE_IRCON_RXINV … /* FIXME/jarod: make this a runtime option */ /* select a same sample period like cir register */ #define CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL … /* CIR WAKE IRSTS Bits */ #define CIR_WAKE_IRSTS_RDR … #define CIR_WAKE_IRSTS_RTR … #define CIR_WAKE_IRSTS_PE … #define CIR_WAKE_IRSTS_RFO … #define CIR_WAKE_IRSTS_GH … #define CIR_WAKE_IRSTS_IR_PENDING … /* CIR WAKE UP IREN Bits */ #define CIR_WAKE_IREN_RDR … #define CIR_WAKE_IREN_RTR … #define CIR_WAKE_IREN_PE … #define CIR_WAKE_IREN_RFO … #define CIR_WAKE_IREN_GH … /* CIR WAKE FIFOCON settings */ #define CIR_WAKE_FIFOCON_RXFIFOCLR … #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_67 … #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_66 … #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_65 … #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV_64 … /* FIXME: make this a runtime option */ /* select WAKE UP RX trigger level as 67 */ #define CIR_WAKE_FIFOCON_RX_TRIGGER_LEV … /* CIR WAKE SRXFSTS settings */ #define CIR_WAKE_IRFIFOSTS_RX_GS … #define CIR_WAKE_IRFIFOSTS_RX_FTA … #define CIR_WAKE_IRFIFOSTS_RX_EMPTY … #define CIR_WAKE_IRFIFOSTS_RX_FULL … /* * The CIR Wake FIFO buffer is 67 bytes long, but the stock remote wakes * the system comparing only 65 bytes (fails with this set to 67) */ #define CIR_WAKE_FIFO_CMP_BYTES … /* CIR Wake byte comparison tolerance */ #define CIR_WAKE_CMP_TOLERANCE … /* * Extended Function Enable Registers: * Extended Function Index Register * Extended Function Data Register */ #define CR_EFIR … #define CR_EFDR … /* Possible alternate EFER values, depends on how the chip is wired */ #define CR_EFIR2 … #define CR_EFDR2 … /* Extended Function Mode enable/disable magic values */ #define EFER_EFM_ENABLE … #define EFER_EFM_DISABLE … /* Config regs we need to care about */ #define CR_SOFTWARE_RESET … #define CR_LOGICAL_DEV_SEL … #define CR_CHIP_ID_HI … #define CR_CHIP_ID_LO … #define CR_DEV_POWER_DOWN … #define CR_OUTPUT_PIN_SEL … #define CR_MULTIFUNC_PIN_SEL … #define CR_LOGICAL_DEV_EN … /* next three regs valid for both the CIR and CIR_WAKE logical devices */ #define CR_CIR_BASE_ADDR_HI … #define CR_CIR_BASE_ADDR_LO … #define CR_CIR_IRQ_RSRC … /* next three regs valid only for ACPI logical dev */ #define CR_ACPI_CIR_WAKE … #define CR_ACPI_IRQ_EVENTS … #define CR_ACPI_IRQ_EVENTS2 … /* Logical devices that we need to care about */ #define LOGICAL_DEV_LPT … #define LOGICAL_DEV_CIR … #define LOGICAL_DEV_ACPI … #define LOGICAL_DEV_CIR_WAKE … #define LOGICAL_DEV_DISABLE … #define LOGICAL_DEV_ENABLE … #define CIR_WAKE_ENABLE_BIT … #define PME_INTR_CIR_PASS_BIT … /* w83677hg CIR pin config */ #define OUTPUT_PIN_SEL_MASK … #define OUTPUT_ENABLE_CIR … #define OUTPUT_ENABLE_CIRWB … /* w83667hg CIR pin config */ #define MULTIFUNC_PIN_SEL_MASK … #define MULTIFUNC_ENABLE_CIR … #define MULTIFUNC_ENABLE_CIRWB … /* MCE CIR signal length, related on sample period */ /* MCE CIR controller signal length: about 43ms * 43ms / 50us (sample period) * 0.85 (inaccuracy) */ #define CONTROLLER_BUF_LEN_MIN … /* MCE CIR keyboard signal length: about 26ms * 26ms / 50us (sample period) * 0.85 (inaccuracy) */ #define KEYBOARD_BUF_LEN_MAX … #define KEYBOARD_BUF_LEN_MIN … /* MCE CIR mouse signal length: about 24ms * 24ms / 50us (sample period) * 0.85 (inaccuracy) */ #define MOUSE_BUF_LEN_MIN … #define CIR_SAMPLE_PERIOD … #define CIR_SAMPLE_LOW_INACCURACY … /* MAX silence time that driver will sent to lirc */ #define MAX_SILENCE_TIME … #if CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_100 #define SAMPLE_PERIOD … #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_50 #define SAMPLE_PERIOD … #elif CIR_IRCON_SAMPLE_PERIOD_SEL == CIR_IRCON_SAMPLE_PERIOD_SEL_25 #define SAMPLE_PERIOD … #else #define SAMPLE_PERIOD … #endif /* as VISTA MCE definition, valid carrier value */ #define MAX_CARRIER … #define MIN_CARRIER … /* max wakeup sequence length */ #define WAKEUP_MAX_SIZE …
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