// SPDX-License-Identifier: GPL-2.0 /* * Driver for Renesas RZ/G2L MIPI CSI-2 Receiver * * Copyright (C) 2022 Renesas Electronics Corp. */ #include <linux/clk.h> #include <linux/delay.h> #include <linux/interrupt.h> #include <linux/io.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_graph.h> #include <linux/platform_device.h> #include <linux/pm_runtime.h> #include <linux/reset.h> #include <linux/sys_soc.h> #include <linux/units.h> #include <media/v4l2-ctrls.h> #include <media/v4l2-device.h> #include <media/v4l2-fwnode.h> #include <media/v4l2-mc.h> #include <media/v4l2-subdev.h> /* LINK registers */ /* Module Configuration Register */ #define CSI2nMCG … #define CSI2nMCG_SDLN … /* Module Control Register 0 */ #define CSI2nMCT0 … #define CSI2nMCT0_VDLN(x) … /* Module Control Register 2 */ #define CSI2nMCT2 … #define CSI2nMCT2_FRRSKW(x) … #define CSI2nMCT2_FRRCLK(x) … /* Module Control Register 3 */ #define CSI2nMCT3 … #define CSI2nMCT3_RXEN … /* Reset Control Register */ #define CSI2nRTCT … #define CSI2nRTCT_VSRST … /* Reset Status Register */ #define CSI2nRTST … #define CSI2nRTST_VSRSTS … /* Receive Data Type Enable Low Register */ #define CSI2nDTEL … /* Receive Data Type Enable High Register */ #define CSI2nDTEH … /* DPHY registers */ /* D-PHY Control Register 0 */ #define CSIDPHYCTRL0 … #define CSIDPHYCTRL0_EN_LDO1200 … #define CSIDPHYCTRL0_EN_BGR … /* D-PHY Timing Register 0 */ #define CSIDPHYTIM0 … #define CSIDPHYTIM0_TCLK_MISS(x) … #define CSIDPHYTIM0_T_INIT(x) … /* D-PHY Timing Register 1 */ #define CSIDPHYTIM1 … #define CSIDPHYTIM1_THS_PREPARE(x) … #define CSIDPHYTIM1_TCLK_PREPARE(x) … #define CSIDPHYTIM1_THS_SETTLE(x) … #define CSIDPHYTIM1_TCLK_SETTLE(x) … /* D-PHY Skew Adjustment Function */ #define CSIDPHYSKW0 … #define CSIDPHYSKW0_UTIL_DL0_SKW_ADJ(x) … #define CSIDPHYSKW0_UTIL_DL1_SKW_ADJ(x) … #define CSIDPHYSKW0_UTIL_DL2_SKW_ADJ(x) … #define CSIDPHYSKW0_UTIL_DL3_SKW_ADJ(x) … #define CSIDPHYSKW0_DEFAULT_SKW … #define VSRSTS_RETRIES … #define RZG2L_CSI2_MIN_WIDTH … #define RZG2L_CSI2_MIN_HEIGHT … #define RZG2L_CSI2_MAX_WIDTH … #define RZG2L_CSI2_MAX_HEIGHT … #define RZG2L_CSI2_DEFAULT_WIDTH … #define RZG2L_CSI2_DEFAULT_HEIGHT … #define RZG2L_CSI2_DEFAULT_FMT … enum rzg2l_csi2_pads { … }; struct rzg2l_csi2 { … }; struct rzg2l_csi2_timings { … }; static const struct rzg2l_csi2_timings rzg2l_csi2_global_timings[] = …; struct rzg2l_csi2_format { … }; static const struct rzg2l_csi2_format rzg2l_csi2_formats[] = …; static inline struct rzg2l_csi2 *sd_to_csi2(struct v4l2_subdev *sd) { … } static const struct rzg2l_csi2_format *rzg2l_csi2_code_to_fmt(unsigned int code) { … } static inline struct rzg2l_csi2 *notifier_to_csi2(struct v4l2_async_notifier *n) { … } static u32 rzg2l_csi2_read(struct rzg2l_csi2 *csi2, unsigned int reg) { … } static void rzg2l_csi2_write(struct rzg2l_csi2 *csi2, unsigned int reg, u32 data) { … } static void rzg2l_csi2_set(struct rzg2l_csi2 *csi2, unsigned int reg, u32 set) { … } static void rzg2l_csi2_clr(struct rzg2l_csi2 *csi2, unsigned int reg, u32 clr) { … } static int rzg2l_csi2_calc_mbps(struct rzg2l_csi2 *csi2) { … } /* ----------------------------------------------------------------------------- * DPHY setting */ static int rzg2l_csi2_dphy_disable(struct rzg2l_csi2 *csi2) { … } static int rzg2l_csi2_dphy_enable(struct rzg2l_csi2 *csi2) { … } static int rzg2l_csi2_dphy_setting(struct v4l2_subdev *sd, bool on) { … } static int rzg2l_csi2_mipi_link_enable(struct rzg2l_csi2 *csi2) { … } static int rzg2l_csi2_mipi_link_disable(struct rzg2l_csi2 *csi2) { … } static int rzg2l_csi2_mipi_link_setting(struct v4l2_subdev *sd, bool on) { … } static int rzg2l_csi2_s_stream(struct v4l2_subdev *sd, int enable) { … } static int rzg2l_csi2_pre_streamon(struct v4l2_subdev *sd, u32 flags) { … } static int rzg2l_csi2_post_streamoff(struct v4l2_subdev *sd) { … } static int rzg2l_csi2_set_format(struct v4l2_subdev *sd, struct v4l2_subdev_state *state, struct v4l2_subdev_format *fmt) { … } static int rzg2l_csi2_init_state(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state) { … } static int rzg2l_csi2_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_mbus_code_enum *code) { … } static int rzg2l_csi2_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_state *sd_state, struct v4l2_subdev_frame_size_enum *fse) { … } static const struct v4l2_subdev_video_ops rzg2l_csi2_video_ops = …; static const struct v4l2_subdev_pad_ops rzg2l_csi2_pad_ops = …; static const struct v4l2_subdev_ops rzg2l_csi2_subdev_ops = …; static const struct v4l2_subdev_internal_ops rzg2l_csi2_internal_ops = …; /* ----------------------------------------------------------------------------- * Async handling and registration of subdevices and links. */ static int rzg2l_csi2_notify_bound(struct v4l2_async_notifier *notifier, struct v4l2_subdev *subdev, struct v4l2_async_connection *asd) { … } static void rzg2l_csi2_notify_unbind(struct v4l2_async_notifier *notifier, struct v4l2_subdev *subdev, struct v4l2_async_connection *asd) { … } static const struct v4l2_async_notifier_operations rzg2l_csi2_notify_ops = …; static int rzg2l_csi2_parse_v4l2(struct rzg2l_csi2 *csi2, struct v4l2_fwnode_endpoint *vep) { … } static int rzg2l_csi2_parse_dt(struct rzg2l_csi2 *csi2) { … } static int rzg2l_validate_csi2_lanes(struct rzg2l_csi2 *csi2) { … } /* ----------------------------------------------------------------------------- * Platform Device Driver. */ static const struct media_entity_operations rzg2l_csi2_entity_ops = …; static int rzg2l_csi2_probe(struct platform_device *pdev) { … } static void rzg2l_csi2_remove(struct platform_device *pdev) { … } static int rzg2l_csi2_pm_runtime_suspend(struct device *dev) { … } static int rzg2l_csi2_pm_runtime_resume(struct device *dev) { … } static const struct dev_pm_ops rzg2l_csi2_pm_ops = …; static const struct of_device_id rzg2l_csi2_of_table[] = …; MODULE_DEVICE_TABLE(of, rzg2l_csi2_of_table); static struct platform_driver rzg2l_csi2_pdrv = …; module_platform_driver(…) …; MODULE_AUTHOR(…) …; MODULE_DESCRIPTION(…) …; MODULE_LICENSE(…) …;
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