/* SPDX-License-Identifier: GPL-2.0-only */ /* * TI CAL camera interface driver * * Copyright (c) 2015 Texas Instruments Inc. * * Benoit Parrot, <[email protected]> */ #ifndef __TI_CAL_REGS_H #define __TI_CAL_REGS_H /* * struct cal_dev.flags possibilities * * DRA72_CAL_PRE_ES2_LDO_DISABLE: * Errata i913: CSI2 LDO Needs to be disabled when module is powered on * * Enabling CSI2 LDO shorts it to core supply. It is crucial the 2 CSI2 * LDOs on the device are disabled if CSI-2 module is powered on * (0x4845 B304 | 0x4845 B384 [28:27] = 0x1) or in ULPS (0x4845 B304 * | 0x4845 B384 [28:27] = 0x2) mode. Common concerns include: high * current draw on the module supply in active mode. * * Errata does not apply when CSI-2 module is powered off * (0x4845 B304 | 0x4845 B384 [28:27] = 0x0). * * SW Workaround: * Set the following register bits to disable the LDO, * which is essentially CSI2 REG10 bit 6: * * Core 0: 0x4845 B828 = 0x0000 0040 * Core 1: 0x4845 B928 = 0x0000 0040 */ #define DRA72_CAL_PRE_ES2_LDO_DISABLE … /* CAL register offsets */ #define CAL_HL_REVISION … #define CAL_HL_HWINFO … #define CAL_HL_SYSCONFIG … #define CAL_HL_IRQ_EOI … #define CAL_HL_IRQSTATUS_RAW(m) … #define CAL_HL_IRQSTATUS(m) … #define CAL_HL_IRQENABLE_SET(m) … #define CAL_HL_IRQENABLE_CLR(m) … #define CAL_PIX_PROC(m) … #define CAL_CTRL … #define CAL_CTRL1 … #define CAL_LINE_NUMBER_EVT … #define CAL_VPORT_CTRL1 … #define CAL_VPORT_CTRL2 … #define CAL_BYS_CTRL1 … #define CAL_BYS_CTRL2 … #define CAL_RD_DMA_CTRL … #define CAL_RD_DMA_PIX_ADDR … #define CAL_RD_DMA_PIX_OFST … #define CAL_RD_DMA_XSIZE … #define CAL_RD_DMA_YSIZE … #define CAL_RD_DMA_INIT_ADDR … #define CAL_RD_DMA_INIT_OFST … #define CAL_RD_DMA_CTRL2 … #define CAL_WR_DMA_CTRL(m) … #define CAL_WR_DMA_ADDR(m) … #define CAL_WR_DMA_OFST(m) … #define CAL_WR_DMA_XSIZE(m) … #define CAL_CSI2_PPI_CTRL(m) … #define CAL_CSI2_COMPLEXIO_CFG(m) … #define CAL_CSI2_COMPLEXIO_IRQSTATUS(m) … #define CAL_CSI2_SHORT_PACKET(m) … #define CAL_CSI2_COMPLEXIO_IRQENABLE(m) … #define CAL_CSI2_TIMING(m) … #define CAL_CSI2_VC_IRQENABLE(m) … #define CAL_CSI2_VC_IRQSTATUS(m) … #define CAL_CSI2_CTX(phy, csi2_ctx) … #define CAL_CSI2_STATUS(phy, csi2_ctx) … /* CAL CSI2 PHY register offsets */ #define CAL_CSI2_PHY_REG0 … #define CAL_CSI2_PHY_REG1 … #define CAL_CSI2_PHY_REG2 … #define CAL_CSI2_PHY_REG10 … /* CAL Control Module Core Camerrx Control register offsets */ #define CM_CTRL_CORE_CAMERRX_CONTROL … /********************************************************************* * Field Definition Macros *********************************************************************/ #define CAL_HL_REVISION_MINOR_MASK … #define CAL_HL_REVISION_CUSTOM_MASK … #define CAL_HL_REVISION_MAJOR_MASK … #define CAL_HL_REVISION_RTL_MASK … #define CAL_HL_REVISION_FUNC_MASK … #define CAL_HL_REVISION_SCHEME_MASK … #define CAL_HL_REVISION_SCHEME_H08 … #define CAL_HL_REVISION_SCHEME_LEGACY … #define CAL_HL_HWINFO_WFIFO_MASK … #define CAL_HL_HWINFO_RFIFO_MASK … #define CAL_HL_HWINFO_PCTX_MASK … #define CAL_HL_HWINFO_WCTX_MASK … #define CAL_HL_HWINFO_VFIFO_MASK … #define CAL_HL_HWINFO_NCPORT_MASK … #define CAL_HL_HWINFO_NPPI_CTXS0_MASK … #define CAL_HL_HWINFO_NPPI_CTXS1_MASK … #define CAL_HL_HWINFO_NPPI_CONTEXTS_ZERO … #define CAL_HL_HWINFO_NPPI_CONTEXTS_FOUR … #define CAL_HL_HWINFO_NPPI_CONTEXTS_EIGHT … #define CAL_HL_HWINFO_NPPI_CONTEXTS_RESERVED … #define CAL_HL_SYSCONFIG_SOFTRESET_MASK … #define CAL_HL_SYSCONFIG_SOFTRESET_DONE … #define CAL_HL_SYSCONFIG_SOFTRESET_PENDING … #define CAL_HL_SYSCONFIG_SOFTRESET_NOACTION … #define CAL_HL_SYSCONFIG_SOFTRESET_RESET … #define CAL_HL_SYSCONFIG_IDLE_MASK … #define CAL_HL_SYSCONFIG_IDLEMODE_FORCE … #define CAL_HL_SYSCONFIG_IDLEMODE_NO … #define CAL_HL_SYSCONFIG_IDLEMODE_SMART1 … #define CAL_HL_SYSCONFIG_IDLEMODE_SMART2 … #define CAL_HL_IRQ_EOI_LINE_NUMBER_MASK … #define CAL_HL_IRQ_EOI_LINE_NUMBER_READ0 … #define CAL_HL_IRQ_EOI_LINE_NUMBER_EOI0 … #define CAL_HL_IRQ_WDMA_END_MASK(m) … #define CAL_HL_IRQ_WDMA_START_MASK(m) … #define CAL_HL_IRQ_OCPO_ERR_MASK … #define CAL_HL_IRQ_CIO_MASK(i) … #define CAL_HL_IRQ_VC_MASK(i) … #define CAL_PIX_PROC_EN_MASK … #define CAL_PIX_PROC_EXTRACT_MASK … #define CAL_PIX_PROC_EXTRACT_B6 … #define CAL_PIX_PROC_EXTRACT_B7 … #define CAL_PIX_PROC_EXTRACT_B8 … #define CAL_PIX_PROC_EXTRACT_B10 … #define CAL_PIX_PROC_EXTRACT_B10_MIPI … #define CAL_PIX_PROC_EXTRACT_B12 … #define CAL_PIX_PROC_EXTRACT_B12_MIPI … #define CAL_PIX_PROC_EXTRACT_B14 … #define CAL_PIX_PROC_EXTRACT_B14_MIPI … #define CAL_PIX_PROC_EXTRACT_B16_BE … #define CAL_PIX_PROC_EXTRACT_B16_LE … #define CAL_PIX_PROC_DPCMD_MASK … #define CAL_PIX_PROC_DPCMD_BYPASS … #define CAL_PIX_PROC_DPCMD_DPCM_10_8_1 … #define CAL_PIX_PROC_DPCMD_DPCM_12_8_1 … #define CAL_PIX_PROC_DPCMD_DPCM_10_7_1 … #define CAL_PIX_PROC_DPCMD_DPCM_10_7_2 … #define CAL_PIX_PROC_DPCMD_DPCM_10_6_1 … #define CAL_PIX_PROC_DPCMD_DPCM_10_6_2 … #define CAL_PIX_PROC_DPCMD_DPCM_12_7_1 … #define CAL_PIX_PROC_DPCMD_DPCM_12_6_1 … #define CAL_PIX_PROC_DPCMD_DPCM_14_10 … #define CAL_PIX_PROC_DPCMD_DPCM_14_8_1 … #define CAL_PIX_PROC_DPCMD_DPCM_16_12_1 … #define CAL_PIX_PROC_DPCMD_DPCM_16_10_1 … #define CAL_PIX_PROC_DPCMD_DPCM_16_8_1 … #define CAL_PIX_PROC_DPCME_MASK … #define CAL_PIX_PROC_DPCME_BYPASS … #define CAL_PIX_PROC_DPCME_DPCM_10_8_1 … #define CAL_PIX_PROC_DPCME_DPCM_12_8_1 … #define CAL_PIX_PROC_DPCME_DPCM_14_10 … #define CAL_PIX_PROC_DPCME_DPCM_14_8_1 … #define CAL_PIX_PROC_DPCME_DPCM_16_12_1 … #define CAL_PIX_PROC_DPCME_DPCM_16_10_1 … #define CAL_PIX_PROC_DPCME_DPCM_16_8_1 … #define CAL_PIX_PROC_PACK_MASK … #define CAL_PIX_PROC_PACK_B8 … #define CAL_PIX_PROC_PACK_B10_MIPI … #define CAL_PIX_PROC_PACK_B12 … #define CAL_PIX_PROC_PACK_B12_MIPI … #define CAL_PIX_PROC_PACK_B16 … #define CAL_PIX_PROC_PACK_ARGB … #define CAL_PIX_PROC_CPORT_MASK … #define CAL_CTRL_POSTED_WRITES_MASK … #define CAL_CTRL_POSTED_WRITES_NONPOSTED … #define CAL_CTRL_POSTED_WRITES … #define CAL_CTRL_TAGCNT_MASK … #define CAL_CTRL_BURSTSIZE_MASK … #define CAL_CTRL_BURSTSIZE_BURST16 … #define CAL_CTRL_BURSTSIZE_BURST32 … #define CAL_CTRL_BURSTSIZE_BURST64 … #define CAL_CTRL_BURSTSIZE_BURST128 … #define CAL_CTRL_LL_FORCE_STATE_MASK … #define CAL_CTRL_MFLAGL_MASK … #define CAL_CTRL_PWRSCPCLK_MASK … #define CAL_CTRL_PWRSCPCLK_AUTO … #define CAL_CTRL_PWRSCPCLK_FORCE … #define CAL_CTRL_RD_DMA_STALL_MASK … #define CAL_CTRL_MFLAGH_MASK … #define CAL_CTRL1_PPI_GROUPING_MASK … #define CAL_CTRL1_PPI_GROUPING_DISABLED … #define CAL_CTRL1_PPI_GROUPING_RESERVED … #define CAL_CTRL1_PPI_GROUPING_0 … #define CAL_CTRL1_PPI_GROUPING_1 … #define CAL_CTRL1_INTERLEAVE01_MASK … #define CAL_CTRL1_INTERLEAVE01_DISABLED … #define CAL_CTRL1_INTERLEAVE01_PIX1 … #define CAL_CTRL1_INTERLEAVE01_PIX4 … #define CAL_CTRL1_INTERLEAVE01_RESERVED … #define CAL_CTRL1_INTERLEAVE23_MASK … #define CAL_CTRL1_INTERLEAVE23_DISABLED … #define CAL_CTRL1_INTERLEAVE23_PIX1 … #define CAL_CTRL1_INTERLEAVE23_PIX4 … #define CAL_CTRL1_INTERLEAVE23_RESERVED … #define CAL_LINE_NUMBER_EVT_CPORT_MASK … #define CAL_LINE_NUMBER_EVT_MASK … #define CAL_VPORT_CTRL1_PCLK_MASK … #define CAL_VPORT_CTRL1_XBLK_MASK … #define CAL_VPORT_CTRL1_YBLK_MASK … #define CAL_VPORT_CTRL1_WIDTH_MASK … #define CAL_VPORT_CTRL1_WIDTH_ONE … #define CAL_VPORT_CTRL1_WIDTH_TWO … #define CAL_VPORT_CTRL2_CPORT_MASK … #define CAL_VPORT_CTRL2_FREERUNNING_MASK … #define CAL_VPORT_CTRL2_FREERUNNING_GATED … #define CAL_VPORT_CTRL2_FREERUNNING_FREE … #define CAL_VPORT_CTRL2_FS_RESETS_MASK … #define CAL_VPORT_CTRL2_FS_RESETS_NO … #define CAL_VPORT_CTRL2_FS_RESETS_YES … #define CAL_VPORT_CTRL2_FSM_RESET_MASK … #define CAL_VPORT_CTRL2_FSM_RESET_NOEFFECT … #define CAL_VPORT_CTRL2_FSM_RESET … #define CAL_VPORT_CTRL2_RDY_THR_MASK … #define CAL_BYS_CTRL1_PCLK_MASK … #define CAL_BYS_CTRL1_XBLK_MASK … #define CAL_BYS_CTRL1_YBLK_MASK … #define CAL_BYS_CTRL1_BYSINEN_MASK … #define CAL_BYS_CTRL2_CPORTIN_MASK … #define CAL_BYS_CTRL2_CPORTOUT_MASK … #define CAL_BYS_CTRL2_DUPLICATEDDATA_MASK … #define CAL_BYS_CTRL2_DUPLICATEDDATA_NO … #define CAL_BYS_CTRL2_DUPLICATEDDATA_YES … #define CAL_BYS_CTRL2_FREERUNNING_MASK … #define CAL_BYS_CTRL2_FREERUNNING_NO … #define CAL_BYS_CTRL2_FREERUNNING_YES … #define CAL_RD_DMA_CTRL_GO_MASK … #define CAL_RD_DMA_CTRL_GO_DIS … #define CAL_RD_DMA_CTRL_GO_EN … #define CAL_RD_DMA_CTRL_GO_IDLE … #define CAL_RD_DMA_CTRL_GO_BUSY … #define CAL_RD_DMA_CTRL_INIT_MASK … #define CAL_RD_DMA_CTRL_BW_LIMITER_MASK … #define CAL_RD_DMA_CTRL_OCP_TAG_CNT_MASK … #define CAL_RD_DMA_CTRL_PCLK_MASK … #define CAL_RD_DMA_PIX_ADDR_MASK … #define CAL_RD_DMA_PIX_OFST_MASK … #define CAL_RD_DMA_XSIZE_MASK … #define CAL_RD_DMA_YSIZE_MASK … #define CAL_RD_DMA_INIT_ADDR_MASK … #define CAL_RD_DMA_INIT_OFST_MASK … #define CAL_RD_DMA_CTRL2_CIRC_MODE_MASK … #define CAL_RD_DMA_CTRL2_CIRC_MODE_DIS … #define CAL_RD_DMA_CTRL2_CIRC_MODE_ONE … #define CAL_RD_DMA_CTRL2_CIRC_MODE_FOUR … #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTEEN … #define CAL_RD_DMA_CTRL2_CIRC_MODE_SIXTYFOUR … #define CAL_RD_DMA_CTRL2_CIRC_MODE_RESERVED … #define CAL_RD_DMA_CTRL2_ICM_CSTART_MASK … #define CAL_RD_DMA_CTRL2_PATTERN_MASK … #define CAL_RD_DMA_CTRL2_PATTERN_LINEAR … #define CAL_RD_DMA_CTRL2_PATTERN_YUV420 … #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP2 … #define CAL_RD_DMA_CTRL2_PATTERN_RD2SKIP4 … #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_MASK … #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_FREERUNNING … #define CAL_RD_DMA_CTRL2_BYSOUT_LE_WAIT_WAITFORBYSOUT … #define CAL_RD_DMA_CTRL2_CIRC_SIZE_MASK … #define CAL_WR_DMA_CTRL_MODE_MASK … #define CAL_WR_DMA_CTRL_MODE_DIS … #define CAL_WR_DMA_CTRL_MODE_SHD … #define CAL_WR_DMA_CTRL_MODE_CNT … #define CAL_WR_DMA_CTRL_MODE_CNT_INIT … #define CAL_WR_DMA_CTRL_MODE_CONST … #define CAL_WR_DMA_CTRL_MODE_RESERVED … #define CAL_WR_DMA_CTRL_PATTERN_MASK … #define CAL_WR_DMA_CTRL_PATTERN_LINEAR … #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP2 … #define CAL_WR_DMA_CTRL_PATTERN_WR2SKIP4 … #define CAL_WR_DMA_CTRL_PATTERN_RESERVED … #define CAL_WR_DMA_CTRL_ICM_PSTART_MASK … #define CAL_WR_DMA_CTRL_DTAG_MASK … #define CAL_WR_DMA_CTRL_DTAG_ATT_HDR … #define CAL_WR_DMA_CTRL_DTAG_ATT_DAT … #define CAL_WR_DMA_CTRL_DTAG … #define CAL_WR_DMA_CTRL_DTAG_PIX_HDR … #define CAL_WR_DMA_CTRL_DTAG_PIX_DAT … #define CAL_WR_DMA_CTRL_DTAG_D5 … #define CAL_WR_DMA_CTRL_DTAG_D6 … #define CAL_WR_DMA_CTRL_DTAG_D7 … #define CAL_WR_DMA_CTRL_CPORT_MASK … #define CAL_WR_DMA_CTRL_STALL_RD_MASK … #define CAL_WR_DMA_CTRL_YSIZE_MASK … #define CAL_WR_DMA_ADDR_MASK … #define CAL_WR_DMA_OFST_MASK … #define CAL_WR_DMA_OFST_CIRC_MODE_MASK … #define CAL_WR_DMA_OFST_CIRC_MODE_ONE … #define CAL_WR_DMA_OFST_CIRC_MODE_FOUR … #define CAL_WR_DMA_OFST_CIRC_MODE_SIXTYFOUR … #define CAL_WR_DMA_OFST_CIRC_MODE_DISABLED … #define CAL_WR_DMA_OFST_CIRC_SIZE_MASK … #define CAL_WR_DMA_XSIZE_XSKIP_MASK … #define CAL_WR_DMA_XSIZE_MASK … #define CAL_CSI2_PPI_CTRL_IF_EN_MASK … #define CAL_CSI2_PPI_CTRL_ECC_EN_MASK … #define CAL_CSI2_PPI_CTRL_FRAME_MASK … #define CAL_CSI2_PPI_CTRL_FRAME_IMMEDIATE … #define CAL_CSI2_PPI_CTRL_FRAME … #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POSITION_MASK … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_5 … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_4 … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_3 … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_2 … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_1 … #define CAL_CSI2_COMPLEXIO_CFG_POSITION_NOT_USED … #define CAL_CSI2_COMPLEXIO_CFG_CLOCK_POL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_POL_PLUSMINUS … #define CAL_CSI2_COMPLEXIO_CFG_POL_MINUSPLUS … #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POSITION_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA1_POL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POSITION_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA2_POL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POSITION_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA3_POL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POSITION_MASK … #define CAL_CSI2_COMPLEXIO_CFG_DATA4_POL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_PWR_AUTO_MASK … #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_MASK … #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_OFF … #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ON … #define CAL_CSI2_COMPLEXIO_CFG_PWR_STATUS_STATE_ULP … #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_MASK … #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_OFF … #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ON … #define CAL_CSI2_COMPLEXIO_CFG_PWR_CMD_STATE_ULP … #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK … #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED … #define CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETONGOING … #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_MASK … #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL … #define CAL_CSI2_COMPLEXIO_CFG_RESET_CTRL_OPERATIONAL … #define CAL_CSI2_SHORT_PACKET_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS1_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS2_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS3_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS4_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTHS5_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS1_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS2_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS3_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS4_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRSOTSYNCHS5_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC1_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC2_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC3_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC4_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRESC5_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL1_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL2_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL3_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL4_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ERRCONTROL5_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_LANE_ERRORS_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM1_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM2_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM3_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM4_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEULPM5_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMENTER_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_STATEALLULPMEXIT_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_FIFO_OVR_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_SHORT_PACKET_MASK … #define CAL_CSI2_COMPLEXIO_IRQ_ECC_NO_CORRECTION_MASK … #define CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK … #define CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK … #define CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK … #define CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK … #define CAL_CSI2_VC_IRQ_FS_IRQ_MASK(n) … #define CAL_CSI2_VC_IRQ_FE_IRQ_MASK(n) … #define CAL_CSI2_VC_IRQ_LS_IRQ_MASK(n) … #define CAL_CSI2_VC_IRQ_LE_IRQ_MASK(n) … #define CAL_CSI2_VC_IRQ_CS_IRQ_MASK(n) … #define CAL_CSI2_VC_IRQ_ECC_CORRECTION_IRQ_MASK(n) … #define CAL_CSI2_CTX_DT_MASK … #define CAL_CSI2_CTX_DT_DISABLED … #define CAL_CSI2_CTX_DT_ANY … #define CAL_CSI2_CTX_VC_MASK … #define CAL_CSI2_CTX_CPORT_MASK … #define CAL_CSI2_CTX_ATT_MASK … #define CAL_CSI2_CTX_ATT_PIX … #define CAL_CSI2_CTX_ATT … #define CAL_CSI2_CTX_PACK_MODE_MASK … #define CAL_CSI2_CTX_PACK_MODE_LINE … #define CAL_CSI2_CTX_PACK_MODE_FRAME … #define CAL_CSI2_CTX_LINES_MASK … #define CAL_CSI2_STATUS_FRAME_MASK … #define CAL_CSI2_PHY_REG0_THS_SETTLE_MASK … #define CAL_CSI2_PHY_REG0_THS_TERM_MASK … #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_MASK … #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_DISABLE … #define CAL_CSI2_PHY_REG0_HSCLOCKCONFIG_ENABLE … #define CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK … #define CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK … #define CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK … #define CAL_CSI2_PHY_REG1_TCLK_TERM_MASK … #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_MASK … #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_ERROR … #define CAL_CSI2_PHY_REG1_CLOCK_MISS_DETECTOR_STATUS_SUCCESS … #define CAL_CSI2_PHY_REG1_RESET_DONE_STATUS_MASK … #define CAL_CSI2_PHY_REG10_I933_LDO_DISABLE_MASK … #define CAL_CSI2_PHY_REG2_CCP2_SYNC_PATTERN_MASK … #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC3_MASK … #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC2_MASK … #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC1_MASK … #define CAL_CSI2_PHY_REG2_TRIGGER_CMD_RXTRIGESC0_MASK … #define CM_CAMERRX_CTRL_CSI1_CTRLCLKEN_MASK … #define CM_CAMERRX_CTRL_CSI1_CAMMODE_MASK … #define CM_CAMERRX_CTRL_CSI1_LANEENABLE_MASK … #define CM_CAMERRX_CTRL_CSI1_MODE_MASK … #define CM_CAMERRX_CTRL_CSI0_CTRLCLKEN_MASK … #define CM_CAMERRX_CTRL_CSI0_CAMMODE_MASK … #define CM_CAMERRX_CTRL_CSI0_LANEENABLE_MASK … #define CM_CAMERRX_CTRL_CSI0_MODE_MASK … #endif
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