/* SPDX-License-Identifier: GPL-2.0-only */ /* * Intel Atom SoC Power Management Controller Header File * Copyright (c) 2014-2015,2022 Intel Corporation. */ #ifndef PMC_ATOM_H #define PMC_ATOM_H #include <linux/bits.h> /* ValleyView Power Control Unit PCI Device ID */ #define PCI_DEVICE_ID_VLV_PMC … /* CherryTrail Power Control Unit PCI Device ID */ #define PCI_DEVICE_ID_CHT_PMC … /* PMC Memory mapped IO registers */ #define PMC_BASE_ADDR_OFFSET … #define PMC_BASE_ADDR_MASK … #define PMC_MMIO_REG_LEN … #define PMC_REG_BIT_WIDTH … /* BIOS uses FUNC_DIS to disable specific function */ #define PMC_FUNC_DIS … #define PMC_FUNC_DIS_2 … /* CHT specific bits in FUNC_DIS2 register */ #define BIT_FD_GMM … #define BIT_FD_ISH … /* S0ix wake event control */ #define PMC_S0IX_WAKE_EN … #define BIT_LPC_CLOCK_RUN … #define BIT_SHARED_IRQ_GPSC … #define BIT_ORED_DEDICATED_IRQ_GPSS … #define BIT_ORED_DEDICATED_IRQ_GPSC … #define BIT_SHARED_IRQ_GPSS … #define PMC_WAKE_EN_SETTING … /* External clk generator settings */ #define PMC_CLK_CTL_OFFSET … #define PMC_CLK_CTL_SIZE … #define PMC_CLK_NUM … #define PMC_CLK_CTL_GATED_ON_D3 … #define PMC_CLK_CTL_FORCE_ON … #define PMC_CLK_CTL_FORCE_OFF … #define PMC_CLK_CTL_RESERVED … #define PMC_MASK_CLK_CTL … #define PMC_MASK_CLK_FREQ … #define PMC_CLK_FREQ_XTAL … #define PMC_CLK_FREQ_PLL … /* The timers accumulate time spent in sleep state */ #define PMC_S0IR_TMR … #define PMC_S0I1_TMR … #define PMC_S0I2_TMR … #define PMC_S0I3_TMR … #define PMC_S0_TMR … /* Sleep state counter is in units of 32us */ #define PMC_TMR_SHIFT … /* Power status of power islands */ #define PMC_PSS … #define PMC_PSS_BIT_GBE … #define PMC_PSS_BIT_SATA … #define PMC_PSS_BIT_HDA … #define PMC_PSS_BIT_SEC … #define PMC_PSS_BIT_PCIE … #define PMC_PSS_BIT_LPSS … #define PMC_PSS_BIT_LPE … #define PMC_PSS_BIT_DFX … #define PMC_PSS_BIT_USH_CTRL … #define PMC_PSS_BIT_USH_SUS … #define PMC_PSS_BIT_USH_VCCS … #define PMC_PSS_BIT_USH_VCCA … #define PMC_PSS_BIT_OTG_CTRL … #define PMC_PSS_BIT_OTG_VCCS … #define PMC_PSS_BIT_OTG_VCCA_CLK … #define PMC_PSS_BIT_OTG_VCCA … #define PMC_PSS_BIT_USB … #define PMC_PSS_BIT_USB_SUS … /* CHT specific bits in PSS register */ #define PMC_PSS_BIT_CHT_UFS … #define PMC_PSS_BIT_CHT_UXD … #define PMC_PSS_BIT_CHT_UXD_FD … #define PMC_PSS_BIT_CHT_UX_ENG … #define PMC_PSS_BIT_CHT_USB_SUS … #define PMC_PSS_BIT_CHT_GMM … #define PMC_PSS_BIT_CHT_ISH … #define PMC_PSS_BIT_CHT_DFX_MASTER … #define PMC_PSS_BIT_CHT_DFX_CLUSTER1 … #define PMC_PSS_BIT_CHT_DFX_CLUSTER2 … #define PMC_PSS_BIT_CHT_DFX_CLUSTER3 … #define PMC_PSS_BIT_CHT_DFX_CLUSTER4 … #define PMC_PSS_BIT_CHT_DFX_CLUSTER5 … /* These registers reflect D3 status of functions */ #define PMC_D3_STS_0 … #define BIT_LPSS1_F0_DMA … #define BIT_LPSS1_F1_PWM1 … #define BIT_LPSS1_F2_PWM2 … #define BIT_LPSS1_F3_HSUART1 … #define BIT_LPSS1_F4_HSUART2 … #define BIT_LPSS1_F5_SPI … #define BIT_LPSS1_F6_XXX … #define BIT_LPSS1_F7_XXX … #define BIT_SCC_EMMC … #define BIT_SCC_SDIO … #define BIT_SCC_SDCARD … #define BIT_SCC_MIPI … #define BIT_HDA … #define BIT_LPE … #define BIT_OTG … #define BIT_USH … #define BIT_GBE … #define BIT_SATA … #define BIT_USB_EHCI … #define BIT_SEC … #define BIT_PCIE_PORT0 … #define BIT_PCIE_PORT1 … #define BIT_PCIE_PORT2 … #define BIT_PCIE_PORT3 … #define BIT_LPSS2_F0_DMA … #define BIT_LPSS2_F1_I2C1 … #define BIT_LPSS2_F2_I2C2 … #define BIT_LPSS2_F3_I2C3 … #define BIT_LPSS2_F4_I2C4 … #define BIT_LPSS2_F5_I2C5 … #define BIT_LPSS2_F6_I2C6 … #define BIT_LPSS2_F7_I2C7 … #define PMC_D3_STS_1 … #define BIT_SMB … #define BIT_OTG_SS_PHY … #define BIT_USH_SS_PHY … #define BIT_DFX … /* CHT specific bits in PMC_D3_STS_1 register */ #define BIT_STS_GMM … #define BIT_STS_ISH … /* PMC I/O Registers */ #define ACPI_BASE_ADDR_OFFSET … #define ACPI_BASE_ADDR_MASK … #define ACPI_MMIO_REG_LEN … #define PM1_CNT … #define SLEEP_TYPE_MASK … #define SLEEP_TYPE_S5 … #define SLEEP_ENABLE … extern int pmc_atom_read(int offset, u32 *value); #endif /* PMC_ATOM_H */
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