// SPDX-License-Identifier: GPL-2.0-or-later /* * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit) * * Copyright (C) 2014 Samsung Electronics * Bartlomiej Zolnierkiewicz <[email protected]> * Lukasz Majewski <[email protected]> * * Copyright (C) 2011 Samsung Electronics * Donggeun Kim <[email protected]> * Amit Daniel Kachhap <[email protected]> */ #include <linux/clk.h> #include <linux/io.h> #include <linux/interrupt.h> #include <linux/module.h> #include <linux/of.h> #include <linux/of_address.h> #include <linux/of_irq.h> #include <linux/platform_device.h> #include <linux/regulator/consumer.h> #include <linux/thermal.h> #include <dt-bindings/thermal/thermal_exynos.h> /* Exynos generic registers */ #define EXYNOS_TMU_REG_TRIMINFO … #define EXYNOS_TMU_REG_CONTROL … #define EXYNOS_TMU_REG_STATUS … #define EXYNOS_TMU_REG_CURRENT_TEMP … #define EXYNOS_TMU_REG_INTEN … #define EXYNOS_TMU_REG_INTSTAT … #define EXYNOS_TMU_REG_INTCLEAR … #define EXYNOS_TMU_TEMP_MASK … #define EXYNOS_TMU_REF_VOLTAGE_SHIFT … #define EXYNOS_TMU_REF_VOLTAGE_MASK … #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK … #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT … #define EXYNOS_TMU_CORE_EN_SHIFT … /* Exynos3250 specific registers */ #define EXYNOS_TMU_TRIMINFO_CON1 … /* Exynos4210 specific registers */ #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP … #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 … /* Exynos5250, Exynos4412, Exynos3250 specific registers */ #define EXYNOS_TMU_TRIMINFO_CON2 … #define EXYNOS_THD_TEMP_RISE … #define EXYNOS_THD_TEMP_FALL … #define EXYNOS_EMUL_CON … #define EXYNOS_TRIMINFO_RELOAD_ENABLE … #define EXYNOS_TRIMINFO_25_SHIFT … #define EXYNOS_TRIMINFO_85_SHIFT … #define EXYNOS_TMU_TRIP_MODE_SHIFT … #define EXYNOS_TMU_TRIP_MODE_MASK … #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT … #define EXYNOS_TMU_INTEN_RISE0_SHIFT … #define EXYNOS_TMU_INTEN_FALL0_SHIFT … #define EXYNOS_EMUL_TIME … #define EXYNOS_EMUL_TIME_MASK … #define EXYNOS_EMUL_TIME_SHIFT … #define EXYNOS_EMUL_DATA_SHIFT … #define EXYNOS_EMUL_DATA_MASK … #define EXYNOS_EMUL_ENABLE … /* Exynos5260 specific */ #define EXYNOS5260_TMU_REG_INTEN … #define EXYNOS5260_TMU_REG_INTSTAT … #define EXYNOS5260_TMU_REG_INTCLEAR … #define EXYNOS5260_EMUL_CON … /* Exynos4412 specific */ #define EXYNOS4412_MUX_ADDR_VALUE … #define EXYNOS4412_MUX_ADDR_SHIFT … /* Exynos5433 specific registers */ #define EXYNOS5433_THD_TEMP_RISE3_0 … #define EXYNOS5433_THD_TEMP_RISE7_4 … #define EXYNOS5433_THD_TEMP_FALL3_0 … #define EXYNOS5433_THD_TEMP_FALL7_4 … #define EXYNOS5433_TMU_REG_INTEN … #define EXYNOS5433_TMU_REG_INTPEND … #define EXYNOS5433_TMU_EMUL_CON … #define EXYNOS5433_TMU_PD_DET_EN … #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT … #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT … #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK … #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK … #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING … #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING … #define EXYNOS5433_PD_DET_EN … #define EXYNOS5433_G3D_BASE … /* Exynos7 specific registers */ #define EXYNOS7_THD_TEMP_RISE7_6 … #define EXYNOS7_THD_TEMP_FALL7_6 … #define EXYNOS7_TMU_REG_INTEN … #define EXYNOS7_TMU_REG_INTPEND … #define EXYNOS7_TMU_REG_EMUL_CON … #define EXYNOS7_TMU_TEMP_MASK … #define EXYNOS7_PD_DET_EN_SHIFT … #define EXYNOS7_TMU_INTEN_RISE0_SHIFT … #define EXYNOS7_EMUL_DATA_SHIFT … #define EXYNOS7_EMUL_DATA_MASK … #define EXYNOS_FIRST_POINT_TRIM … #define EXYNOS_SECOND_POINT_TRIM … #define EXYNOS_NOISE_CANCEL_MODE … #define MCELSIUS … enum soc_type { … }; /** * struct exynos_tmu_data : A structure to hold the private data of the TMU * driver * @base: base address of the single instance of the TMU controller. * @base_second: base address of the common registers of the TMU controller. * @irq: irq number of the TMU controller. * @soc: id of the SOC type. * @lock: lock to implement synchronization. * @clk: pointer to the clock structure. * @clk_sec: pointer to the clock structure for accessing the base_second. * @sclk: pointer to the clock structure for accessing the tmu special clk. * @cal_type: calibration type for temperature * @efuse_value: SoC defined fuse value * @min_efuse_value: minimum valid trimming data * @max_efuse_value: maximum valid trimming data * @temp_error1: fused value of the first point trim. * @temp_error2: fused value of the second point trim. * @gain: gain of amplifier in the positive-TC generator block * 0 < gain <= 15 * @reference_voltage: reference voltage of amplifier * in the positive-TC generator block * 0 < reference_voltage <= 31 * @tzd: pointer to thermal_zone_device structure * @enabled: current status of TMU device * @tmu_set_low_temp: SoC specific method to set trip (falling threshold) * @tmu_set_high_temp: SoC specific method to set trip (rising threshold) * @tmu_set_crit_temp: SoC specific method to set critical temperature * @tmu_disable_low: SoC specific method to disable an interrupt (falling threshold) * @tmu_disable_high: SoC specific method to disable an interrupt (rising threshold) * @tmu_initialize: SoC specific TMU initialization method * @tmu_control: SoC specific TMU control method * @tmu_read: SoC specific TMU temperature read method * @tmu_set_emulation: SoC specific TMU emulation setting method * @tmu_clear_irqs: SoC specific TMU interrupts clearing method */ struct exynos_tmu_data { … }; /* * TMU treats temperature as a mapped temperature code. * The temperature is converted differently depending on the calibration type. */ static int temp_to_code(struct exynos_tmu_data *data, u8 temp) { … } /* * Calculate a temperature value from a temperature code. * The unit of the temperature is degree Celsius. */ static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) { … } static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) { … } static int exynos_tmu_initialize(struct platform_device *pdev) { … } static int exynos_thermal_zone_configure(struct platform_device *pdev) { … } static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) { … } static void exynos_tmu_control(struct platform_device *pdev, bool on) { … } static void exynos_tmu_update_bit(struct exynos_tmu_data *data, int reg_off, int bit_off, bool enable) { … } static void exynos_tmu_update_temp(struct exynos_tmu_data *data, int reg_off, int bit_off, u8 temp) { … } static void exynos4210_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4210_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4210_tmu_disable_low(struct exynos_tmu_data *data) { … } static void exynos4210_tmu_disable_high(struct exynos_tmu_data *data) { … } static void exynos4210_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4210_tmu_initialize(struct platform_device *pdev) { … } static void exynos4412_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4412_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4412_tmu_disable_low(struct exynos_tmu_data *data) { … } static void exynos4412_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos4412_tmu_initialize(struct platform_device *pdev) { … } static void exynos5433_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos5433_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos5433_tmu_disable_low(struct exynos_tmu_data *data) { … } static void exynos5433_tmu_disable_high(struct exynos_tmu_data *data) { … } static void exynos5433_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos5433_tmu_initialize(struct platform_device *pdev) { … } static void exynos7_tmu_set_low_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos7_tmu_set_high_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos7_tmu_disable_low(struct exynos_tmu_data *data) { … } static void exynos7_tmu_disable_high(struct exynos_tmu_data *data) { … } static void exynos7_tmu_set_crit_temp(struct exynos_tmu_data *data, u8 temp) { … } static void exynos7_tmu_initialize(struct platform_device *pdev) { … } static void exynos4210_tmu_control(struct platform_device *pdev, bool on) { … } static void exynos5433_tmu_control(struct platform_device *pdev, bool on) { … } static void exynos7_tmu_control(struct platform_device *pdev, bool on) { … } static int exynos_get_temp(struct thermal_zone_device *tz, int *temp) { … } #ifdef CONFIG_THERMAL_EMULATION static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, int temp) { … } static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, int temp) { … } static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) { … } #else #define exynos4412_tmu_set_emulation … static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) { return -EINVAL; } #endif /* CONFIG_THERMAL_EMULATION */ static int exynos4210_tmu_read(struct exynos_tmu_data *data) { … } static int exynos4412_tmu_read(struct exynos_tmu_data *data) { … } static int exynos7_tmu_read(struct exynos_tmu_data *data) { … } static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) { … } static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) { … } static const struct of_device_id exynos_tmu_match[] = …; MODULE_DEVICE_TABLE(of, exynos_tmu_match); static int exynos_map_dt_data(struct platform_device *pdev) { … } static int exynos_set_trips(struct thermal_zone_device *tz, int low, int high) { … } static const struct thermal_zone_device_ops exynos_sensor_ops = …; static int exynos_tmu_probe(struct platform_device *pdev) { … } static void exynos_tmu_remove(struct platform_device *pdev) { … } #ifdef CONFIG_PM_SLEEP static int exynos_tmu_suspend(struct device *dev) { … } static int exynos_tmu_resume(struct device *dev) { … } static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, exynos_tmu_suspend, exynos_tmu_resume); #define EXYNOS_TMU_PM … #else #define EXYNOS_TMU_PM … #endif static struct platform_driver exynos_tmu_driver = …; module_platform_driver(…) …; MODULE_DESCRIPTION(…) …; MODULE_AUTHOR(…) …; MODULE_LICENSE(…) …; MODULE_ALIAS(…) …;
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