// SPDX-License-Identifier: GPL-2.0+ /* * Actions Semi Owl S500 SoC clock driver * * Copyright (c) 2014 Actions Semi Inc. * Author: David Liu <[email protected]> * * Copyright (c) 2018 Linaro Ltd. * Author: Manivannan Sadhasivam <[email protected]> * * Copyright (c) 2018 LSI-TEC - Caninos Loucos * Author: Edgar Bernardi Righi <[email protected]> */ #include <linux/clk-provider.h> #include <linux/platform_device.h> #include "owl-common.h" #include "owl-composite.h" #include "owl-divider.h" #include "owl-factor.h" #include "owl-fixed-factor.h" #include "owl-gate.h" #include "owl-mux.h" #include "owl-pll.h" #include "owl-reset.h" #include <dt-bindings/clock/actions,s500-cmu.h> #include <dt-bindings/reset/actions,s500-reset.h> #define CMU_COREPLL … #define CMU_DEVPLL … #define CMU_DDRPLL … #define CMU_NANDPLL … #define CMU_DISPLAYPLL … #define CMU_AUDIOPLL … #define CMU_TVOUTPLL … #define CMU_BUSCLK … #define CMU_SENSORCLK … #define CMU_LCDCLK … #define CMU_DSICLK … #define CMU_CSICLK … #define CMU_DECLK … #define CMU_BISPCLK … #define CMU_BUSCLK1 … #define CMU_VDECLK … #define CMU_VCECLK … #define CMU_NANDCCLK … #define CMU_SD0CLK … #define CMU_SD1CLK … #define CMU_SD2CLK … #define CMU_UART0CLK … #define CMU_UART1CLK … #define CMU_UART2CLK … #define CMU_PWM4CLK … #define CMU_PWM5CLK … #define CMU_PWM0CLK … #define CMU_PWM1CLK … #define CMU_PWM2CLK … #define CMU_PWM3CLK … #define CMU_USBPLL … #define CMU_ETHERNETPLL … #define CMU_CVBSPLL … #define CMU_LENSCLK … #define CMU_GPU3DCLK … #define CMU_CORECTL … #define CMU_DEVCLKEN0 … #define CMU_DEVCLKEN1 … #define CMU_DEVRST0 … #define CMU_DEVRST1 … #define CMU_UART3CLK … #define CMU_UART4CLK … #define CMU_UART5CLK … #define CMU_UART6CLK … #define CMU_SSCLK … #define CMU_DIGITALDEBUG … #define CMU_ANALOGDEBUG … #define CMU_COREPLLDEBUG … #define CMU_DEVPLLDEBUG … #define CMU_DDRPLLDEBUG … #define CMU_NANDPLLDEBUG … #define CMU_DISPLAYPLLDEBUG … #define CMU_TVOUTPLLDEBUG … #define CMU_DEEPCOLORPLLDEBUG … #define CMU_AUDIOPLL_ETHPLLDEBUG … #define CMU_CVBSPLLDEBUG … #define OWL_S500_COREPLL_DELAY … #define OWL_S500_DDRPLL_DELAY … #define OWL_S500_DEVPLL_DELAY … #define OWL_S500_NANDPLL_DELAY … #define OWL_S500_DISPLAYPLL_DELAY … #define OWL_S500_ETHERNETPLL_DELAY … #define OWL_S500_AUDIOPLL_DELAY … static const struct clk_pll_table clk_audio_pll_table[] = …; /* pll clocks */ static OWL_PLL_NO_PARENT_DELAY(ethernet_pll_clk, "ethernet_pll_clk", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, OWL_S500_ETHERNETPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(core_pll_clk, "core_pll_clk", CMU_COREPLL, 12000000, 9, 0, 8, 4, 134, OWL_S500_COREPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(ddr_pll_clk, "ddr_pll_clk", CMU_DDRPLL, 12000000, 8, 0, 8, 1, 67, OWL_S500_DDRPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(nand_pll_clk, "nand_pll_clk", CMU_NANDPLL, 6000000, 8, 0, 7, 2, 86, OWL_S500_NANDPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(display_pll_clk, "display_pll_clk", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 126, OWL_S500_DISPLAYPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(dev_pll_clk, "dev_pll_clk", CMU_DEVPLL, 6000000, 8, 0, 7, 8, 126, OWL_S500_DEVPLL_DELAY, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT_DELAY(audio_pll_clk, "audio_pll_clk", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, OWL_S500_AUDIOPLL_DELAY, clk_audio_pll_table, CLK_IGNORE_UNUSED); static const char * const dev_clk_mux_p[] = …; static const char * const bisp_clk_mux_p[] = …; static const char * const sensor_clk_mux_p[] = …; static const char * const sd_clk_mux_p[] = …; static const char * const pwm_clk_mux_p[] = …; static const char * const ahbprediv_clk_mux_p[] = …; static const char * const nic_clk_mux_p[] = …; static const char * const uart_clk_mux_p[] = …; static const char * const de_clk_mux_p[] = …; static const char * const i2s_clk_mux_p[] = …; static const char * const hde_clk_mux_p[] = …; static const char * const nand_clk_mux_p[] = …; static struct clk_factor_table sd_factor_table[] = …; static struct clk_factor_table de_factor_table[] = …; static struct clk_factor_table hde_factor_table[] = …; static struct clk_div_table rmii_ref_div_table[] = …; static struct clk_div_table std12rate_div_table[] = …; static struct clk_div_table i2s_div_table[] = …; static struct clk_div_table nand_div_table[] = …; /* mux clock */ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); /* gate clocks */ static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0); static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0); static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED); static OWL_GATE(spi3_clk, "spi3_clk", "ahb_clk", CMU_DEVCLKEN1, 13, 0, CLK_IGNORE_UNUSED); static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0); static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0); /* divider clocks */ static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 2, 2, NULL, 0, 0); static OWL_DIVIDER(apb_clk, "apb_clk", "nic_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0); /* factor clocks */ static OWL_FACTOR(de1_clk, "de_clk1", "de_clk", CMU_DECLK, 0, 4, de_factor_table, 0, 0); static OWL_FACTOR(de2_clk, "de_clk2", "de_clk", CMU_DECLK, 4, 4, de_factor_table, 0, 0); /* composite clocks */ static OWL_COMP_DIV(nic_clk, "nic_clk", nic_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK1, 4, 3), { … }, OWL_DIVIDER_HW(CMU_BUSCLK1, 16, 2, 0, NULL), 0); static OWL_COMP_DIV(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, OWL_MUX_HW(CMU_BUSCLK1, 8, 3), { … }, OWL_DIVIDER_HW(CMU_BUSCLK1, 12, 2, 0, NULL), CLK_SET_RATE_PARENT); static OWL_COMP_FIXED_FACTOR(ahb_clk, "ahb_clk", "h_clk", { … }, 1, 1, 0); static OWL_COMP_FACTOR(vce_clk, "vce_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 26, 0), OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(vde_clk, "vde_clk", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 25, 0), OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_DIV(bisp_clk, "bisp_clk", bisp_clk_mux_p, OWL_MUX_HW(CMU_BISPCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_DIVIDER_HW(CMU_BISPCLK, 0, 4, 0, std12rate_div_table), 0); static OWL_COMP_DIV(sensor0_clk, "sensor0_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, std12rate_div_table), 0); static OWL_COMP_DIV(sensor1_clk, "sensor1_clk", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_DIVIDER_HW(CMU_SENSORCLK, 8, 4, 0, std12rate_div_table), 0); static OWL_COMP_FACTOR(sd0_clk, "sd0_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 5, 0), OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(sd1_clk, "sd1_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD1CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 6, 0), OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(sd2_clk, "sd2_clk", sd_clk_mux_p, OWL_MUX_HW(CMU_SD2CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 7, 0), OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_DIV(pwm0_clk, "pwm0_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM0CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(pwm1_clk, "pwm1_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM1CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 24, 0), OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(pwm2_clk, "pwm2_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM2CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 25, 0), OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(pwm3_clk, "pwm3_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM3CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(pwm4_clk, "pwm4_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM4CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(pwm5_clk, "pwm5_clk", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM5CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), 0); static OWL_COMP_PASS(de_clk, "de_clk", de_clk_mux_p, OWL_MUX_HW(CMU_DECLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), 0); static OWL_COMP_FIXED_FACTOR(i2c0_clk, "i2c0_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c1_clk, "i2c1_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 15, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c2_clk, "i2c2_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 30, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(i2c3_clk, "i2c3_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 5, 0); static OWL_COMP_FIXED_FACTOR(ethernet_clk, "ethernet_clk", "ethernet_pll_clk", OWL_GATE_HW(CMU_DEVCLKEN1, 22, 0), 1, 20, 0); static OWL_COMP_DIV(uart0_clk, "uart0_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 6, 0), OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart1_clk, "uart1_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART1CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 7, 0), OWL_DIVIDER_HW(CMU_UART1CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart2_clk, "uart2_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart3_clk, "uart3_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart4_clk, "uart4_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart5_clk, "uart5_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(uart6_clk, "uart6_clk", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(i2srx_clk, "i2srx_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table), 0); static OWL_COMP_DIV(i2stx_clk, "i2stx_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 20, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table), 0); static OWL_COMP_DIV(hdmia_clk, "hdmia_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, i2s_div_table), 0); static OWL_COMP_DIV(spdif_clk, "spdif_clk", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 28, 4, 0, i2s_div_table), 0); static OWL_COMP_DIV(nand_clk, "nand_clk", nand_clk_mux_p, OWL_MUX_HW(CMU_NANDCCLK, 8, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, nand_div_table), CLK_SET_RATE_PARENT); static OWL_COMP_DIV(ecc_clk, "ecc_clk", nand_clk_mux_p, OWL_MUX_HW(CMU_NANDCCLK, 8, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 4, 0), OWL_DIVIDER_HW(CMU_NANDCCLK, 4, 3, 0, nand_div_table), CLK_SET_RATE_PARENT); static struct owl_clk_common *s500_clks[] = …; static struct clk_hw_onecell_data s500_hw_clks = …; static const struct owl_reset_map s500_resets[] = …; static struct owl_clk_desc s500_clk_desc = …; static int s500_clk_probe(struct platform_device *pdev) { … } static const struct of_device_id s500_clk_of_match[] = …; static struct platform_driver s500_clk_driver = …; static int __init s500_clk_init(void) { … } core_initcall(s500_clk_init);
Codebase Browser
linux