/* SPDX-License-Identifier: GPL-2.0-only */ /* * vmx.h: VMX Architecture related definitions * Copyright (c) 2004, Intel Corporation. * * A few random additions are: * Copyright (C) 2006 Qumranet * Avi Kivity <[email protected]> * Yaniv Kamay <[email protected]> */ #ifndef VMX_H #define VMX_H #include <linux/bitops.h> #include <linux/bug.h> #include <linux/types.h> #include <uapi/asm/vmx.h> #include <asm/trapnr.h> #include <asm/vmxfeatures.h> #define VMCS_CONTROL_BIT(x) … /* * Definitions of Primary Processor-Based VM-Execution Controls. */ #define CPU_BASED_INTR_WINDOW_EXITING … #define CPU_BASED_USE_TSC_OFFSETTING … #define CPU_BASED_HLT_EXITING … #define CPU_BASED_INVLPG_EXITING … #define CPU_BASED_MWAIT_EXITING … #define CPU_BASED_RDPMC_EXITING … #define CPU_BASED_RDTSC_EXITING … #define CPU_BASED_CR3_LOAD_EXITING … #define CPU_BASED_CR3_STORE_EXITING … #define CPU_BASED_ACTIVATE_TERTIARY_CONTROLS … #define CPU_BASED_CR8_LOAD_EXITING … #define CPU_BASED_CR8_STORE_EXITING … #define CPU_BASED_TPR_SHADOW … #define CPU_BASED_NMI_WINDOW_EXITING … #define CPU_BASED_MOV_DR_EXITING … #define CPU_BASED_UNCOND_IO_EXITING … #define CPU_BASED_USE_IO_BITMAPS … #define CPU_BASED_MONITOR_TRAP_FLAG … #define CPU_BASED_USE_MSR_BITMAPS … #define CPU_BASED_MONITOR_EXITING … #define CPU_BASED_PAUSE_EXITING … #define CPU_BASED_ACTIVATE_SECONDARY_CONTROLS … #define CPU_BASED_ALWAYSON_WITHOUT_TRUE_MSR … /* * Definitions of Secondary Processor-Based VM-Execution Controls. */ #define SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES … #define SECONDARY_EXEC_ENABLE_EPT … #define SECONDARY_EXEC_DESC … #define SECONDARY_EXEC_ENABLE_RDTSCP … #define SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE … #define SECONDARY_EXEC_ENABLE_VPID … #define SECONDARY_EXEC_WBINVD_EXITING … #define SECONDARY_EXEC_UNRESTRICTED_GUEST … #define SECONDARY_EXEC_APIC_REGISTER_VIRT … #define SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY … #define SECONDARY_EXEC_PAUSE_LOOP_EXITING … #define SECONDARY_EXEC_RDRAND_EXITING … #define SECONDARY_EXEC_ENABLE_INVPCID … #define SECONDARY_EXEC_ENABLE_VMFUNC … #define SECONDARY_EXEC_SHADOW_VMCS … #define SECONDARY_EXEC_ENCLS_EXITING … #define SECONDARY_EXEC_RDSEED_EXITING … #define SECONDARY_EXEC_ENABLE_PML … #define SECONDARY_EXEC_EPT_VIOLATION_VE … #define SECONDARY_EXEC_PT_CONCEAL_VMX … #define SECONDARY_EXEC_ENABLE_XSAVES … #define SECONDARY_EXEC_MODE_BASED_EPT_EXEC … #define SECONDARY_EXEC_PT_USE_GPA … #define SECONDARY_EXEC_TSC_SCALING … #define SECONDARY_EXEC_ENABLE_USR_WAIT_PAUSE … #define SECONDARY_EXEC_BUS_LOCK_DETECTION … #define SECONDARY_EXEC_NOTIFY_VM_EXITING … /* * Definitions of Tertiary Processor-Based VM-Execution Controls. */ #define TERTIARY_EXEC_IPI_VIRT … #define PIN_BASED_EXT_INTR_MASK … #define PIN_BASED_NMI_EXITING … #define PIN_BASED_VIRTUAL_NMIS … #define PIN_BASED_VMX_PREEMPTION_TIMER … #define PIN_BASED_POSTED_INTR … #define PIN_BASED_ALWAYSON_WITHOUT_TRUE_MSR … #define VM_EXIT_SAVE_DEBUG_CONTROLS … #define VM_EXIT_HOST_ADDR_SPACE_SIZE … #define VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL … #define VM_EXIT_ACK_INTR_ON_EXIT … #define VM_EXIT_SAVE_IA32_PAT … #define VM_EXIT_LOAD_IA32_PAT … #define VM_EXIT_SAVE_IA32_EFER … #define VM_EXIT_LOAD_IA32_EFER … #define VM_EXIT_SAVE_VMX_PREEMPTION_TIMER … #define VM_EXIT_CLEAR_BNDCFGS … #define VM_EXIT_PT_CONCEAL_PIP … #define VM_EXIT_CLEAR_IA32_RTIT_CTL … #define VM_EXIT_ALWAYSON_WITHOUT_TRUE_MSR … #define VM_ENTRY_LOAD_DEBUG_CONTROLS … #define VM_ENTRY_IA32E_MODE … #define VM_ENTRY_SMM … #define VM_ENTRY_DEACT_DUAL_MONITOR … #define VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL … #define VM_ENTRY_LOAD_IA32_PAT … #define VM_ENTRY_LOAD_IA32_EFER … #define VM_ENTRY_LOAD_BNDCFGS … #define VM_ENTRY_PT_CONCEAL_PIP … #define VM_ENTRY_LOAD_IA32_RTIT_CTL … #define VM_ENTRY_ALWAYSON_WITHOUT_TRUE_MSR … /* VMFUNC functions */ #define VMFUNC_CONTROL_BIT(x) … #define VMX_VMFUNC_EPTP_SWITCHING … #define VMFUNC_EPTP_ENTRIES … #define VMX_BASIC_32BIT_PHYS_ADDR_ONLY … #define VMX_BASIC_DUAL_MONITOR_TREATMENT … #define VMX_BASIC_INOUT … #define VMX_BASIC_TRUE_CTLS … static inline u32 vmx_basic_vmcs_revision_id(u64 vmx_basic) { … } static inline u32 vmx_basic_vmcs_size(u64 vmx_basic) { … } static inline u32 vmx_basic_vmcs_mem_type(u64 vmx_basic) { … } static inline u64 vmx_basic_encode_vmcs_info(u32 revision, u16 size, u8 memtype) { … } #define VMX_MISC_SAVE_EFER_LMA … #define VMX_MISC_ACTIVITY_HLT … #define VMX_MISC_ACTIVITY_SHUTDOWN … #define VMX_MISC_ACTIVITY_WAIT_SIPI … #define VMX_MISC_INTEL_PT … #define VMX_MISC_RDMSR_IN_SMM … #define VMX_MISC_VMXOFF_BLOCK_SMI … #define VMX_MISC_VMWRITE_SHADOW_RO_FIELDS … #define VMX_MISC_ZERO_LEN_INS … #define VMX_MISC_MSR_LIST_MULTIPLIER … static inline int vmx_misc_preemption_timer_rate(u64 vmx_misc) { … } static inline int vmx_misc_cr3_count(u64 vmx_misc) { … } static inline int vmx_misc_max_msr(u64 vmx_misc) { … } static inline int vmx_misc_mseg_revid(u64 vmx_misc) { … } /* VMCS Encodings */ enum vmcs_field { … }; /* * Interruption-information format */ #define INTR_INFO_VECTOR_MASK … #define INTR_INFO_INTR_TYPE_MASK … #define INTR_INFO_DELIVER_CODE_MASK … #define INTR_INFO_UNBLOCK_NMI … #define INTR_INFO_VALID_MASK … #define INTR_INFO_RESVD_BITS_MASK … #define VECTORING_INFO_VECTOR_MASK … #define VECTORING_INFO_TYPE_MASK … #define VECTORING_INFO_DELIVER_CODE_MASK … #define VECTORING_INFO_VALID_MASK … #define INTR_TYPE_EXT_INTR … #define INTR_TYPE_RESERVED … #define INTR_TYPE_NMI_INTR … #define INTR_TYPE_HARD_EXCEPTION … #define INTR_TYPE_SOFT_INTR … #define INTR_TYPE_PRIV_SW_EXCEPTION … #define INTR_TYPE_SOFT_EXCEPTION … #define INTR_TYPE_OTHER_EVENT … /* GUEST_INTERRUPTIBILITY_INFO flags. */ #define GUEST_INTR_STATE_STI … #define GUEST_INTR_STATE_MOV_SS … #define GUEST_INTR_STATE_SMI … #define GUEST_INTR_STATE_NMI … #define GUEST_INTR_STATE_ENCLAVE_INTR … /* GUEST_ACTIVITY_STATE flags */ #define GUEST_ACTIVITY_ACTIVE … #define GUEST_ACTIVITY_HLT … #define GUEST_ACTIVITY_SHUTDOWN … #define GUEST_ACTIVITY_WAIT_SIPI … /* * Exit Qualifications for MOV for Control Register Access */ #define CONTROL_REG_ACCESS_NUM … #define CONTROL_REG_ACCESS_TYPE … #define CONTROL_REG_ACCESS_REG … #define LMSW_SOURCE_DATA_SHIFT … #define LMSW_SOURCE_DATA … #define REG_EAX … #define REG_ECX … #define REG_EDX … #define REG_EBX … #define REG_ESP … #define REG_EBP … #define REG_ESI … #define REG_EDI … #define REG_R8 … #define REG_R9 … #define REG_R10 … #define REG_R11 … #define REG_R12 … #define REG_R13 … #define REG_R14 … #define REG_R15 … /* * Exit Qualifications for MOV for Debug Register Access */ #define DEBUG_REG_ACCESS_NUM … #define DEBUG_REG_ACCESS_TYPE … #define TYPE_MOV_TO_DR … #define TYPE_MOV_FROM_DR … #define DEBUG_REG_ACCESS_REG(eq) … /* * Exit Qualifications for APIC-Access */ #define APIC_ACCESS_OFFSET … #define APIC_ACCESS_TYPE … #define TYPE_LINEAR_APIC_INST_READ … #define TYPE_LINEAR_APIC_INST_WRITE … #define TYPE_LINEAR_APIC_INST_FETCH … #define TYPE_LINEAR_APIC_EVENT … #define TYPE_PHYSICAL_APIC_EVENT … #define TYPE_PHYSICAL_APIC_INST … /* segment AR in VMCS -- these are different from what LAR reports */ #define VMX_SEGMENT_AR_L_MASK … #define VMX_AR_TYPE_ACCESSES_MASK … #define VMX_AR_TYPE_READABLE_MASK … #define VMX_AR_TYPE_WRITEABLE_MASK … #define VMX_AR_TYPE_CODE_MASK … #define VMX_AR_TYPE_MASK … #define VMX_AR_TYPE_BUSY_64_TSS … #define VMX_AR_TYPE_BUSY_32_TSS … #define VMX_AR_TYPE_BUSY_16_TSS … #define VMX_AR_TYPE_LDT … #define VMX_AR_UNUSABLE_MASK … #define VMX_AR_S_MASK … #define VMX_AR_P_MASK … #define VMX_AR_L_MASK … #define VMX_AR_DB_MASK … #define VMX_AR_G_MASK … #define VMX_AR_DPL_SHIFT … #define VMX_AR_DPL(ar) … #define VMX_AR_RESERVD_MASK … #define TSS_PRIVATE_MEMSLOT … #define APIC_ACCESS_PAGE_PRIVATE_MEMSLOT … #define IDENTITY_PAGETABLE_PRIVATE_MEMSLOT … #define VMX_NR_VPIDS … #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR … #define VMX_VPID_EXTENT_SINGLE_CONTEXT … #define VMX_VPID_EXTENT_ALL_CONTEXT … #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL … #define VMX_EPT_EXTENT_CONTEXT … #define VMX_EPT_EXTENT_GLOBAL … #define VMX_EPT_EXTENT_SHIFT … #define VMX_EPT_EXECUTE_ONLY_BIT … #define VMX_EPT_PAGE_WALK_4_BIT … #define VMX_EPT_PAGE_WALK_5_BIT … #define VMX_EPTP_UC_BIT … #define VMX_EPTP_WB_BIT … #define VMX_EPT_2MB_PAGE_BIT … #define VMX_EPT_1GB_PAGE_BIT … #define VMX_EPT_INVEPT_BIT … #define VMX_EPT_AD_BIT … #define VMX_EPT_EXTENT_CONTEXT_BIT … #define VMX_EPT_EXTENT_GLOBAL_BIT … #define VMX_VPID_INVVPID_BIT … #define VMX_VPID_EXTENT_INDIVIDUAL_ADDR_BIT … #define VMX_VPID_EXTENT_SINGLE_CONTEXT_BIT … #define VMX_VPID_EXTENT_GLOBAL_CONTEXT_BIT … #define VMX_VPID_EXTENT_SINGLE_NON_GLOBAL_BIT … #define VMX_EPT_MT_EPTE_SHIFT … #define VMX_EPTP_PWL_MASK … #define VMX_EPTP_PWL_4 … #define VMX_EPTP_PWL_5 … #define VMX_EPTP_AD_ENABLE_BIT … /* The EPTP memtype is encoded in bits 2:0, i.e. doesn't need to be shifted. */ #define VMX_EPTP_MT_MASK … #define VMX_EPTP_MT_WB … #define VMX_EPTP_MT_UC … #define VMX_EPT_READABLE_MASK … #define VMX_EPT_WRITABLE_MASK … #define VMX_EPT_EXECUTABLE_MASK … #define VMX_EPT_IPAT_BIT … #define VMX_EPT_ACCESS_BIT … #define VMX_EPT_DIRTY_BIT … #define VMX_EPT_SUPPRESS_VE_BIT … #define VMX_EPT_RWX_MASK … #define VMX_EPT_MT_MASK … static inline u8 vmx_eptp_page_walk_level(u64 eptp) { … } /* The mask to use to trigger an EPT Misconfiguration in order to track MMIO */ #define VMX_EPT_MISCONFIG_WX_VALUE … #define VMX_EPT_IDENTITY_PAGETABLE_ADDR … struct vmx_msr_entry { … } __aligned(…); /* * Exit Qualifications for entry failure during or after loading guest state */ enum vm_entry_failure_code { … }; /* * Exit Qualifications for EPT Violations */ #define EPT_VIOLATION_ACC_READ_BIT … #define EPT_VIOLATION_ACC_WRITE_BIT … #define EPT_VIOLATION_ACC_INSTR_BIT … #define EPT_VIOLATION_RWX_SHIFT … #define EPT_VIOLATION_GVA_IS_VALID_BIT … #define EPT_VIOLATION_GVA_TRANSLATED_BIT … #define EPT_VIOLATION_ACC_READ … #define EPT_VIOLATION_ACC_WRITE … #define EPT_VIOLATION_ACC_INSTR … #define EPT_VIOLATION_RWX_MASK … #define EPT_VIOLATION_GVA_IS_VALID … #define EPT_VIOLATION_GVA_TRANSLATED … /* * Exit Qualifications for NOTIFY VM EXIT */ #define NOTIFY_VM_CONTEXT_INVALID … /* * VM-instruction error numbers */ enum vm_instruction_error_number { … }; /* * VM-instruction errors that can be encountered on VM-Enter, used to trace * nested VM-Enter failures reported by hardware. Errors unique to VM-Enter * from a SMI Transfer Monitor are not included as things have gone seriously * sideways if we get one of those... */ #define VMX_VMENTER_INSTRUCTION_ERRORS … enum vmx_l1d_flush_state { … }; extern enum vmx_l1d_flush_state l1tf_vmx_mitigation; struct vmx_ve_information { … }; #endif
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