// SPDX-License-Identifier: GPL-2.0+ /* * Actions Semi S700 clock driver * * Copyright (c) 2014 Actions Semi Inc. * Author: David Liu <[email protected]> * * Author: Pathiban Nallathambi <[email protected]> * Author: Saravanan Sekar <[email protected]> */ #include <linux/clk-provider.h> #include <linux/platform_device.h> #include "owl-common.h" #include "owl-composite.h" #include "owl-divider.h" #include "owl-factor.h" #include "owl-fixed-factor.h" #include "owl-gate.h" #include "owl-mux.h" #include "owl-pll.h" #include "owl-reset.h" #include <dt-bindings/clock/actions,s700-cmu.h> #include <dt-bindings/reset/actions,s700-reset.h> #define CMU_COREPLL … #define CMU_DEVPLL … #define CMU_DDRPLL … #define CMU_NANDPLL … #define CMU_DISPLAYPLL … #define CMU_AUDIOPLL … #define CMU_TVOUTPLL … #define CMU_BUSCLK … #define CMU_SENSORCLK … #define CMU_LCDCLK … #define CMU_DSIPLLCLK … #define CMU_CSICLK … #define CMU_DECLK … #define CMU_SICLK … #define CMU_BUSCLK1 … #define CMU_HDECLK … #define CMU_VDECLK … #define CMU_VCECLK … #define CMU_NANDCCLK … #define CMU_SD0CLK … #define CMU_SD1CLK … #define CMU_SD2CLK … #define CMU_UART0CLK … #define CMU_UART1CLK … #define CMU_UART2CLK … #define CMU_UART3CLK … #define CMU_UART4CLK … #define CMU_UART5CLK … #define CMU_UART6CLK … #define CMU_PWM0CLK … #define CMU_PWM1CLK … #define CMU_PWM2CLK … #define CMU_PWM3CLK … #define CMU_PWM4CLK … #define CMU_PWM5CLK … #define CMU_GPU3DCLK … #define CMU_CORECTL … #define CMU_DEVCLKEN0 … #define CMU_DEVCLKEN1 … #define CMU_DEVRST0 … #define CMU_DEVRST1 … #define CMU_USBPLL … #define CMU_ETHERNETPLL … #define CMU_CVBSPLL … #define CMU_SSTSCLK … static struct clk_pll_table clk_audio_pll_table[] = …; static struct clk_pll_table clk_cvbs_pll_table[] = …; /* pll clocks */ static OWL_PLL_NO_PARENT(clk_core_pll, "core_pll", CMU_COREPLL, 12000000, 9, 0, 8, 4, 174, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_dev_pll, "dev_pll", CMU_DEVPLL, 6000000, 8, 0, 8, 8, 126, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_ddr_pll, "ddr_pll", CMU_DDRPLL, 6000000, 8, 0, 8, 2, 180, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_nand_pll, "nand_pll", CMU_NANDPLL, 6000000, 8, 0, 8, 2, 86, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_display_pll, "display_pll", CMU_DISPLAYPLL, 6000000, 8, 0, 8, 2, 140, NULL, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_cvbs_pll, "cvbs_pll", CMU_CVBSPLL, 0, 8, 0, 8, 27, 43, clk_cvbs_pll_table, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_audio_pll, "audio_pll", CMU_AUDIOPLL, 0, 4, 0, 1, 0, 0, clk_audio_pll_table, CLK_IGNORE_UNUSED); static OWL_PLL_NO_PARENT(clk_ethernet_pll, "ethernet_pll", CMU_ETHERNETPLL, 500000000, 0, 0, 0, 0, 0, NULL, CLK_IGNORE_UNUSED); static const char *cpu_clk_mux_p[] = …; static const char *dev_clk_p[] = …; static const char *noc_clk_mux_p[] = …; static const char *csi_clk_mux_p[] = …; static const char *de_clk_mux_p[] = …; static const char *hde_clk_mux_p[] = …; static const char *nand_clk_mux_p[] = …; static const char *sd_clk_mux_p[] = …; static const char *uart_clk_mux_p[] = …; static const char *pwm_clk_mux_p[] = …; static const char *gpu_clk_mux_p[] = …; static const char *lcd_clk_mux_p[] = …; static const char *i2s_clk_mux_p[] = …; static const char *sensor_clk_mux_p[] = …; /* mux clocks */ static OWL_MUX(clk_cpu, "cpu_clk", cpu_clk_mux_p, CMU_BUSCLK, 0, 2, CLK_SET_RATE_PARENT); static OWL_MUX(clk_dev, "dev_clk", dev_clk_p, CMU_DEVPLL, 12, 1, CLK_SET_RATE_PARENT); static OWL_MUX(clk_noc0_clk_mux, "noc0_clk_mux", noc_clk_mux_p, CMU_BUSCLK, 4, 3, CLK_SET_RATE_PARENT); static OWL_MUX(clk_noc1_clk_mux, "noc1_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 4, 3, CLK_SET_RATE_PARENT); static OWL_MUX(clk_hp_clk_mux, "hp_clk_mux", noc_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT); static struct clk_factor_table sd_factor_table[] = …; static struct clk_factor_table lcd_factor_table[] = …; static struct clk_div_table hdmia_div_table[] = …; static struct clk_div_table rmii_div_table[] = …; /* divider clocks */ static OWL_DIVIDER(clk_noc0, "noc0_clk", "noc0_clk_mux", CMU_BUSCLK, 16, 2, NULL, 0, 0); static OWL_DIVIDER(clk_noc1, "noc1_clk", "noc1_clk_mux", CMU_BUSCLK1, 16, 2, NULL, 0, 0); static OWL_DIVIDER(clk_noc1_clk_div, "noc1_clk_div", "noc1_clk", CMU_BUSCLK1, 20, 1, NULL, 0, 0); static OWL_DIVIDER(clk_hp_clk_div, "hp_clk_div", "hp_clk_mux", CMU_BUSCLK1, 12, 2, NULL, 0, 0); static OWL_DIVIDER(clk_ahb, "ahb_clk", "hp_clk_div", CMU_BUSCLK1, 2, 2, NULL, 0, 0); static OWL_DIVIDER(clk_apb, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0); static OWL_DIVIDER(clk_sensor0, "sensor0", "sensor_src", CMU_SENSORCLK, 0, 4, NULL, 0, 0); static OWL_DIVIDER(clk_sensor1, "sensor1", "sensor_src", CMU_SENSORCLK, 8, 4, NULL, 0, 0); static OWL_DIVIDER(clk_rmii_ref, "rmii_ref", "ethernet_pll", CMU_ETHERNETPLL, 2, 1, rmii_div_table, 0, 0); static struct clk_factor_table de_factor_table[] = …; static struct clk_factor_table hde_factor_table[] = …; /* gate clocks */ static OWL_GATE(clk_gpio, "gpio", "apb_clk", CMU_DEVCLKEN1, 25, 0, 0); static OWL_GATE(clk_dmac, "dmac", "hp_clk_div", CMU_DEVCLKEN0, 17, 0, 0); static OWL_GATE(clk_timer, "timer", "hosc", CMU_DEVCLKEN1, 22, 0, 0); static OWL_GATE_NO_PARENT(clk_dsi, "dsi_clk", CMU_DEVCLKEN0, 2, 0, 0); static OWL_GATE_NO_PARENT(clk_tvout, "tvout_clk", CMU_DEVCLKEN0, 3, 0, 0); static OWL_GATE_NO_PARENT(clk_hdmi_dev, "hdmi_dev", CMU_DEVCLKEN0, 5, 0, 0); static OWL_GATE_NO_PARENT(clk_usb3_480mpll0, "usb3_480mpll0", CMU_USBPLL, 3, 0, 0); static OWL_GATE_NO_PARENT(clk_usb3_480mphy0, "usb3_480mphy0", CMU_USBPLL, 2, 0, 0); static OWL_GATE_NO_PARENT(clk_usb3_5gphy, "usb3_5gphy", CMU_USBPLL, 1, 0, 0); static OWL_GATE_NO_PARENT(clk_usb3_cce, "usb3_cce", CMU_DEVCLKEN0, 25, 0, 0); static OWL_GATE(clk_i2c0, "i2c0", "hosc", CMU_DEVCLKEN1, 0, 0, 0); static OWL_GATE(clk_i2c1, "i2c1", "hosc", CMU_DEVCLKEN1, 1, 0, 0); static OWL_GATE(clk_i2c2, "i2c2", "hosc", CMU_DEVCLKEN1, 2, 0, 0); static OWL_GATE(clk_i2c3, "i2c3", "hosc", CMU_DEVCLKEN1, 3, 0, 0); static OWL_GATE(clk_spi0, "spi0", "ahb_clk", CMU_DEVCLKEN1, 4, 0, 0); static OWL_GATE(clk_spi1, "spi1", "ahb_clk", CMU_DEVCLKEN1, 5, 0, 0); static OWL_GATE(clk_spi2, "spi2", "ahb_clk", CMU_DEVCLKEN1, 6, 0, 0); static OWL_GATE(clk_spi3, "spi3", "ahb_clk", CMU_DEVCLKEN1, 7, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h0_pllen, "usbh0_pllen", CMU_USBPLL, 12, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h0_phy, "usbh0_phy", CMU_USBPLL, 10, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h0_cce, "usbh0_cce", CMU_DEVCLKEN0, 26, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h1_pllen, "usbh1_pllen", CMU_USBPLL, 13, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h1_phy, "usbh1_phy", CMU_USBPLL, 11, 0, 0); static OWL_GATE_NO_PARENT(clk_usb2h1_cce, "usbh1_cce", CMU_DEVCLKEN0, 27, 0, 0); static OWL_GATE_NO_PARENT(clk_irc_switch, "irc_switch", CMU_DEVCLKEN1, 15, 0, 0); /* composite clocks */ static OWL_COMP_DIV(clk_csi, "csi", csi_clk_mux_p, OWL_MUX_HW(CMU_CSICLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 13, 0), OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL), 0); static OWL_COMP_DIV(clk_si, "si", csi_clk_mux_p, OWL_MUX_HW(CMU_SICLK, 4, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 14, 0), OWL_DIVIDER_HW(CMU_SICLK, 0, 4, 0, NULL), 0); static OWL_COMP_FACTOR(clk_de, "de", de_clk_mux_p, OWL_MUX_HW(CMU_DECLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 0, 0), OWL_FACTOR_HW(CMU_DECLK, 0, 3, 0, de_factor_table), 0); static OWL_COMP_FACTOR(clk_hde, "hde", hde_clk_mux_p, OWL_MUX_HW(CMU_HDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 9, 0), OWL_FACTOR_HW(CMU_HDECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(clk_vde, "vde", hde_clk_mux_p, OWL_MUX_HW(CMU_VDECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 10, 0), OWL_FACTOR_HW(CMU_VDECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(clk_vce, "vce", hde_clk_mux_p, OWL_MUX_HW(CMU_VCECLK, 4, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 11, 0), OWL_FACTOR_HW(CMU_VCECLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_DIV(clk_nand, "nand", nand_clk_mux_p, OWL_MUX_HW(CMU_NANDCCLK, 8, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 21, 0), OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 3, 0, NULL), CLK_SET_RATE_PARENT); static OWL_COMP_FACTOR(clk_sd0, "sd0", sd_clk_mux_p, OWL_MUX_HW(CMU_SD0CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 22, 0), OWL_FACTOR_HW(CMU_SD0CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(clk_sd1, "sd1", sd_clk_mux_p, OWL_MUX_HW(CMU_SD1CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 23, 0), OWL_FACTOR_HW(CMU_SD1CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_FACTOR(clk_sd2, "sd2", sd_clk_mux_p, OWL_MUX_HW(CMU_SD2CLK, 9, 1), OWL_GATE_HW(CMU_DEVCLKEN0, 24, 0), OWL_FACTOR_HW(CMU_SD2CLK, 0, 9, 0, sd_factor_table), 0); static OWL_COMP_DIV(clk_uart0, "uart0", uart_clk_mux_p, OWL_MUX_HW(CMU_UART0CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 8, 0), OWL_DIVIDER_HW(CMU_UART0CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart1, "uart1", uart_clk_mux_p, OWL_MUX_HW(CMU_UART1CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 9, 0), OWL_DIVIDER_HW(CMU_UART1CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart2, "uart2", uart_clk_mux_p, OWL_MUX_HW(CMU_UART2CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 10, 0), OWL_DIVIDER_HW(CMU_UART2CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart3, "uart3", uart_clk_mux_p, OWL_MUX_HW(CMU_UART3CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 11, 0), OWL_DIVIDER_HW(CMU_UART3CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart4, "uart4", uart_clk_mux_p, OWL_MUX_HW(CMU_UART4CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 12, 0), OWL_DIVIDER_HW(CMU_UART4CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart5, "uart5", uart_clk_mux_p, OWL_MUX_HW(CMU_UART5CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 13, 0), OWL_DIVIDER_HW(CMU_UART5CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_uart6, "uart6", uart_clk_mux_p, OWL_MUX_HW(CMU_UART6CLK, 16, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 14, 0), OWL_DIVIDER_HW(CMU_UART6CLK, 0, 9, CLK_DIVIDER_ROUND_CLOSEST, NULL), 0); static OWL_COMP_DIV(clk_pwm0, "pwm0", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM0CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 16, 0), OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 10, 0, NULL), CLK_IGNORE_UNUSED); static OWL_COMP_DIV(clk_pwm1, "pwm1", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM1CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 17, 0), OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(clk_pwm2, "pwm2", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM2CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 18, 0), OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(clk_pwm3, "pwm3", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM3CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 19, 0), OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(clk_pwm4, "pwm4", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM4CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 20, 0), OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 10, 0, NULL), 0); static OWL_COMP_DIV(clk_pwm5, "pwm5", pwm_clk_mux_p, OWL_MUX_HW(CMU_PWM5CLK, 12, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 21, 0), OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 10, 0, NULL), 0); static OWL_COMP_FACTOR(clk_gpu3d, "gpu3d", gpu_clk_mux_p, OWL_MUX_HW(CMU_GPU3DCLK, 4, 3), OWL_GATE_HW(CMU_DEVCLKEN0, 8, 0), OWL_FACTOR_HW(CMU_GPU3DCLK, 0, 3, 0, hde_factor_table), 0); static OWL_COMP_FACTOR(clk_lcd, "lcd", lcd_clk_mux_p, OWL_MUX_HW(CMU_LCDCLK, 12, 2), OWL_GATE_HW(CMU_DEVCLKEN0, 1, 0), OWL_FACTOR_HW(CMU_LCDCLK, 0, 9, 0, lcd_factor_table), 0); static OWL_COMP_DIV(clk_hdmi_audio, "hdmia", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), /*CMU_AUDIOPLL 24,1 unused*/ OWL_GATE_HW(CMU_DEVCLKEN1, 28, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table), 0); static OWL_COMP_DIV(clk_i2srx, "i2srx", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 27, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, hdmia_div_table), 0); static OWL_COMP_DIV(clk_i2stx, "i2stx", i2s_clk_mux_p, OWL_MUX_HW(CMU_AUDIOPLL, 24, 1), OWL_GATE_HW(CMU_DEVCLKEN1, 26, 0), OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, hdmia_div_table), 0); /* for bluetooth pcm communication */ static OWL_COMP_FIXED_FACTOR(clk_pcm1, "pcm1", "audio_pll", OWL_GATE_HW(CMU_DEVCLKEN1, 31, 0), 1, 2, 0); static OWL_COMP_DIV(clk_sensor_src, "sensor_src", sensor_clk_mux_p, OWL_MUX_HW(CMU_SENSORCLK, 4, 1), { … }, OWL_DIVIDER_HW(CMU_SENSORCLK, 5, 2, 0, NULL), 0); static OWL_COMP_FIXED_FACTOR(clk_ethernet, "ethernet", "ethernet_pll", OWL_GATE_HW(CMU_DEVCLKEN1, 23, 0), 1, 20, 0); static OWL_COMP_DIV_FIXED(clk_thermal_sensor, "thermal_sensor", "hosc", OWL_GATE_HW(CMU_DEVCLKEN0, 31, 0), OWL_DIVIDER_HW(CMU_SSTSCLK, 20, 10, 0, NULL), 0); static struct owl_clk_common *s700_clks[] = …; static struct clk_hw_onecell_data s700_hw_clks = …; static const struct owl_reset_map s700_resets[] = …; static struct owl_clk_desc s700_clk_desc = …; static int s700_clk_probe(struct platform_device *pdev) { … } static const struct of_device_id s700_clk_of_match[] = …; static struct platform_driver s700_clk_driver = …; static int __init s700_clk_init(void) { … } core_initcall(s700_clk_init);
Codebase Browser
linux